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SM8150 and SM8250 dispcc drivers

PATCH Applied Jonathan Marek 3 participants 6 messages Sep 27, 2020 – Oct 14, 2020

Subsystems (4)
Device tree bindings Arm Qualcomm mailing list Common clk Qualcomm clock drivers
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Jonathan Marek

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#0 lore raw

v4 cover SM8150 and SM8250 dispcc drivers

Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs.

Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream

v3:
- combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too
- use the right order in drivers/clk/qcom/Kconfig

v4:
- Dropped combining yaml with sdm845/sc7180 dispcc
- Combined drivers into one (sm8250 driver + patched pll config for sm8150)
- Dropped uses of CLK_GET_RATE_NOCACHE (which was copied from downstream)
- Dropped CLK_SET_RATE_PARENT from some DP clocks (upstream phy design)

Jonathan Marek (2):
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150 and SM8250

 .../bindings/clock/qcom,dispcc-sm8x50.yaml    |   93 ++
 drivers/clk/qcom/Kconfig                      |    9 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/dispcc-sm8250.c              | 1107 +++++++++++++++++
 .../dt-bindings/clock/qcom,dispcc-sm8150.h    |    1 +
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    |   66 +
 6 files changed, 1277 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
 create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
 create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8150.h
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
Signature · 1 line
2.26.1
author
#1 lore raw

PATCH v4 1/2 dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 and SM8250 SoCs.

Signed-off-by Jonathan Marek <[email protected]>
Tested-by Dmitry Baryshkov <[email protected]> (SM8250)
---
 .../bindings/clock/qcom,dispcc-sm8x50.yaml    | 93 +++++++++++++++++++
 .../dt-bindings/clock/qcom,dispcc-sm8150.h    |  1 +
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    | 66 +++++++++++++
 3 files changed, 160 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
 create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8150.h
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml new file +93 -0
new file mode 100644
index 000000000000..0cdf53f41f84
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+  - Jonathan Marek <[email protected]>
+
+description: |
+  Qualcomm display clock control module which supports the clocks, resets and
+  power domains on SM8150 and SM8250.
+
+  See also:
+    dt-bindings/clock/qcom,dispcc-sm8150.h
+    dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm8150-dispcc
+      - qcom,sm8250-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY0
+      - description: Byte clock from DSI PHY1
+      - description: Pixel clock from DSI PHY1
+      - description: Link clock from DP PHY
+      - description: VCO DIV clock from DP PHY
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: dsi0_phy_pll_out_byteclk
+      - const: dsi0_phy_pll_out_dsiclk
+      - const: dsi1_phy_pll_out_byteclk
+      - const: dsi1_phy_pll_out_dsiclk
+      - const: dp_phy_pll_link_clk
+      - const: dp_phy_pll_vco_div_clk
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@af00000 {
+      compatible = "qcom,sm8250-dispcc";
+      reg = <0x0af00000 0x10000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&dsi0_phy 0>,
+               <&dsi0_phy 1>,
+               <&dsi1_phy 0>,
+               <&dsi1_phy 1>,
+               <&dp_phy 0>,
+               <&dp_phy 1>;
+      clock-names = "bi_tcxo",
+                    "dsi0_phy_pll_out_byteclk",
+                    "dsi0_phy_pll_out_dsiclk",
+                    "dsi1_phy_pll_out_byteclk",
+                    "dsi1_phy_pll_out_dsiclk",
+                    "dp_phy_pll_link_clk",
+                    "dp_phy_pll_vco_div_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
include/dt-bindings/clock/qcom,dispcc-sm8150.h new file +1 -0
new file mode 120000
index 000000000000..0312b4544acb
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
include/dt-bindings/clock/qcom,dispcc-sm8250.h new file +66 -0

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Signature · 1 line
2.26.1
maintainer Reviewed-by on v4 1/2
#2 lore raw

Re: [PATCH v4 1/2] dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings

Quoted 5 lines · Jonathan Marek

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 and SM8250 SoCs.

Signed-off-by Jonathan Marek <[email protected]>
Tested-by Dmitry Baryshkov <[email protected]> (SM8250)
Quoted 9 lines
---
 .../bindings/clock/qcom,dispcc-sm8x50.yaml    | 93 +++++++++++++++++++
 .../dt-bindings/clock/qcom,dispcc-sm8150.h    |  1 +
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    | 66 +++++++++++++
 3 files changed, 160 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
 create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8150.h
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
Reviewed-by Rob Herring <[email protected]>
author
#4 lore raw

PATCH v4 2/2 clk: qcom: Add display clock controller driver for SM8150 and SM8250

In reply to Jonathan Marek

Add support for the display clock controller found on SM8150 and SM8250.

Signed-off-by Jonathan Marek <[email protected]>
Tested-by Dmitry Baryshkov <[email protected]> (SM8250)
---
 drivers/clk/qcom/Kconfig         |    9 +
 drivers/clk/qcom/Makefile        |    1 +
 drivers/clk/qcom/dispcc-sm8250.c | 1107 ++++++++++++++++++++++++++++++
 3 files changed, 1117 insertions(+)
 create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
drivers/clk/qcom/Kconfig +9 -0
index 058327310c25..c4f1c5c4c442 100644
@@ -413,6 +413,15 @@ config SDM_LPASSCC_845
 	  Say Y if you want to use the LPASS branch clocks of the LPASS clock
 	  controller to reset the LPASS subsystem.
 
+config SM_DISPCC_8250
+	tristate "SM8150 and SM8250 Display Clock Controller"
+	depends on SM_GCC_8150 || SM_GCC_8250
+	help
+	  Support for the display clock controller on Qualcomm Technologies, Inc
+	  SM8150 and SM8250 devices.
+	  Say Y if you want to support display devices and functionality such as
+	  splash screen.
+
 config SM_GCC_8150
 	tristate "SM8150 Global Clock Controller"
 	help
drivers/clk/qcom/Makefile +1 -0
index 9677e769e7e9..d3c72354cb27 100644
@@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
 obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
+obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
drivers/clk/qcom/dispcc-sm8250.c new file +1107 -0

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