Modify ASPEED SoC some default clks are critical

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---
 drivers/clk/clk-aspeed.c  | 8 ++++----
 drivers/clk/clk-ast2600.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

drivers/clk/clk-aspeed.c +1 -1

index 411ff5fb2c07..d348c4fd3f9f 100644
@@ -54,15 +54,15 @@ static const struct aspeed_gate_data aspeed_gates[] = {
        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",          NULL,   CLK_IS_CRITICAL }, /* DAC */
        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",        "clkin", CLK_IS_CRITICAL },
        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",     NULL,   0 }, /* USB2.0 Host port 2 */
-       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",          NULL,   0 }, /* LPC */
+       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",          NULL,   CLK_IS_CRITICAL }, /* LPC */
        [ASPEED_CLK_GATE_USBUHCICLK] =  {  9, 15, "usb-uhci-gate",      NULL,   0 }, /* USB1.1 (requires port 2 enabled) */

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_MAC1CLK] =     { 20, 11, "mac1clk-gate",       "mac",  0 }, /* MAC1 */
        [ASPEED_CLK_GATE_MAC2CLK] =     { 21, 12, "mac2clk-gate",       "mac",  0 }, /* MAC2 */
        [ASPEED_CLK_GATE_RSACLK] =      { 24, -1, "rsaclk-gate",        NULL,   0 }, /* RSA */

drivers/clk/clk-ast2600.c +4 -5

index bbacaccad554..6802a2d5bbe2 100644
@@ -86,8 +86,8 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
        /* Reserved 26 */
        [ASPEED_CLK_GATE_EMMCCLK]       = { 27, 16, "emmcclk-gate",     NULL,    0 },   /* For card clk */
        /* Reserved 28/29/30 */
-       [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",        NULL,    0 }, /* LPC */
-       [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",     NULL,    0 }, /* eSPI */
+       [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",        NULL,    CLK_IS_CRITICAL }, /* LPC */
+       [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",     NULL,    CLK_IS_CRITICAL }, /* eSPI */
        [ASPEED_CLK_GATE_REF1CLK]       = { 34, -1, "ref1clk-gate",     "clkin", CLK_IS_CRITICAL },
        /* Reserved 35 */
        [ASPEED_CLK_GATE_SDCLK]         = { 36, 56, "sdclk-gate",       NULL,    0 },   /* SDIO/SD */

@@ -102,8 +102,8 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
        [ASPEED_CLK_GATE_I3C5CLK]       = { 45,  45, "i3c5clk-gate",    NULL,    0 },   /* I3C5 */
        [ASPEED_CLK_GATE_I3C6CLK]       = { 46,  46, "i3c6clk-gate",    NULL,    0 },   /* I3C6 */
        [ASPEED_CLK_GATE_I3C7CLK]       = { 47,  47, "i3c7clk-gate",    NULL,    0 },   /* I3C7 */
-       [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",   "uart",  0 },   /* UART1 */
-       [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",   "uart",  0 },   /* UART2 */
+       [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",   "uart",  CLK_IS_CRITICAL },     /* UART1 */
+       [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",   "uart",  CLK_IS_CRITICAL },     /* UART2 */
        [ASPEED_CLK_GATE_UART3CLK]      = { 50,  -1, "uart3clk-gate",   "uart",  0 },   /* UART3 */
        [ASPEED_CLK_GATE_UART4CLK]      = { 51,  -1, "uart4clk-gate",   "uart",  0 },   /* UART4 */
        [ASPEED_CLK_GATE_MAC3CLK]       = { 52,  52, "mac3clk-gate",    "mac34", 0 },   /* MAC3 */
--

2.17.1

From: Joel Stanley <[email protected]>
Sent: Tuesday, September 29, 2020 4:04 PM
To: Ryan Chen <[email protected]>; Jae Hyun Yoo <[email protected]>; Andrew Jeffery <[email protected]>
Cc: Michael Turquette <[email protected]>; Stephen Boyd <[email protected]>; linux-clk at vger.kernel.org; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; Linux Kernel Mailing List <[email protected]>; BMC-SW <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[]

Quoted 17 lines · Ryan Chen

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---
 drivers/clk/clk-aspeed.c  | 8 ++++----  drivers/clk/clk-ast2600.c | 8
++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

drivers/clk/clk-aspeed.c index renamed from drivers/clk/clk-aspeed.c +0 -0

411ff5fb2c07..d348c4fd3f9f 100644

drivers/clk/clk-aspeed.c +0 -0

@@ -54,15 +54,15 @@ static const struct aspeed_gate_data aspeed_gates[]

= {

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 54

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",

NULL, CLK_IS_CRITICAL }, /* DAC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 55

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",

"clkin", CLK_IS_CRITICAL },

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 56

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",

NULL, 0 }, /* USB2.0 Host port 2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 57

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",

NULL, 0 }, /* LPC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 57

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",

NULL, CLK_IS_CRITICAL }, /* LPC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 58

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBUHCICLK] =  {  9, 15, "usb-uhci-gate",

NULL, 0 }, /* USB1.1 (requires port 2 enabled) */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 59

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_D1CLK] =       { 10, 13, "d1clk-gate",

NULL, 0 }, /* GFX CRT */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 60

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_YCLK] =        { 13,  4, "yclk-gate",

NULL, 0 }, /* HAC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 61

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate",

NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 62

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_UART1CLK] =    { 15, -1, "uart1clk-gate",

"uart", 0 }, /* UART1 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 63

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_UART2CLK] =    { 16, -1, "uart2clk-gate",

"uart", 0 }, /* UART2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 62

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_UART1CLK] =    { 15, -1, "uart1clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART1 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 63

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_UART2CLK] =    { 16, -1, "uart2clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 64

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_UART5CLK] =    { 17, -1, "uart5clk-gate",

"uart", 0 }, /* UART5 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 65

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_ESPICLK] =     { 19, -1, "espiclk-gate",

NULL, 0 }, /* eSPI */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 65

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_ESPICLK] =     { 19, -1, "espiclk-gate",

NULL, CLK_IS_CRITICAL }, /* eSPI */

This is fine for systems that have eSPI. For systems that do not use eSPI, the clocks are not "required".

I was sent a similar patch by Jae some time ago:

https://lore.kernel.org/openbmc/697a184b-ef99-a46e-bf98-4d339b3aafd8 at lin ux.intel.com/

Better is to associate drivers with these clocks, and those drivers will ensure they are left enabled.

Alternatively, we will need to come up with a device tree binding to describe the hardware requirement that these clocks are left on.

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 66

Quoted 2 lines

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_MAC1CLK] =     { 20, 11, "mac1clk-gate",

"mac", 0 }, /* MAC1 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 67

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_MAC2CLK] =     { 21, 12, "mac2clk-gate",

"mac", 0 }, /* MAC2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 68

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_RSACLK] =      { 24, -1, "rsaclk-gate",

NULL, 0 }, /* RSA */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[]

Quoted 5 lines

drivers/clk/clk-ast2600.c +0 -0

index bbacaccad554..6802a2d5bbe2 100644
@@ -86,8 +86,8 @@ static const struct aspeed_gate_data aspeed_g6_gates[]

= {

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 87

Quoted 2 lines

drivers/clk/clk-ast2600.c +0 -0

        /* Reserved 26 */
        [ASPEED_CLK_GATE_EMMCCLK]       = { 27, 16,

"emmcclk-gate", NULL, 0 }, /* For card clk */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 89

Quoted 2 lines

drivers/clk/clk-ast2600.c +0 -1

        /* Reserved 28/29/30 */
-       [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",

NULL, 0 }, /* LPC */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 90

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -1

-       [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",

NULL, 0 }, /* eSPI */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 89

Quoted 1 line

drivers/clk/clk-ast2600.c +1 -0

+       [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",

NULL, CLK_IS_CRITICAL }, /* LPC */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 90

Quoted 1 line

drivers/clk/clk-ast2600.c +1 -0

+       [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",

NULL, CLK_IS_CRITICAL }, /* eSPI */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 91

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_REF1CLK]       = { 34, -1, "ref1clk-gate",

"clkin", CLK_IS_CRITICAL },

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data aspeed_g6_gates[] · line 93

Quoted 2 lines

drivers/clk/clk-ast2600.c +0 -0

        /* Reserved 35 */
        [ASPEED_CLK_GATE_SDCLK]         = { 36, 56, "sdclk-gate",

NULL, 0 }, /* SDIO/SD */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

@@ -102,8 +102,8 @@ static const struct aspeed_gate_data

aspeed_g6_gates[] = {

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 102

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_I3C5CLK]       = { 45,  45, "i3c5clk-gate",

NULL, 0 }, /* I3C5 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 103

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_I3C6CLK]       = { 46,  46, "i3c6clk-gate",

NULL, 0 }, /* I3C6 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 104

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_I3C7CLK]       = { 47,  47, "i3c7clk-gate",

NULL, 0 }, /* I3C7 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 105

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -1

-       [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",

"uart", 0 }, /* UART1 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 106

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -1

-       [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",

"uart", 0 }, /* UART2 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 105

Quoted 1 line

drivers/clk/clk-ast2600.c +1 -0

+       [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART1 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 106

Quoted 1 line

drivers/clk/clk-ast2600.c +1 -0

+       [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART2 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 107

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_UART3CLK]      = { 50,  -1,

"uart3clk-gate", "uart", 0 }, /* UART3 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 108

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_UART4CLK]      = { 51,  -1,

"uart4clk-gate", "uart", 0 }, /* UART4 */

drivers/clk/clk-ast2600.c static const struct aspeed_gate_data · line 109

Quoted 1 line

drivers/clk/clk-ast2600.c +0 -0

        [ASPEED_CLK_GATE_MAC3CLK]       = { 52,  52,

"mac3clk-gate", "mac34", 0 }, /* MAC3 */

Quoted 3 lines

--
2.17.1

Quoted 77 lines

From: Joel Stanley <[email protected]>
Sent: Tuesday, September 29, 2020 4:04 PM
To: Ryan Chen <[email protected]>; Jae Hyun Yoo <[email protected]>; Andrew Jeffery <[email protected]>
Cc: Michael Turquette <[email protected]>; Stephen Boyd <[email protected]>; linux-clk at vger.kernel.org; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; Linux Kernel Mailing List <[email protected]>; BMC-SW <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[]

Quoted 17 lines · Ryan Chen

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---
 drivers/clk/clk-aspeed.c  | 8 ++++----  drivers/clk/clk-ast2600.c | 8
++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

drivers/clk/clk-aspeed.c index renamed from drivers/clk/clk-aspeed.c +0 -0

411ff5fb2c07..d348c4fd3f9f 100644

drivers/clk/clk-aspeed.c +0 -0

@@ -54,15 +54,15 @@ static const struct aspeed_gate_data aspeed_gates[]

= {

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 54

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",

NULL, CLK_IS_CRITICAL }, /* DAC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 55

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",

"clkin", CLK_IS_CRITICAL },

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 56

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",

NULL, 0 }, /* USB2.0 Host port 2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 57

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",

NULL, 0 }, /* LPC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 57

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_LCLK] =        {  8,  5, "lclk-gate",

NULL, CLK_IS_CRITICAL }, /* LPC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 58

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBUHCICLK] =  {  9, 15, "usb-uhci-gate",

NULL, 0 }, /* USB1.1 (requires port 2 enabled) */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 59

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_D1CLK] =       { 10, 13, "d1clk-gate",

NULL, 0 }, /* GFX CRT */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 60

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_YCLK] =        { 13,  4, "yclk-gate",

NULL, 0 }, /* HAC */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 61

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate",

NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 62

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_UART1CLK] =    { 15, -1, "uart1clk-gate",

"uart", 0 }, /* UART1 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 63

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_UART2CLK] =    { 16, -1, "uart2clk-gate",

"uart", 0 }, /* UART2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 62

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_UART1CLK] =    { 15, -1, "uart1clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART1 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 63

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_UART2CLK] =    { 16, -1, "uart2clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART2 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 64

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -0

        [ASPEED_CLK_GATE_UART5CLK] =    { 17, -1, "uart5clk-gate",

"uart", 0 }, /* UART5 */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 65

Quoted 1 line

drivers/clk/clk-aspeed.c +0 -1

-       [ASPEED_CLK_GATE_ESPICLK] =     { 19, -1, "espiclk-gate",

NULL, 0 }, /* eSPI */

drivers/clk/clk-aspeed.c static const struct aspeed_gate_data aspeed_gates[] · line 65

Quoted 1 line

drivers/clk/clk-aspeed.c +1 -0

+       [ASPEED_CLK_GATE_ESPICLK] =     { 19, -1, "espiclk-gate",

NULL, CLK_IS_CRITICAL }, /* eSPI */

This is fine for systems that have eSPI. For systems that do not use eSPI, the clocks are not "required".

I was sent a similar patch by Jae some time ago:

https://lore.kernel.org/openbmc/697a184b-ef99-a46e-bf98-4d339b3aafd8 at lin ux.intel.com/

Better is to associate drivers with these clocks, and those drivers will ensure they are left enabled.

Quoted 3 lines

Alternatively, we will need to come up with a device tree binding to describe the hardware requirement that these clocks are left on.

ASPEED BMC SoC have SuperIO device that default enable, even without BMC fw boot. Host can use SUART1/SUART2/GPIO....
That the reason even Linux kernel boot should not change the SoC default clk, that is the impact.

-----Original Message-----
From: Joel Stanley <[email protected]>
Sent: Wednesday, October 7, 2020 7:34 PM
To: Ryan Chen <[email protected]>
Cc: Jae Hyun Yoo <[email protected]>; Andrew Jeffery <[email protected]>; Michael Turquette <[email protected]>; Stephen Boyd <[email protected]>; linux-clk at vger.kernel.org; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; Linux Kernel Mailing List <[email protected]>; BMC-SW <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Quoted 13 lines · Ryan Chen

Quoted 13 lines

From: Joel Stanley <[email protected]>
Sent: Tuesday, September 29, 2020 4:04 PM
To: Ryan Chen <[email protected]>; Jae Hyun Yoo <[email protected]>; Andrew Jeffery <[email protected]>
Cc: Michael Turquette <[email protected]>; Stephen Boyd <[email protected]>; linux-clk at vger.kernel.org; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; Linux Kernel Mailing List <[email protected]>; BMC-SW <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Quoted 7 lines

Quoted 7 lines

Quoted 5 lines · Ryan Chen

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access

SuperIO and SPI slave device.

Quoted 19 lines

Quoted 19 lines

Quoted 13 lines

Signed-off-by Ryan Chen <[email protected]>

---
drivers/clk/clk-aspeed.c | 8 ++++---- drivers/clk/clk-ast2600.c
| 8
++++----

 2 files changed, 8 insertions(+), 8 deletions(-)

drivers/clk/clk-aspeed.c +0 -0

index 411ff5fb2c07..d348c4fd3f9f 100644
@@ -54,15 +54,15 @@ static const struct aspeed_gate_data

Quoted 1 line

aspeed_gates[]

= {

Quoted 1 line

        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",

NULL, CLK_IS_CRITICAL }, /* DAC */

Quoted 1 line

        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",

"clkin", CLK_IS_CRITICAL },

Quoted 8 lines

Quoted 8 lines

Quoted 2 lines

        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3,

"usb-port2-gate",

NULL, 0 }, /* USB2.0 Host port 2 */

Quoted 1 line

- [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate",

NULL, 0 }, /* LPC */

Quoted 1 line

+ [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate",

NULL, CLK_IS_CRITICAL }, /* LPC */

Quoted 1 line

        [ASPEED_CLK_GATE_USBUHCICLK] =  {  9, 15,

"usb-uhci-gate",

Quoted 9 lines

Quoted 9 lines

NULL, 0 }, /* USB1.1 (requires port 2 enabled) */

Quoted 1 line

        [ASPEED_CLK_GATE_D1CLK] =       { 10, 13, "d1clk-gate",

NULL, 0 }, /* GFX CRT */

Quoted 1 line

        [ASPEED_CLK_GATE_YCLK] =        { 13,  4, "yclk-gate",

NULL, 0 }, /* HAC */

Quoted 2 lines

        [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14,

"usb-port1-gate",

NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */

Quoted 1 line

- [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate",

Quoted 8 lines

Quoted 8 lines

"uart", 0 }, /* UART1 */

Quoted 1 line

- [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate",

"uart", 0 }, /* UART2 */

Quoted 1 line

+ [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART1 */

Quoted 1 line

+ [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate",

"uart", CLK_IS_CRITICAL }, /* UART2 */

Quoted 1 line

        [ASPEED_CLK_GATE_UART5CLK] =    { 17, -1,

"uart5clk-gate",

Quoted 16 lines

Quoted 16 lines

"uart", 0 }, /* UART5 */

Quoted 1 line

- [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate",

NULL, 0 }, /* eSPI */

Quoted 1 line

+ [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate",

NULL, CLK_IS_CRITICAL }, /* eSPI */

This is fine for systems that have eSPI. For systems that do not use eSPI, the clocks are not "required".

I was sent a similar patch by Jae some time ago:

https://lore.kernel.org/openbmc/697a184b-ef99-a46e-bf98-4d339b3aafd8
@lin
ux.intel.com/

Quoted 7 lines

Quoted 6 lines

Better is to associate drivers with these clocks, and those drivers will ensure they are left enabled.

Alternatively, we will need to come up with a device tree binding to describe the hardware requirement that these clocks are left on.

ASPEED BMC SoC have SuperIO device that default enable, even without

BMC fw boot.

Quoted 2 lines

Host can use SUART1/SUART2/GPIO....
That the reason even Linux kernel boot should not change the SoC default clk,

that is the impact.

Ok, that makes sense. Linux will not enable these clocks if a driver is loaded for them though, so we should load a driver for them.

ESPI: We do not have an upstream driver for eSPI, but once you submit one this will solve the eSPI issue.

LPC: The existing LPC driver will enable the clock, so by loading that this clock will be left enabled.

UART1/UART2: This is harder, as the SUART mode means the BMC does not load a driver for these devices. We could add a property to the device tree to describe the clocks that must be left on?

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 7 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

-----Original Message-----
From: Joel Stanley <[email protected]>
Sent: Wednesday, October 14, 2020 1:28 PM
To: Stephen Boyd <[email protected]>
Cc: Andrew Jeffery <[email protected]>; Michael Turquette <[email protected]>; Ryan Chen <[email protected]>; BMC-SW <[email protected]>; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; linux-clk at vger.kernel.org; Linux Kernel Mailing List <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Quoted 11 lines · Stephen Boyd

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 7 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them down.

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem already?

Quoted 11 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 7 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them down.

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem already?

Quoting Joel Stanley (2020-10-13 22:28:00)

Quoted 26 lines · Stephen Boyd

Quoted 11 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 7 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them down.

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Quoted 2 lines

Do you have any thoughts? Has anyone solved a similar problem already?

Is this critical clocks in DT? Where we want to have different DT for different device configurations to indicate that some clks should be marked critical so they're never turned off and other times they aren't so they're turned off?

It also sounds sort of like the protected-clocks binding. Where you don't want to touch certain clks depending on the usage configuration of the SoC. There is a patch to make that generic that I haven't applied because it looks wrong at first glance[1].

Maybe not registering those
clks to the framework on the configuration that Ryan has is good enough?

[1] https://lore.kernel.org/r/20200903040015.5627-2-samuel at sholland.org

Quoting Joel Stanley (2020-10-13 22:28:00)

Quoted 20 lines · Stephen Boyd

Quoted 11 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 7 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave device.

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Quoted 8 lines

Ryan wants to have them marked as critical so the BMC never powers them down.

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem already?

Is this critical clocks in DT? Where we want to have different DT for different device configurations to indicate that some clks should be marked critical so they're never turned off and other times they aren't so they're turned off?

It also sounds sort of like the protected-clocks binding. Where you don't want to touch certain clks depending on the usage configuration of the SoC. There is a patch to make that generic that I haven't applied because it looks wrong at first glance[1]. Maybe not registering those clks to the framework on the configuration that Ryan has is good enough?

[1] https://lore.kernel.org/r/20200903040015.5627-2-samuel at sholland.org

-----Original Message-----
From: Samuel Holland <[email protected]>
Sent: Thursday, October 29, 2020 10:25 AM
To: Stephen Boyd <[email protected]>; Joel Stanley <[email protected]>
Cc: Andrew Jeffery <[email protected]>; Michael Turquette <[email protected]>; Ryan Chen <[email protected]>; BMC-SW <[email protected]>; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; linux-clk at vger.kernel.org; Linux Kernel Mailing List <[email protected]>
Subject: Re: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Stephen,

Quoted 8 lines · Stephen Boyd

Quoting Joel Stanley (2020-10-13 22:28:00)

Quoted 7 lines · Stephen Boyd

Quoted 6 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 4 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave

device.

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

Quoted 3 lines

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Quoted 8 lines

Quoted 8 lines

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them

down.

Quoted 13 lines

Quoted 7 lines

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem already?

Is this critical clocks in DT? Where we want to have different DT for different device configurations to indicate that some clks should be marked critical so they're never turned off and other times they aren't so they're turned off?

Quoted 5 lines

It also sounds sort of like the protected-clocks binding. Where you don't want to touch certain clks depending on the usage configuration of the SoC. There is a patch to make that generic that I haven't applied because it looks wrong at first glance[1]. Maybe not registering those clks to the framework on the configuration that Ryan has is

good enough?

Could you please be more specific than the patch "looks wrong"? I'm more than happy to update the patch to address your concerns, but I cannot do that unless I know what your concerns are.

Regards,
Samuel

Quoted 2 lines

[1]
https://lore.kernel.org/r/20200903040015.5627-2-samuel at sholland.org

Hello,
How about this patch progress?
It does impact a lot of machine that when BMC boot at u-boot. SUART is work for Host. But after boot into kernel, due to the clk disabled. The SUART is not work for Host anymore.

Regards,
Ryan

Quoted 57 lines

-----Original Message-----
From: Samuel Holland <[email protected]>
Sent: Thursday, October 29, 2020 10:25 AM
To: Stephen Boyd <[email protected]>; Joel Stanley <[email protected]>
Cc: Andrew Jeffery <[email protected]>; Michael Turquette <[email protected]>; Ryan Chen <[email protected]>; BMC-SW <[email protected]>; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; linux-clk at vger.kernel.org; Linux Kernel Mailing List <[email protected]>
Subject: Re: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Stephen,

Quoted 8 lines · Stephen Boyd

Quoting Joel Stanley (2020-10-13 22:28:00)

Quoted 7 lines · Stephen Boyd

Quoted 6 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 4 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave

device.

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

Quoted 3 lines

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Quoted 8 lines

Quoted 8 lines

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them

down.

Quoted 13 lines

Quoted 7 lines

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem already?

Is this critical clocks in DT? Where we want to have different DT for different device configurations to indicate that some clks should be marked critical so they're never turned off and other times they aren't so they're turned off?

Quoted 5 lines

It also sounds sort of like the protected-clocks binding. Where you don't want to touch certain clks depending on the usage configuration of the SoC. There is a patch to make that generic that I haven't applied because it looks wrong at first glance[1]. Maybe not registering those clks to the framework on the configuration that Ryan has is

Quoted 11 lines

good enough?

Could you please be more specific than the patch "looks wrong"? I'm more than happy to update the patch to address your concerns, but I cannot do that unless I know what your concerns are.

Regards,
Samuel

Quoted 2 lines

[1]
https://lore.kernel.org/r/20200903040015.5627-2-samuel at sholland.org

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-----Original Message-----
From: Andrew Jeffery <[email protected]>
Sent: Monday, January 25, 2021 8:47 AM
To: Ryan Chen <[email protected]>; Samuel Holland <[email protected]>; Stephen Boyd <[email protected]>; Joel Stanley <[email protected]>
Cc: BMC-SW <[email protected]>; linux-aspeed <[email protected]>; Michael Turquette <[email protected]>; Linux Kernel Mailing List <[email protected]>; linux-clk at vger.kernel.org; Linux ARM <[email protected]>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Quoted 5 lines · Ryan Chen

Hello,
How about this patch progress?
It does impact a lot of machine that when BMC boot at u-boot. SUART is work for Host. But after boot into kernel, due to the clk disabled. The SUART is not work for Host anymore.

Maybe it's worth taking Ryan's patch for now, and when the protected-clocks binding gets merged we can rip out the CLK_IS_CRITICAL flags and convert the Aspeed devicetrees to use protected-clocks instead?

The only issue I see with that plan is it becomes ambiguous as to which clock each platform considers crititical/in-need-of-protection.

Quoted 18 lines

Quoted 18 lines

-----Original Message-----
From: Samuel Holland <[email protected]>
Sent: Thursday, October 29, 2020 10:25 AM
To: Stephen Boyd <[email protected]>; Joel Stanley <[email protected]>
Cc: Andrew Jeffery <[email protected]>; Michael Turquette <[email protected]>; Ryan Chen <[email protected]>; BMC-SW <[email protected]>; Linux ARM <[email protected]>; linux-aspeed <[email protected]>; linux-clk at vger.kernel.org; Linux Kernel Mailing List <[email protected]>
Subject: Re: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Stephen,

Quoted 2 lines · Stephen Boyd

Quoting Joel Stanley (2020-10-13 22:28:00)

Quoted 1 line

On Wed, 14 Oct 2020 at 02:50, Stephen Boyd <[email protected]>

Quoted 23 lines · wrote:

Quoted 23 lines

Quoted 7 lines

Quoted 7 lines

Quoted 7 lines

Quoting Ryan Chen (2020-09-28 00:01:08)

Quoted 5 lines

In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are default for Host SuperIO UART device, eSPI clk for Host eSPI bus access eSPI slave channel, those clks can't be disable should keep default, otherwise will affect Host side access SuperIO and SPI slave

device.

Quoted 15 lines

Quoted 15 lines

Quoted 5 lines

Quoted 3 lines

Signed-off-by Ryan Chen <[email protected]>

---

Is there resolution on this thread?

Not yet.

We have a system where the BMC (management controller) controls some clocks, but the peripherals that it's clocking are outside the BMC's control. In this case, the host processor us using some UARTs and what not independent of any code running on the BMC.

Ryan wants to have them marked as critical so the BMC never powers them

Quoted 7 lines

Quoted 7 lines

down.

Quoted 6 lines

Quoted 6 lines

However, there are systems that don't use this part of the soc, so for those implementations they are not critical and Linux on the BMC can turn them off.

Do you have any thoughts? Has anyone solved a similar problem

already?

Quoted 30 lines

Quoted 13 lines

Quoted 7 lines

Quoted 1 line

Is this critical clocks in DT? Where we want to have different DT for different device configurations to indicate that some clks should be marked critical so they're never turned off and other times they aren't so they're turned off?

Quoted 6 lines

It also sounds sort of like the protected-clocks binding. Where you don't want to touch certain clks depending on the usage configuration of the SoC. There is a patch to make that generic that I haven't applied because it looks wrong at first glance[1]. Maybe not registering those clks to the framework on the configuration that Ryan has is

Quoted 12 lines

good enough?

Could you please be more specific than the patch "looks wrong"? I'm more than happy to update the patch to address your concerns, but I cannot do that unless I know what your concerns are.

Regards,
Samuel

Quoted 3 lines

[1]
https://lore.kernel.org/r/20200903040015.5627-2-samuel at sholland.or g

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linux-arm-kernel at lists.infradead.org
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