pinctrl: tigerlake: Fix register offsets for TGL-H variant
Subsystems (3)
PATCH 1/3 pinctrl: tigerlake: Fix register offsets for TGL-H variant
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
--- drivers/pinctrl/intel/pinctrl-tigerlake.c | 42 ++++++++++++++--------- 1 file changed, 25 insertions(+), 17 deletions(-)
drivers/pinctrl/intel/pinctrl-tigerlake.c +25 -17
@@ -15,11 +15,13 @@#include "pinctrl-intel.h" -#define TGL_PAD_OWN 0x020 -#define TGL_PADCFGLOCK 0x080 -#define TGL_HOSTSW_OWN 0x0b0 -#define TGL_GPI_IS 0x100 -#define TGL_GPI_IE 0x120 +#define TGL_PAD_OWN 0x020 +#define TGL_LP_PADCFGLOCK 0x080 +#define TGL_H_PADCFGLOCK 0x090 +#define TGL_LP_HOSTSW_OWN 0x0b0 +#define TGL_H_HOSTSW_OWN 0x0c0 +#define TGL_GPI_IS 0x100 +#define TGL_GPI_IE 0x120#define TGL_GPP (r, s, e, g) \ { \
@@ -29,12 +31,12 @@ .gpio_base = (g), \ } -#define TGL_COMMUNITY (b, s, e, g) \ +#define TGL_COMMUNITY (b, s, e, pl, ho, g) \ { \ .barno = (b), \ .padown_offset = TGL_PAD_OWN, \ - .padcfglock_offset = TGL_PADCFGLOCK, \ - .hostown_offset = TGL_HOSTSW_OWN, \ + .padcfglock_offset = (pl), \ + .hostown_offset = (ho), \ .is_offset = TGL_GPI_IS, \ .ie_offset = TGL_GPI_IE, \ .pin_base = (s), \
@@ -43,6 +45,12 @@ .ngpps = ARRAY_SIZE(g), \ } +#define TGL_LP_COMMUNITY (b, s, e, g) \ + TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g) + +#define TGL_H_COMMUNITY (b, s, e, g) \ + TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g) +/* Tiger Lake-LP */ static const struct pinctrl_pin_desc tgllp_pins[] = {/* GPP_B */
@@ -367,10 +375,10 @@ static const struct intel_padgroup tgllp_community5_gpps[] = { };static const struct intel_community tgllp_communities[] = { -TGL_COMMUNITY (0 ,0 ,66 , tgllp_community0_gpps), -TGL_COMMUNITY (1 ,67 ,170 , tgllp_community1_gpps), -TGL_COMMUNITY (2 ,171 ,259 , tgllp_community4_gpps), -TGL_COMMUNITY (3 ,260 ,276 , tgllp_community5_gpps), +TGL_LP_COMMUNITY (0 ,0 ,66 , tgllp_community0_gpps), +TGL_LP_COMMUNITY (1 ,67 ,170 , tgllp_community1_gpps), +TGL_LP_COMMUNITY (2 ,171 ,259 , tgllp_community4_gpps), +TGL_LP_COMMUNITY (3 ,260 ,276 , tgllp_community5_gpps), };static const struct intel_pinctrl_soc_data tgllp_soc_data = {
@@ -723,11 +731,11 @@ static const struct intel_padgroup tglh_community5_gpps[] = { };static const struct intel_community tglh_communities[] = { -TGL_COMMUNITY (0 ,0 ,78 , tglh_community0_gpps), -TGL_COMMUNITY (1 ,79 ,180 , tglh_community1_gpps), -TGL_COMMUNITY (2 ,181 ,217 , tglh_community3_gpps), -TGL_COMMUNITY (3 ,218 ,266 , tglh_community4_gpps), -TGL_COMMUNITY (4 ,267 ,290 , tglh_community5_gpps), +TGL_H_COMMUNITY (0 ,0 ,78 , tglh_community0_gpps), +TGL_H_COMMUNITY (1 ,79 ,180 , tglh_community1_gpps), +TGL_H_COMMUNITY (2 ,181 ,217 , tglh_community3_gpps), +TGL_H_COMMUNITY (3 ,218 ,266 , tglh_community4_gpps), +TGL_H_COMMUNITY (4 ,267 ,290 , tglh_community5_gpps), };static const struct intel_pinctrl_soc_data tglh_soc_data = {
Signature · 1 line
2.28.0
PATCH 2/3 pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended.
--- drivers/pinctrl/intel/pinctrl-cannonlake.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)
drivers/pinctrl/intel/pinctrl-cannonlake.c +11 -11
@@ -30,12 +30,12 @@ .gpio_base = (g), \ } -#define CNL_COMMUNITY (b, s, e, o, g) \ +#define CNL_COMMUNITY (b, s, e, ho, g) \ { \ .barno = (b), \ .padown_offset = CNL_PAD_OWN, \ .padcfglock_offset = CNL_PADCFGLOCK, \ - .hostown_offset = (o), \ + .hostown_offset = (ho), \ .is_offset = CNL_GPI_IS, \ .ie_offset = CNL_GPI_IE, \ .pin_base = (s), \
@@ -44,10 +44,10 @@ .ngpps = ARRAY_SIZE(g), \ } -#define CNLLP_COMMUNITY (b, s, e, g) \ +#define CNL_LP_COMMUNITY (b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g) -#define CNLH_COMMUNITY (b, s, e, g) \ +#define CNL_H_COMMUNITY (b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)/* Cannon Lake-H */
@@ -449,10 +449,10 @@ static const struct intel_function cnlh_functions[] = { };static const struct intel_community cnlh_communities[] = { -CNLH_COMMUNITY (0 ,0 ,50 , cnlh_community0_gpps), -CNLH_COMMUNITY (1 ,51 ,154 , cnlh_community1_gpps), -CNLH_COMMUNITY (2 ,155 ,248 , cnlh_community3_gpps), -CNLH_COMMUNITY (3 ,249 ,298 , cnlh_community4_gpps), +CNL_H_COMMUNITY (0 ,0 ,50 , cnlh_community0_gpps), +CNL_H_COMMUNITY (1 ,51 ,154 , cnlh_community1_gpps), +CNL_H_COMMUNITY (2 ,155 ,248 , cnlh_community3_gpps), +CNL_H_COMMUNITY (3 ,249 ,298 , cnlh_community4_gpps), };static const struct intel_pinctrl_soc_data cnlh_soc_data = {
@@ -810,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = { };static const struct intel_community cnllp_communities[] = { -CNLLP_COMMUNITY (0 ,0 ,67 , cnllp_community0_gpps), -CNLLP_COMMUNITY (1 ,68 ,180 , cnllp_community1_gpps), -CNLLP_COMMUNITY (2 ,181 ,243 , cnllp_community4_gpps), +CNL_LP_COMMUNITY (0 ,0 ,67 , cnllp_community0_gpps), +CNL_LP_COMMUNITY (1 ,68 ,180 , cnllp_community1_gpps), +CNL_LP_COMMUNITY (2 ,181 ,243 , cnllp_community4_gpps), };static const struct intel_pinctrl_soc_data cnllp_soc_data = {
Signature · 1 line
2.28.0
Re: [PATCH v1 2/3] pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
Quoted 4 lines · Andy Shevchenko
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended.
Signed-off-by Andy Shevchenko <[email protected]>
PATCH 3/3 pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
In reply to Andy ShevchenkoModify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended.
--- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 60 +++++++++----------- 1 file changed, 27 insertions(+), 33 deletions(-)
drivers/pinctrl/intel/pinctrl-sunrisepoint.c +27 -33
@@ -22,21 +22,26 @@#define SPT_GPI_IS 0x100#define SPT_GPI_IE 0x120 -#define SPT_COMMUNITY (b, s, e) \ +#define SPT_COMMUNITY (b, s, e, pl, gs, gn, g, n) \ { \ .barno = (b), \ .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_LP_PADCFGLOCK, \ + .padcfglock_offset = (pl), \ .hostown_offset = SPT_HOSTSW_OWN, \ .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ - .gpp_size = 24, \ - .gpp_num_padown_regs = 4, \ + .gpp_size = (gs), \ + .gpp_num_padown_regs = (gn), \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = (n), \ } -#define SPTH_GPP (r, s, e, g) \ +#define SPT_LP_COMMUNITY (b, s, e) \ + SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0) + +#define SPT_H_GPP (r, s, e, g) \ { \ .reg_num = (r), \ .base = (s), \
@@ -44,19 +49,8 @@ .gpio_base = (g), \ } -#define SPTH_COMMUNITY (b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_H_PADCFGLOCK, \ - .hostown_offset = SPT_HOSTSW_OWN, \ - .is_offset = SPT_GPI_IS, \ - .ie_offset = SPT_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } +#define SPT_H_COMMUNITY (b, s, e, g) \ + SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))/* Sunrisepoint-LP */ static const struct pinctrl_pin_desc sptlp_pins[] = {
@@ -292,9 +286,9 @@ static const struct intel_function sptlp_functions[] = { };static const struct intel_community sptlp_communities[] = { -SPT_COMMUNITY (0 ,0 ,47 ), -SPT_COMMUNITY (1 ,48 ,119 ), -SPT_COMMUNITY (2 ,120 ,151 ), +SPT_LP_COMMUNITY (0 ,0 ,47 ), +SPT_LP_COMMUNITY (1 ,48 ,119 ), +SPT_LP_COMMUNITY (2 ,120 ,151 ), };static const struct intel_pinctrl_soc_data sptlp_soc_data = {
@@ -554,27 +548,27 @@ static const struct intel_function spth_functions[] = { };static const struct intel_padgroup spth_community0_gpps[] = { -SPTH_GPP (0 ,0 ,23 ,0 ),/* GPP_A */ -SPTH_GPP (1 ,24 ,47 ,24 ),/* GPP_B */ +SPT_H_GPP (0 ,0 ,23 ,0 ),/* GPP_A */ +SPT_H_GPP (1 ,24 ,47 ,24 ),/* GPP_B */ };static const struct intel_padgroup spth_community1_gpps[] = { -SPTH_GPP (0 ,48 ,71 ,48 ),/* GPP_C */ -SPTH_GPP (1 ,72 ,95 ,72 ),/* GPP_D */ -SPTH_GPP (2 ,96 ,108 ,96 ),/* GPP_E */ -SPTH_GPP (3 ,109 ,132 ,120 ),/* GPP_F */ -SPTH_GPP (4 ,133 ,156 ,144 ),/* GPP_G */ -SPTH_GPP (5 ,157 ,180 ,168 ),/* GPP_H */ +SPT_H_GPP (0 ,48 ,71 ,48 ),/* GPP_C */ +SPT_H_GPP (1 ,72 ,95 ,72 ),/* GPP_D */ +SPT_H_GPP (2 ,96 ,108 ,96 ),/* GPP_E */ +SPT_H_GPP (3 ,109 ,132 ,120 ),/* GPP_F */ +SPT_H_GPP (4 ,133 ,156 ,144 ),/* GPP_G */ +SPT_H_GPP (5 ,157 ,180 ,168 ),/* GPP_H */ };static const struct intel_padgroup spth_community3_gpps[] = { -SPTH_GPP (0 ,181 ,191 ,192 ),/* GPP_I */ +SPT_H_GPP (0 ,181 ,191 ,192 ),/* GPP_I */ };static const struct intel_community spth_communities[] = { -SPTH_COMMUNITY (0 ,0 ,47 , spth_community0_gpps), -SPTH_COMMUNITY (1 ,48 ,180 , spth_community1_gpps), -SPTH_COMMUNITY (2 ,181 ,191 , spth_community3_gpps), +SPT_H_COMMUNITY (0 ,0 ,47 , spth_community0_gpps), +SPT_H_COMMUNITY (1 ,48 ,180 , spth_community1_gpps), +SPT_H_COMMUNITY (2 ,181 ,191 , spth_community3_gpps), };static const struct intel_pinctrl_soc_data spth_soc_data = {
Signature · 1 line
2.28.0
Re: [PATCH v1 3/3] pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
Quoted 4 lines · Andy Shevchenko
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended.
Signed-off-by Andy Shevchenko <[email protected]>
Quoted 7 lines · Andy Shevchenko
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Fixes 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")Reported-by Pierre-Louis Bossart <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>
I could apply this one for fixes as you indicated in another thread, does the other two patches depend on it?
Yours,
Linus Walleij
Quoted 7 lines · Linus Walleij
Quoted 4 lines · Andy Shevchenko
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Quoted 6 lines
Quoted 3 lines
Fixes 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")Reported-by Pierre-Louis Bossart <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>I could apply this one for fixes as you indicated in another thread, does the other two patches depend on it?
Logically -- yes, functionally -- no. They may be applied for v5.10 or, as I said, v5.11 (but in the latter case I will do it the usual way, via our branch).
Thanks!
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 12 lines · Andy Shevchenko
Quoted 11 lines · Linus Walleij
Quoted 7 lines · Andy Shevchenko
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Fixes 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")Reported-by Pierre-Louis Bossart <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>
Quoted 6 lines
Quoted 2 lines
I could apply this one for fixes as you indicated in another thread, does the other two patches depend on it?
Logically -- yes, functionally -- no. They may be applied for v5.10 or, as I said, v5.11 (but in the latter case I will do it the usual way, via our branch).
OK since they are all ACKed I just applied all three for v5.10.
Thanks!
Linus Walleij
Quoted 14 lines · Linus Walleij
Quoted 12 lines · Andy Shevchenko
Quoted 11 lines · Linus Walleij
Quoted 7 lines · Andy Shevchenko
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Fixes 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")Reported-by Pierre-Louis Bossart <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
I could apply this one for fixes as you indicated in another thread, does the other two patches depend on it?
Logically -- yes, functionally -- no. They may be applied for v5.10 or, as I said, v5.11 (but in the latter case I will do it the usual way, via our branch).
OK since they are all ACKed I just applied all three for v5.10.
Thanks! First one can be part of v5.9 (it's a fix) in case it doesn't hurt your workflow.
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 7 lines · Andy Shevchenko
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant.
Fixes 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H")Reported-by Pierre-Louis Bossart <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>