arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD

TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.

Cc Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.

Cc Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---

v1 -> v2: Retain isb() prior to TLB invalidation.

 arch/arm64/kernel/cpufeature.c | 1 +
 1 file changed, 1 insertion(+)

arch/arm64/kernel/cpufeature.c +1 -0

index 6424584be01e..a474a4f39c95 100644
@@ -1443,6 +1443,7 @@ static inline void __cpu_enable_hw_dbm(void)
 
 	write_sysreg(tcr, tcr_el1);
 	isb();
+	local_flush_tlb_all();
 }
 
 static bool cpu_has_broken_dbm(void)

Signature · 1 line

2.28.0.709.gb0816b6eb0-goog