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i915/perf_pmu: Fix perf fd leak

PATCH Superseded Tvrtko Ursulin 3 participants 8 messages Oct 13, 2020

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Tvrtko Ursulin

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#0 lore raw

PATCH 1/1 i915/perf_pmu: Fix perf fd leak

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
 1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +78 -52
index 873b275dca6b..6f8bec28d274 100644
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -546,7 +547,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -600,7 +602,8 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -617,22 +620,23 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	igt_spin_t *spin;
 	uint64_t val[2][2];
-	int fd;
+	int fd[2];
 
-	fd = open_group(gem_fd,
-			I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
+			   fd[0]);
 
 	if (flags & TEST_BUSY)
 		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
-	pmu_read_multi(fd, 2, val[0]);
+	pmu_read_multi(fd[0], 2, val[0]);
 	measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
 		end_spin(gem_fd, spin, flags);
-	pmu_read_multi(fd, 2, val[1]);
+	pmu_read_multi(fd[0], 2, val[1]);
 
 	val[0][0] = val[1][0] - val[0][0];
 	val[0][1] = val[1][1] - val[0][1];

@@ -641,7 +645,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 		end_spin(gem_fd, spin, FLAG_SYNC);
 		igt_spin_free(gem_fd, spin);
 	}
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	assert_within_epsilon(val[0][0], 0.0f, tolerance);
 	assert_within_epsilon(val[0][1], 0.0f, tolerance);

@@ -861,18 +866,21 @@ sema_busy(int gem_fd,
 	  const struct intel_execution_engine2 *e,
 	  unsigned int flags)
 {
-	int fd;
+	int fd[2];
 
 	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
 
-	fd = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance),
+			   fd[0]);
 
-	__sema_busy(gem_fd, fd, e, 50, 100);
-	__sema_busy(gem_fd, fd, e, 25, 50);
-	__sema_busy(gem_fd, fd, e, 75, 75);
+	__sema_busy(gem_fd, fd[0], e, 50, 100);
+	__sema_busy(gem_fd, fd[0], e, 25, 50);
+	__sema_busy(gem_fd, fd[0], e, 75, 75);
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 }
 
 #define   MI_WAIT_FOR_PIPE_C_VBLANK (1<<21)

@@ -1441,7 +1449,7 @@ test_frequency(int gem_fd)
 	uint64_t val[2], start[2], slept;
 	double min[2], max[2];
 	igt_spin_t *spin;
-	int fd, sysfs;
+	int fd[2], sysfs;
 
 	sysfs = igt_sysfs_open(gem_fd);
 	igt_require(sysfs >= 0);

@@ -1455,8 +1463,8 @@ test_frequency(int gem_fd)
 	igt_require(max_freq > min_freq);
 	igt_require(boost_freq > min_freq);
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
 	/*
 	 * Set GPU to min frequency and read PMU counters.

@@ -1471,9 +1479,9 @@ test_frequency(int gem_fd)
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
 	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
 	min[0] = 1e9*(val[0] - start[0]) / slept;
 	min[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1497,9 +1505,9 @@ test_frequency(int gem_fd)
 	gem_quiescent_gpu(gem_fd);
 	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
 	max[0] = 1e9*(val[0] - start[0]) / slept;
 	max[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1514,7 +1522,8 @@ test_frequency(int gem_fd)
 	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
 		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
 			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	igt_info("Min frequency: requested %.1f, actual %.1f\n",
 		 min[0], min[1]);

@@ -1535,7 +1544,7 @@ test_frequency_idle(int gem_fd)
 	uint32_t min_freq;
 	uint64_t val[2], start[2], slept;
 	double idle[2];
-	int fd, sysfs;
+	int fd[2], sysfs;
 
 	sysfs = igt_sysfs_open(gem_fd);
 	igt_require(sysfs >= 0);

@@ -1545,17 +1554,18 @@ test_frequency_idle(int gem_fd)
 
 	/* While parked, our convention is to report the GPU at 0Hz */
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
 	gem_quiescent_gpu(gem_fd); /* Be idle! */
 	measured_usleep(2000); /* Wait for timers to cease */
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	idle[0] = 1e9*(val[0] - start[0]) / slept;
 	idle[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1926,57 +1936,73 @@ static int unload_i915(void)
 	return 0;
 }
 
-static void test_unload(void)
+static void test_unload(unsigned int num_engines)
 {
 	igt_fork(child, 1) {
 		const struct intel_execution_engine2 *e;
+		int fd[4 + num_engines], i;
 		uint64_t *buf;
-		int count = 1;
+		int count = 0;
 		int i915;
-		int fd;
 
 		i915 = __drm_open_driver(DRIVER_INTEL);
 
 		igt_debug("Opening perf events\n");
-		fd = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		fd[count] = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		if (fd[count] != -1)
+			count++;
 
-		if (perf_i915_open_group(i915, I915_PMU_REQUESTED_FREQUENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_REQUESTED_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
-		if (perf_i915_open_group(i915, I915_PMU_ACTUAL_FREQUENCY, fd) != -1)
+
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_ACTUAL_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
 
 		__for_each_physical_engine(i915, e) {
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_BUSY(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_BUSY(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_SEMA(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_SEMA(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_WAIT(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_WAIT(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 		}
 
-		if (perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
 
 		close(i915);
 
-		buf = calloc(count + 1, sizeof(uint64_t));
+		buf = calloc(count, sizeof(uint64_t));
 		igt_assert(buf);
 
 		igt_debug("Read %d events from perf and trial unload\n", count);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
 		igt_assert_eq(unload_i915(), -EBUSY);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
 
 		igt_debug("Close perf\n");
-		close(fd);
+
+		for (i = 0; i < count; i++)
+			close(fd[i]);
 
 		free(buf);
 	}

@@ -2357,6 +2383,6 @@ igt_main
 	igt_subtest("module-unload") {
 		igt_require(unload_i915() == 0);
 		for (int pass = 0; pass < 3; pass++)
-			test_unload();
+			test_unload(num_engines);
 	}
 }
Signature · 6 lines
2.25.1

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author
#1 lore raw
Quoted 202 lines · Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
  tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
  1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +41 -31
index 873b275dca6b..6f8bec28d274 100644
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
  	end_spin(gem_fd, spin, FLAG_SYNC);
  	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
  	for (i = 0; i < num_engines; i++)
  		val[i] = tval[1][i] - tval[0][i];

@@ -546,7 +547,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
  	end_spin(gem_fd, spin, FLAG_SYNC);
  	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
  	for (i = 0; i < num_engines; i++)
  		val[i] = tval[1][i] - tval[0][i];

@@ -600,7 +602,8 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 
  	end_spin(gem_fd, spin, FLAG_SYNC);
  	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
  	for (i = 0; i < num_engines; i++)
  		val[i] = tval[1][i] - tval[0][i];

@@ -617,22 +620,23 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
  {
  	igt_spin_t *spin;
  	uint64_t val[2][2];
-	int fd;
+	int fd[2];
 
-	fd = open_group(gem_fd,
-			I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
+			   fd[0]);
 
  	if (flags & TEST_BUSY)
  		spin = spin_sync(gem_fd, 0, e);
  	else
  		spin = NULL;
 
-	pmu_read_multi(fd, 2, val[0]);
+	pmu_read_multi(fd[0], 2, val[0]);
  	measured_usleep(batch_duration_ns / 1000);
  	if (flags & TEST_TRAILING_IDLE)
  		end_spin(gem_fd, spin, flags);
-	pmu_read_multi(fd, 2, val[1]);
+	pmu_read_multi(fd[0], 2, val[1]);
 
  	val[0][0] = val[1][0] - val[0][0];
  	val[0][1] = val[1][1] - val[0][1];

@@ -641,7 +645,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
  		end_spin(gem_fd, spin, FLAG_SYNC);
  		igt_spin_free(gem_fd, spin);
  	}
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
  	assert_within_epsilon(val[0][0], 0.0f, tolerance);
  	assert_within_epsilon(val[0][1], 0.0f, tolerance);

@@ -861,18 +866,21 @@ sema_busy(int gem_fd,
  	  const struct intel_execution_engine2 *e,
  	  unsigned int flags)
  {
-	int fd;
+	int fd[2];
 
  	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
 
-	fd = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance),
+			   fd[0]);
 
-	__sema_busy(gem_fd, fd, e, 50, 100);
-	__sema_busy(gem_fd, fd, e, 25, 50);
-	__sema_busy(gem_fd, fd, e, 75, 75);
+	__sema_busy(gem_fd, fd[0], e, 50, 100);
+	__sema_busy(gem_fd, fd[0], e, 25, 50);
+	__sema_busy(gem_fd, fd[0], e, 75, 75);
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
  }
 
  #define   MI_WAIT_FOR_PIPE_C_VBLANK (1<<21)

@@ -1441,7 +1449,7 @@ test_frequency(int gem_fd)
  	uint64_t val[2], start[2], slept;
  	double min[2], max[2];
  	igt_spin_t *spin;
-	int fd, sysfs;
+	int fd[2], sysfs;
 
  	sysfs = igt_sysfs_open(gem_fd);
  	igt_require(sysfs >= 0);

@@ -1455,8 +1463,8 @@ test_frequency(int gem_fd)
  	igt_require(max_freq > min_freq);
  	igt_require(boost_freq > min_freq);
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
  	/*
  	 * Set GPU to min frequency and read PMU counters.

@@ -1471,9 +1479,9 @@ test_frequency(int gem_fd)
  	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
  	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
  	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
  	min[0] = 1e9*(val[0] - start[0]) / slept;
  	min[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1497,9 +1505,9 @@ test_frequency(int gem_fd)
  	gem_quiescent_gpu(gem_fd);
  	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
  	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
  	max[0] = 1e9*(val[0] - start[0]) / slept;
  	max[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1514,7 +1522,8 @@ test_frequency(int gem_fd)
  	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
  		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
  			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
  	igt_info("Min frequency: requested %.1f, actual %.1f\n",
  		 min[0], min[1]);

@@ -1535,7 +1544,7 @@ test_frequency_idle(int gem_fd)
  	uint32_t min_freq;
  	uint64_t val[2], start[2], slept;
  	double idle[2];
-	int fd, sysfs;
+	int fd[2], sysfs;
 
  	sysfs = igt_sysfs_open(gem_fd);
  	igt_require(sysfs >= 0);

@@ -1545,17 +1554,18 @@ test_frequency_idle(int gem_fd)
 
  	/* While parked, our convention is to report the GPU at 0Hz */
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
  	gem_quiescent_gpu(gem_fd); /* Be idle! */
  	measured_usleep(2000); /* Wait for timers to cease */
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
  	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
  	idle[0] = 1e9*(val[0] - start[0]) / slept;
  	idle[1] = 1e9*(val[1] - start[1]) / slept;

tests/i915/perf_pmu.c static int unload_i915(void) · line 1943

Quoted 9 lines
tests/i915/perf_pmu.c +2 -1
@@ -1926,57 +1936,73 @@ static int unload_i915(void)
  	return 0;
  }
 
-static void test_unload(void)
+static void test_unload(unsigned int num_engines)
  {
  	igt_fork(child, 1) {
  		const struct intel_execution_engine2 *e;
+		int fd[4 + num_engines], i;

4 + num_engines * 3

Regards,

Tvrtko

Quoted 86 lines
tests/i915/perf_pmu.c +34 -19
  		uint64_t *buf;
-		int count = 1;
+		int count = 0;
  		int i915;
-		int fd;
 
  		i915 = __drm_open_driver(DRIVER_INTEL);
 
  		igt_debug("Opening perf events\n");
-		fd = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		fd[count] = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		if (fd[count] != -1)
+			count++;
 
-		if (perf_i915_open_group(i915, I915_PMU_REQUESTED_FREQUENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_REQUESTED_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
  			count++;
-		if (perf_i915_open_group(i915, I915_PMU_ACTUAL_FREQUENCY, fd) != -1)
+
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_ACTUAL_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
  			count++;
 
  		__for_each_physical_engine(i915, e) {
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_BUSY(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_BUSY(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
  				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_SEMA(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_SEMA(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
  				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_WAIT(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_WAIT(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
  				count++;
  		}
 
-		if (perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
  			count++;
 
  		close(i915);
 
-		buf = calloc(count + 1, sizeof(uint64_t));
+		buf = calloc(count, sizeof(uint64_t));
  		igt_assert(buf);
 
  		igt_debug("Read %d events from perf and trial unload\n", count);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
  		igt_assert_eq(unload_i915(), -EBUSY);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
 
  		igt_debug("Close perf\n");
-		close(fd);
+
+		for (i = 0; i < count; i++)
+			close(fd[i]);
 
  		free(buf);
  	}

tests/i915/perf_pmu.c igt_main · line 2388

Quoted 7 lines
tests/i915/perf_pmu.c +1 -1
@@ -2357,6 +2383,6 @@ igt_main
  	igt_subtest("module-unload") {
  		igt_require(unload_i915() == 0);
  		for (int pass = 0; pass < 3; pass++)
-			test_unload();
+			test_unload(num_engines);
  	}
  }

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author
#2 lore raw

PATCH v2 1/1 i915/perf_pmu: Fix perf fd leak

In reply to Tvrtko Ursulin

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

v2:
* Fix array sizing unload.

Signed-off-by Tvrtko Ursulin <[email protected]>
---
 tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
 1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +78 -52
index 873b275dca6b..b2402955092e 100644
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -546,7 +547,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -600,7 +602,8 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 
 	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_free(gem_fd, spin);
-	close(fd[0]);
+	for (i = 0; i < num_engines; i++)
+		close(fd[i]);
 
 	for (i = 0; i < num_engines; i++)
 		val[i] = tval[1][i] - tval[0][i];

@@ -617,22 +620,23 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	igt_spin_t *spin;
 	uint64_t val[2][2];
-	int fd;
+	int fd[2];
 
-	fd = open_group(gem_fd,
-			I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance),
+			   fd[0]);
 
 	if (flags & TEST_BUSY)
 		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
-	pmu_read_multi(fd, 2, val[0]);
+	pmu_read_multi(fd[0], 2, val[0]);
 	measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
 		end_spin(gem_fd, spin, flags);
-	pmu_read_multi(fd, 2, val[1]);
+	pmu_read_multi(fd[0], 2, val[1]);
 
 	val[0][0] = val[1][0] - val[0][0];
 	val[0][1] = val[1][1] - val[0][1];

@@ -641,7 +645,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 		end_spin(gem_fd, spin, FLAG_SYNC);
 		igt_spin_free(gem_fd, spin);
 	}
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	assert_within_epsilon(val[0][0], 0.0f, tolerance);
 	assert_within_epsilon(val[0][1], 0.0f, tolerance);

@@ -861,18 +866,21 @@ sema_busy(int gem_fd,
 	  const struct intel_execution_engine2 *e,
 	  unsigned int flags)
 {
-	int fd;
+	int fd[2];
 
 	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
 
-	fd = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
-	open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+	fd[0] = open_group(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance),
+			   -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance),
+			   fd[0]);
 
-	__sema_busy(gem_fd, fd, e, 50, 100);
-	__sema_busy(gem_fd, fd, e, 25, 50);
-	__sema_busy(gem_fd, fd, e, 75, 75);
+	__sema_busy(gem_fd, fd[0], e, 50, 100);
+	__sema_busy(gem_fd, fd[0], e, 25, 50);
+	__sema_busy(gem_fd, fd[0], e, 75, 75);
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 }
 
 #define   MI_WAIT_FOR_PIPE_C_VBLANK (1<<21)

@@ -1441,7 +1449,7 @@ test_frequency(int gem_fd)
 	uint64_t val[2], start[2], slept;
 	double min[2], max[2];
 	igt_spin_t *spin;
-	int fd, sysfs;
+	int fd[2], sysfs;
 
 	sysfs = igt_sysfs_open(gem_fd);
 	igt_require(sysfs >= 0);

@@ -1455,8 +1463,8 @@ test_frequency(int gem_fd)
 	igt_require(max_freq > min_freq);
 	igt_require(boost_freq > min_freq);
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
 	/*
 	 * Set GPU to min frequency and read PMU counters.

@@ -1471,9 +1479,9 @@ test_frequency(int gem_fd)
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
 	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
 	min[0] = 1e9*(val[0] - start[0]) / slept;
 	min[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1497,9 +1505,9 @@ test_frequency(int gem_fd)
 	gem_quiescent_gpu(gem_fd);
 	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
 	max[0] = 1e9*(val[0] - start[0]) / slept;
 	max[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1514,7 +1522,8 @@ test_frequency(int gem_fd)
 	if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
 		igt_warn("Unable to restore min frequency to saved value [%u MHz], now %u MHz\n",
 			 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	igt_info("Min frequency: requested %.1f, actual %.1f\n",
 		 min[0], min[1]);

@@ -1535,7 +1544,7 @@ test_frequency_idle(int gem_fd)
 	uint32_t min_freq;
 	uint64_t val[2], start[2], slept;
 	double idle[2];
-	int fd, sysfs;
+	int fd[2], sysfs;
 
 	sysfs = igt_sysfs_open(gem_fd);
 	igt_require(sysfs >= 0);

@@ -1545,17 +1554,18 @@ test_frequency_idle(int gem_fd)
 
 	/* While parked, our convention is to report the GPU at 0Hz */
 
-	fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
-	open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
+	fd[0] = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+	fd[1] = open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd[0]);
 
 	gem_quiescent_gpu(gem_fd); /* Be idle! */
 	measured_usleep(2000); /* Wait for timers to cease */
 
-	slept = pmu_read_multi(fd, 2, start);
+	slept = pmu_read_multi(fd[0], 2, start);
 	measured_usleep(batch_duration_ns / 1000);
-	slept = pmu_read_multi(fd, 2, val) - slept;
+	slept = pmu_read_multi(fd[0], 2, val) - slept;
 
-	close(fd);
+	close(fd[0]);
+	close(fd[1]);
 
 	idle[0] = 1e9*(val[0] - start[0]) / slept;
 	idle[1] = 1e9*(val[1] - start[1]) / slept;

@@ -1926,57 +1936,73 @@ static int unload_i915(void)
 	return 0;
 }
 
-static void test_unload(void)
+static void test_unload(unsigned int num_engines)
 {
 	igt_fork(child, 1) {
 		const struct intel_execution_engine2 *e;
+		int fd[4 + num_engines * 3], i;
 		uint64_t *buf;
-		int count = 1;
+		int count = 0;
 		int i915;
-		int fd;
 
 		i915 = __drm_open_driver(DRIVER_INTEL);
 
 		igt_debug("Opening perf events\n");
-		fd = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		fd[count] = open_group(i915, I915_PMU_INTERRUPTS, -1);
+		if (fd[count] != -1)
+			count++;
 
-		if (perf_i915_open_group(i915, I915_PMU_REQUESTED_FREQUENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_REQUESTED_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
-		if (perf_i915_open_group(i915, I915_PMU_ACTUAL_FREQUENCY, fd) != -1)
+
+		fd[count] = perf_i915_open_group(i915,
+						 I915_PMU_ACTUAL_FREQUENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
 
 		__for_each_physical_engine(i915, e) {
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_BUSY(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_BUSY(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_SEMA(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_SEMA(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 
-			if (perf_i915_open_group(i915,
-						 I915_PMU_ENGINE_WAIT(e->class, e->instance),
-						 fd) != -1)
+			fd[count] = perf_i915_open_group(i915,
+							 I915_PMU_ENGINE_WAIT(e->class, e->instance),
+							 fd[count - 1]);
+			if (fd[count] != -1)
 				count++;
 		}
 
-		if (perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,fd) != -1)
+		fd[count] = perf_i915_open_group(i915, I915_PMU_RC6_RESIDENCY,
+						 fd[count - 1]);
+		if (fd[count] != -1)
 			count++;
 
 		close(i915);
 
-		buf = calloc(count + 1, sizeof(uint64_t));
+		buf = calloc(count, sizeof(uint64_t));
 		igt_assert(buf);
 
 		igt_debug("Read %d events from perf and trial unload\n", count);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
 		igt_assert_eq(unload_i915(), -EBUSY);
-		pmu_read_multi(fd, count, buf);
+		pmu_read_multi(fd[0], count, buf);
 
 		igt_debug("Close perf\n");
-		close(fd);
+
+		for (i = 0; i < count; i++)
+			close(fd[i]);
 
 		free(buf);
 	}

@@ -2357,6 +2383,6 @@ igt_main
 	igt_subtest("module-unload") {
 		igt_require(unload_i915() == 0);
 		for (int pass = 0; pass < 3; pass++)
-			test_unload();
+			test_unload(num_engines);
 	}
 }
Signature · 6 lines
2.25.1

_______________________________________________
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#3 lore raw
In reply to Tvrtko Ursulin

Quoting Tvrtko Ursulin (2020-10-13 10:46:12)

Quoted 5 lines

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

Hmm. That caught me by surprise, but yes while close(group) does call free_event() on all its children [aiui], it will not remove the fd and each event does receive its own fd. And since close(child) will call into perf_event_release, we do have to keep the fd alive until the end.

Quoted 10 lines
Signed-off-by Tvrtko Ursulin <[email protected]>
---
 tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
 1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +0 -0
index 873b275dca6b..6f8bec28d274 100644

tests/i915/perf_pmu.c busy_check_all(int gem_fd, const struct intel_execution_engine2 *e, · line 479

Quoted 6 lines
tests/i915/perf_pmu.c +2 -1
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
        end_spin(gem_fd, spin, FLAG_SYNC);
        igt_spin_free(gem_fd, spin);
-       close(fd[0]);
+       for (i = 0; i < num_engines; i++)
+               close(fd[i]);

close_group(fd, num_engines) ?
-Chris
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author
#4 lore raw
Quoted 23 lines · Chris Wilson

Quoting Tvrtko Ursulin (2020-10-13 10:46:12)

Quoted 5 lines

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

Hmm. That caught me by surprise, but yes while close(group) does call free_event() on all its children [aiui], it will not remove the fd and each event does receive its own fd. And since close(child) will call into perf_event_release, we do have to keep the fd alive until the end.

Quoted 11 lines
Signed-off-by Tvrtko Ursulin <[email protected]>
---
  tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
  1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +0 -0
index 873b275dca6b..6f8bec28d274 100644
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
Quoted 7 lines

tests/i915/perf_pmu.c busy_check_all(int gem_fd, const struct intel_execution_engine2 *e, · line 479

Quoted 5 lines
tests/i915/perf_pmu.c +2 -1
         end_spin(gem_fd, spin, FLAG_SYNC);
         igt_spin_free(gem_fd, spin);
-       close(fd[0]);
+       for (i = 0; i < num_engines; i++)
+               close(fd[i]);

close_group(fd, num_engines) ?

I am not too keen on that since there is local open_group which does not operate on the fd array. Making open_group manage the array and count crossed my mind but it felt a bit too much.

Regards,

Tvrtko

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Reviewed-by
#5 lore raw

Quoting Tvrtko Ursulin (2020-10-13 11:34:11)

Quoted 33 lines · Chris Wilson
Quoted 23 lines

Quoting Tvrtko Ursulin (2020-10-13 10:46:12)

Quoted 5 lines

From: Tvrtko Ursulin <[email protected]>

As it turns out opening the perf fd in group mode still produces separate file descriptors for all members of the group, which in turn need to be closed manually to avoid leaking them.

Hmm. That caught me by surprise, but yes while close(group) does call free_event() on all its children [aiui], it will not remove the fd and each event does receive its own fd. And since close(child) will call into perf_event_release, we do have to keep the fd alive until the end.

Quoted 11 lines
Signed-off-by Tvrtko Ursulin <[email protected]>
---
  tests/i915/perf_pmu.c | 130 +++++++++++++++++++++++++-----------------
  1 file changed, 78 insertions(+), 52 deletions(-)
tests/i915/perf_pmu.c +0 -0
index 873b275dca6b..6f8bec28d274 100644
@@ -475,7 +475,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
Quoted 7 lines

tests/i915/perf_pmu.c busy_check_all(int gem_fd, const struct intel_execution_engine2 *e, · line 479

Quoted 5 lines
tests/i915/perf_pmu.c +2 -1
         end_spin(gem_fd, spin, FLAG_SYNC);
         igt_spin_free(gem_fd, spin);
-       close(fd[0]);
+       for (i = 0; i < num_engines; i++)
+               close(fd[i]);

close_group(fd, num_engines) ?

Quoted 3 lines

I am not too keen on that since there is local open_group which does not operate on the fd array. Making open_group manage the array and count crossed my mind but it felt a bit too much.

Ok, I was thinking I could live with the implementation asymmetry for the semantic symmetry :)

Reviewed-by Chris Wilson <[email protected]>
[trusting in CI to do a better job validating all the extra loops]

I did ponder whether using a dup2() to prove the group was closed (and not closed before the fixes), but that seems pointless. However maybe something like count("/proc/self/fd") at the end to see if we've caught all the leaks?
-Chris
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CI
#6 lore raw

[igt-dev] ✓ Fi.CI.BAT: success for i915/perf_pmu: Fix perf fd leak (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: i915/perf_pmu: Fix perf fd leak (rev2)
URL : https://patchwork.freedesktop.org/series/82611/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9135 -> IGTPW_5061
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html

Known issues
------------

Here are the changes found in IGTPW_5061 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_flink_basic@basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-tgl-y/igt@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-tgl-y/igt@[email protected]

* igt@i915_module_load@reload:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / [k.org#205379])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-tgl-y/igt@[email protected]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-tgl-y/igt@[email protected]

* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-bsw-kefka/igt@[email protected]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-bsw-kefka/igt@[email protected]

* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-tgl-y/igt@kms_flip@[email protected]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-tgl-y/igt@kms_flip@[email protected]

* igt@vgem_basic@unload:
- fi-skl-guc: [PASS][9] -> [DMESG-WARN][10] ([i915#2203]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-skl-guc/igt@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-skl-guc/igt@[email protected]

#### Possible fixes ####

* igt@gem_flink_basic@bad-flink:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-tgl-y/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-tgl-y/igt@[email protected]

* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-byt-j1900/igt@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-byt-j1900/igt@[email protected]
- fi-bsw-n3050: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-bsw-n3050/igt@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-bsw-n3050/igt@[email protected]

* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-icl-u2/igt@[email protected]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-icl-u2/igt@[email protected]
- fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-bsw-kefka/igt@[email protected]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-bsw-kefka/igt@[email protected]
- fi-apl-guc: [DMESG-WARN][21] ([i915#1635] / [i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-apl-guc/igt@[email protected]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-apl-guc/igt@[email protected]

* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- {fi-tgl-dsi}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/fi-tgl-dsi/igt@[email protected]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/fi-tgl-dsi/igt@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379

Participating hosts (47 -> 41)
------------------------------

Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus

Build changes
-------------

* CI: CI-20190529 -> None
* IGT: IGT_5813 -> IGTPW_5061

CI-20190529: 20190529
CI_DRM_9135: eb70ad33fcc91d3464b07679391fb477927ad4c7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5061: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html

_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev

CI
#7 lore raw

[igt-dev] ✗ Fi.CI.IGT: failure for i915/perf_pmu: Fix perf fd leak (rev2)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: i915/perf_pmu: Fix perf fd leak (rev2)
URL : https://patchwork.freedesktop.org/series/82611/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9135_full -> IGTPW_5061_full
====================================================

Summary
-------

**FAILURE**

Serious unknown changes coming with IGTPW_5061_full absolutely need to be verified manually.

If you think the reported changes have nothing to do with the changes introduced in IGTPW_5061_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in IGTPW_5061_full:

### IGT changes ###

#### Possible regressions ####

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [PASS][1] -> [FAIL][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb3/igt@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb5/igt@[email protected]

#### Warnings ####

* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-tglb: [DMESG-FAIL][3] ([i915#1982]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb8/igt@[email protected]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb5/igt@[email protected]

Known issues
------------

Here are the changes found in IGTPW_5061_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@feature_discovery@psr2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb2/igt@[email protected]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb5/igt@[email protected]

* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [PASS][7] -> [TIMEOUT][8] ([i915#1976])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-hsw2/igt@[email protected]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-hsw2/igt@[email protected]

* igt@gem_exec_gttfill@engines@rcs0:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-glk3/igt@gem_exec_gttfill@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-glk3/igt@gem_exec_gttfill@[email protected]

* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#454])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb1/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb8/igt@[email protected]

* igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl7/igt@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl4/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +6 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html

* igt@kms_prime@basic-crc@first-to-second:
- shard-iclb: [PASS][17] -> [SKIP][18] ([i915#1836])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb7/igt@kms_prime@[email protected]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb5/igt@kms_prime@[email protected]
- shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-snb6/igt@kms_prime@[email protected]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-snb4/igt@kms_prime@[email protected]
- shard-hsw: [PASS][21] -> [SKIP][22] ([fdo#109271])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-hsw2/igt@kms_prime@[email protected]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-hsw2/igt@kms_prime@[email protected]
- shard-kbl: [PASS][23] -> [SKIP][24] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl1/igt@kms_prime@[email protected]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl6/igt@kms_prime@[email protected]
- shard-apl: [PASS][25] -> [SKIP][26] ([fdo#109271] / [i915#1635])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl1/igt@kms_prime@[email protected]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl7/igt@kms_prime@[email protected]
- shard-tglb: [PASS][27] -> [SKIP][28] ([i915#1836])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb6/igt@kms_prime@[email protected]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb8/igt@kms_prime@[email protected]
- shard-glk: [PASS][29] -> [SKIP][30] ([fdo#109271])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-glk7/igt@kms_prime@[email protected]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-glk6/igt@kms_prime@[email protected]

* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb2/igt@kms_psr@psr2_suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb4/igt@kms_psr@psr2_suspend.html

* igt@kms_setmode@basic:
- shard-apl: [PASS][33] -> [FAIL][34] ([i915#1635] / [i915#31])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl6/igt@[email protected]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl1/igt@[email protected]

#### Possible fixes ####

* {igt@gem_exec_capture@pi@bcs0}:
- shard-glk: [INCOMPLETE][35] -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-glk1/igt@gem_exec_capture@[email protected]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-glk5/igt@gem_exec_capture@[email protected]

* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][37] ([i915#2521]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl2/igt@[email protected]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl2/igt@[email protected]

* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- shard-tglb: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb1/igt@[email protected]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb7/igt@[email protected]

* igt@kms_cursor_legacy@pipe-b-torture-move:
- shard-tglb: [DMESG-WARN][41] ([i915#128]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb7/igt@[email protected]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb2/igt@[email protected]

* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-glk3/igt@[email protected]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-glk8/igt@[email protected]

* igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
- shard-kbl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl4/igt@kms_flip@[email protected]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl1/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][47] ([i915#1635] / [i915#79]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl8/igt@kms_flip@[email protected]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl2/igt@kms_flip@[email protected]

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [FAIL][49] -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb7/igt@[email protected]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb7/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb8/igt@[email protected]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb1/igt@[email protected]

* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: [FAIL][53] ([i915#1635] / [i915#247]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl2/igt@[email protected]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl8/igt@[email protected]
- shard-kbl: [FAIL][55] ([i915#247]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl6/igt@[email protected]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl4/igt@[email protected]

* igt@kms_prime@basic-crc@second-to-first:
- shard-apl: [SKIP][57] ([fdo#109271] / [i915#1635]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl1/igt@kms_prime@[email protected]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl7/igt@kms_prime@[email protected]
- shard-kbl: [SKIP][59] ([fdo#109271]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl1/igt@kms_prime@[email protected]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl6/igt@kms_prime@[email protected]
- shard-hsw: [SKIP][61] ([fdo#109271]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-hsw2/igt@kms_prime@[email protected]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-hsw2/igt@kms_prime@[email protected]
- shard-iclb: [SKIP][63] ([i915#1836]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb7/igt@kms_prime@[email protected]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb5/igt@kms_prime@[email protected]
- shard-snb: [SKIP][65] ([fdo#109271]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-snb6/igt@kms_prime@[email protected]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-snb4/igt@kms_prime@[email protected]
- shard-tglb: [SKIP][67] ([i915#1836]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb6/igt@kms_prime@[email protected]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb8/igt@kms_prime@[email protected]
- shard-glk: [SKIP][69] ([fdo#109271]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-glk7/igt@kms_prime@[email protected]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-glk6/igt@kms_prime@[email protected]

* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

* igt@sysfs_heartbeat_interval@mixed@vcs1:
- shard-kbl: [INCOMPLETE][73] ([i915#1731]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-kbl4/igt@sysfs_heartbeat_interval@[email protected]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-kbl2/igt@sysfs_heartbeat_interval@[email protected]

#### Warnings ####

* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][75] ([i915#1515]) -> [FAIL][76] ([i915#1515])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-iclb7/igt@[email protected]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-iclb3/igt@[email protected]

* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][77] ([fdo#110321] / [fdo#110336] / [i915#1635]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-apl3/igt@[email protected]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-apl8/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
- shard-tglb: [FAIL][79] -> [DMESG-FAIL][80] ([i915#1982]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9135/shard-tglb2/igt@[email protected]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/shard-tglb7/igt@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1976]: https://gitlab.freedesktop.org/drm/intel/issues/1976
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#247]: https://gitlab.freedesktop.org/drm/intel/issues/247
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95

Participating hosts (11 -> 8)
------------------------------

Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7

Build changes
-------------

* CI: CI-20190529 -> None
* IGT: IGT_5813 -> IGTPW_5061
* Piglit: piglit_4509 -> None

CI-20190529: 20190529
CI_DRM_9135: eb70ad33fcc91d3464b07679391fb477927ad4c7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5061: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5061/index.html

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