arm64: tegra186: Add missing CPU PMUs
Subsystems (2)
PATCH 1/1 arm64: tegra186: Add missing CPU PMUs
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem.
--- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/nvidia/tegra186.dtsi +22 -6
@@ -1321,7 +1321,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + denver_0: cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>;
@@ -1334,7 +1334,7 @@ cpu@0 { reg = <0x000>; }; - cpu@1 { + denver_1: cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>;
@@ -1347,7 +1347,7 @@ cpu@1 { reg = <0x001>; }; - cpu@2 { + ca57_0: cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;
@@ -1360,7 +1360,7 @@ cpu@2 { reg = <0x100>; }; - cpu@3 { + ca57_1: cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;
@@ -1373,7 +1373,7 @@ cpu@3 { reg = <0x101>; }; - cpu@4 { + ca57_2: cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;
@@ -1386,7 +1386,7 @@ cpu@4 { reg = <0x102>; }; - cpu@5 { + ca57_3: cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;
@@ -1418,6 +1418,22 @@ L2_A57: l2-cache1 { }; }; + pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&denver_0 &denver_1>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; + }; + thermal-zones { a57 { polling-delay = <0>;
Signature · 1 line
2.28.0
Quoted 67 lines · Marc Zyngier
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem.
Signed-off-by Marc Zyngier <[email protected]>--- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-)arch/arm64/boot/dts/nvidia/tegra186.dtsi +6
-6@@ -1321,7 +1321,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + denver_0: cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>;@@ -1334,7 +1334,7 @@ cpu@0 { reg = <0x000>; }; - cpu@1 { + denver_1: cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>;@@ -1347,7 +1347,7 @@ cpu@1 { reg = <0x001>; }; - cpu@2 { + ca57_0: cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;@@ -1360,7 +1360,7 @@ cpu@2 { reg = <0x100>; }; - cpu@3 { + ca57_1: cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;@@ -1373,7 +1373,7 @@ cpu@3 { reg = <0x101>; }; - cpu@4 { + ca57_2: cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;@@ -1386,7 +1386,7 @@ cpu@4 { reg = <0x102>; }; - cpu@5 { + ca57_3: cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>;
arch/arm64/boot/dts/nvidia/tegra186.dtsi L2_A57: l2-cache1 { · line 1422
Quoted 5 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi +2
-0@@ -1418,6 +1418,22 @@ L2_A57: l2-cache1 { }; }; + pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
checkpatch complains that this isn't documented. Did I miss the DT bindings patch or do we not have one for this?
Thierry
Quoted 5 lines · Thierry Reding
Quoted 4 lines · Marc Zyngier
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem.
Signed-off-by Marc Zyngier <[email protected]>
[...]
Quoted 6 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi L2_A57: l2-cache1 { · line 1422
Quoted 3 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi +2
-0+ pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";checkpatch complains that this isn't documented. Did I miss the DT bindings patch or do we not have one for this?
We don't. But I don't think adding a compatible string for each and every micro-architecture makes much sense unless we have something useful to add to that compatible string. Such as a full description of the implementation specific events.
Thanks,
M.
Quoted 16 lines · Marc Zyngier
Quoted 5 lines · Thierry Reding
Quoted 4 lines · Marc Zyngier
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem.
Signed-off-by Marc Zyngier <[email protected]>[...]
Quoted 6 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi L2_A57: l2-cache1 { · line 1422
Quoted 3 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi +2
-0+ pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";checkpatch complains that this isn't documented. Did I miss the DT bindings patch or do we not have one for this?
Quoted 4 lines
We don't. But I don't think adding a compatible string for each and every micro-architecture makes much sense unless we have something useful to add to that compatible string. Such as a full description of the implementation specific events.
I'm wondering if this isn't going to upset Rob's json-schema bot and make him mad.
Thierry
Quoted 17 lines · Thierry Reding
Quoted 16 lines · Marc Zyngier
Quoted 5 lines · Thierry Reding
Quoted 4 lines · Marc Zyngier
Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem.
Signed-off-by Marc Zyngier <[email protected]>[...]
Quoted 6 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi L2_A57: l2-cache1 { · line 1422
Quoted 3 lines
arch/arm64/boot/dts/nvidia/tegra186.dtsi +2
-0+ pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";checkpatch complains that this isn't documented. Did I miss the DT bindings patch or do we not have one for this?
Quoted 7 lines
Quoted 4 lines
We don't. But I don't think adding a compatible string for each and every micro-architecture makes much sense unless we have something useful to add to that compatible string. Such as a full description of the implementation specific events.
I'm wondering if this isn't going to upset Rob's json-schema bot and make him mad.
Rob going mad? Never! ;-)
If you *really* want it, I'll respin this patch with the Denver compatible added to Documentation/devicetree/bindings/arm/pmu.yaml.
M.
Signature · 1 line
Jazz is not dead. It just smells funny...