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mtd: rawnand: ifc: Move the ECC engine initialization to the right place

PATCH Applied Fabio Estevam 3 participants 4 messages Oct 16, 2020 – Oct 26, 2020

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v2 of 3 Applied Latest is v3 →

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#0 lore raw

PATCH v2 1/1 mtd: rawnand: ifc: Move the ECC engine initialization to the right place

No ECC initialization should happen during the host controller probe.

In fact, we need the probe function to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Moving these lines to fsl_ifc_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

Based on a fix done for the mxc_nand driver by Miquel Raynal.

---
Changes since v1:
- Do not remove a blank line

 drivers/mtd/nand/raw/fsl_ifc_nand.c | 43 ++++++++++++++++-------------
 1 file changed, 24 insertions(+), 19 deletions(-)
drivers/mtd/nand/raw/fsl_ifc_nand.c +24 -19
index 0e7a9b64301e..e345f9d9f8e8 100644
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
 {
 	struct mtd_info *mtd = nand_to_mtd(chip);
 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
+	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+	struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
+	u32 csor;
+
+	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
+
+	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
+	if (csor & CSOR_NAND_ECC_DEC_EN) {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
+
+		/* Hardware generates ECC per 512 Bytes */
+		chip->ecc.size = 512;
+		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
+			chip->ecc.bytes = 8;
+			chip->ecc.strength = 4;
+		} else {
+			chip->ecc.bytes = 16;
+			chip->ecc.strength = 8;
+		}
+	} else {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+	}
 
 	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 		nanddev_ntargets(&chip->base));
@@ -910,25 +934,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 		return -ENODEV;
 	}
 
-	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
-	if (csor & CSOR_NAND_ECC_DEC_EN) {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
-
-		/* Hardware generates ECC per 512 Bytes */
-		chip->ecc.size = 512;
-		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
-			chip->ecc.bytes = 8;
-			chip->ecc.strength = 4;
-		} else {
-			chip->ecc.bytes = 16;
-			chip->ecc.strength = 8;
-		}
-	} else {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
-	}
-
 	ret = fsl_ifc_sram_init(priv);
 	if (ret)
 		return ret;
Signature · 6 lines
2.17.1


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Tested-by on v2 1/1
#1 lore raw
Quoted 21 lines

-----Original Message-----
From: Fabio Estevam <[email protected]>
Sent: Friday, October 16, 2020 8:26 AM
To: [email protected]
Cc: [email protected]; [email protected]; [email protected]; linux- [email protected]; Han Xu <[email protected]>; [email protected]; Fabio Estevam <[email protected]>
Subject: [EXT] [PATCH v2] mtd: rawnand: ifc: Move the ECC engine initialization to the right place

Caution: EXT Email

No ECC initialization should happen during the host controller probe.

In fact, we need the probe function to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Quoted 7 lines

Moving these lines to fsl_ifc_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

Based on a fix done for the mxc_nand driver by Miquel Raynal.

Quoted 71 lines

---
Changes since v1:
- Do not remove a blank line

 drivers/mtd/nand/raw/fsl_ifc_nand.c | 43 ++++++++++++++++-------------
 1 file changed, 24 insertions(+), 19 deletions(-)
drivers/mtd/nand/raw/fsl_ifc_nand.c +24 -0
index 0e7a9b64301e..e345f9d9f8e8 100644
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)  {
        struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
+       struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+       struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
+       u32 csor;
+
+       csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
+
+       /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
+       if (csor & CSOR_NAND_ECC_DEC_EN) {
+               chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+               mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
+
+               /* Hardware generates ECC per 512 Bytes */
+               chip->ecc.size = 512;
+               if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 CSOR_NAND_ECC_MODE_4) {
+                       chip->ecc.bytes = 8;
+                       chip->ecc.strength = 4;
+               } else {
+                       chip->ecc.bytes = 16;
+                       chip->ecc.strength = 8;
+               }
+       } else {
+               chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+       }
 
        dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
                nanddev_ntargets(&chip->base)); @@ -910,25 +934,6 @@ static int

fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)

                return -ENODEV;
        }
drivers/mtd/nand/raw/fsl_ifc_nand.c +0 -8
-       /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
-       if (csor & CSOR_NAND_ECC_DEC_EN) {
-               chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-               mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
-
-               /* Hardware generates ECC per 512 Bytes */
-               chip->ecc.size = 512;
-               if ((csor & CSOR_NAND_ECC_MODE_MASK) ==

CSOR_NAND_ECC_MODE_4) {

drivers/mtd/nand/raw/fsl_ifc_nand.c +0 -12
-                       chip->ecc.bytes = 8;
-                       chip->ecc.strength = 4;
-               } else {
-                       chip->ecc.bytes = 16;
-                       chip->ecc.strength = 8;
-               }
-       } else {
-               chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
-       }
-
        ret = fsl_ifc_sram_init(priv);
        if (ret)
                return ret;
--
Quoted 1 line

2.17.1

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maintainer Applied
#2 lore raw
In reply to Fabio Estevam
Quoted 7 lines · Fabio Estevam

No ECC initialization should happen during the host controller probe.

In fact, we need the probe function to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Quoted 8 lines

Moving these lines to fsl_ifc_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

Based on a fix done for the mxc_nand driver by Miquel Raynal.

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/fixes, thanks.

Miquel

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maintainer
#3 lore raw

Hello,

Miquel Raynal <[email protected]> wrote on Mon, 26 Oct 2020 18:45:25 +0100:

Quoted 11 lines · Fabio Estevam
Quoted 10 lines

No ECC initialization should happen during the host controller probe.

In fact, we need the probe function to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Moving these lines to fsl_ifc_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

Quoted 7 lines
Quoted 5 lines

Based on a fix done for the mxc_nand driver by Miquel Raynal.

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/fixes, thanks.

FYI I've added a Fixes tag.

Thanks,
Miquèl

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