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mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read

PATCH Applied Praveenkumar I 2 participants 4 messages Oct 9, 2020 – Oct 30, 2020 1 message not in the archive

Subsystems (4)
Stable branch Memory technology devices (MTD) NAND flash Qualcomm NAND controller driver
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Praveenkumar I

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#0 lore raw

PATCH 1/1 mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read

After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf.

This patch adds the DMA sync on reg_read_buf for CPU before reading it.

Fixes 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")
Signed-off-by Praveenkumar I <[email protected]>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/mtd/nand/raw/qcom_nandc.c +2 -0
index bd7a7251429b..5bb85f1ba84c 100644
@@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 	int i;
 
+	nandc_read_buffer_sync(nandc, true);
+
 	for (i = 0; i < cw_cnt; i++) {
 		u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
Signature · 2 lines
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maintainer
#1 lore raw

Hello,

Praveenkumar I <[email protected]> wrote on Fri, 9 Oct 2020 13:37:52 +0530:

Quoted 7 lines

After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf.

This patch adds the DMA sync on reg_read_buf for CPU before reading it.

Fixes 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")

I guess this deserves a proper Cc: stable tag?

Quoted 1 line
Signed-off-by Praveenkumar I <[email protected]>

I think your full name is required in the SoB line (should match the authorship).

Otherwise looks good to me.

Quoted 9 lines
---
 drivers/mtd/nand/raw/qcom_nandc.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/mtd/nand/raw/qcom_nandc.c +0 -0
index bd7a7251429b..5bb85f1ba84c 100644

drivers/mtd/nand/raw/qcom_nandc.c static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt) · line 1577

Quoted 8 lines
drivers/mtd/nand/raw/qcom_nandc.c +2 -0
@@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 	int i;
 
+	nandc_read_buffer_sync(nandc, true);
+
 	for (i = 0; i < cw_cnt; i++) {
 		u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);

Thanks,
Miquèl

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Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

A message that is not in the archive (sent off-list or not yet received): [email protected]

maintainer
#3 lore raw

Hello,

Praveenkumar I <[email protected]> wrote on Wed, 28 Oct 2020 19:48:34 +0530:

Quoted 23 lines

Hi Miquel,

Please find the inline reply.

Thanks,
Praveenkumar I

Quoted 14 lines · Miquel Raynal

Hello,

Praveenkumar I <[email protected]> wrote on Fri, 9 Oct 2020 13:37:52 +0530:

Quoted 7 lines

After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf.

This patch adds the DMA sync on reg_read_buf for CPU before reading it.

Fixes 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")

I guess this deserves a proper Cc: stable tag?

Quoted 1 line
Quoted 1 line

Yes. I will send a V2 Patch with stable tag in Cc

That's fine for this one, I'll add it myself.

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Signed-off-by Praveenkumar I <[email protected]>

I think your full name is required in the SoB line (should match the authorship).

Quoted 1 line
Quoted 1 line

"Praveenkumar I" is my full name and it is same as the authorship.

Ok, sorry for the confusion.

Quoted 6 lines
Quoted 6 lines

Otherwise looks good to me.

Quoted 4 lines
---
  drivers/mtd/nand/raw/qcom_nandc.c | 2 ++
  1 file changed, 2 insertions(+)
Quoted 14 lines
Quoted 5 lines
Quoted 5 lines
drivers/mtd/nand/raw/qcom_nandc.c +0 -0
index bd7a7251429b..5bb85f1ba84c 100644
@@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
Quoted 8 lines

drivers/mtd/nand/raw/qcom_nandc.c static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)

Quoted 7 lines
drivers/mtd/nand/raw/qcom_nandc.c +1 -0
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  	int i;  
  >> +	nandc_read_buffer_sync(nandc, true);  
+
  	for (i = 0; i < cw_cnt; i++) {
  		u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);  
  > Thanks,

Miquèl

Cheers,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

maintainer Applied
#4 lore raw
In reply to Praveenkumar I
Quoted 8 lines · Praveenkumar I

After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf.

This patch adds the DMA sync on reg_read_buf for CPU before reading it.

Fixes 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")
Signed-off-by Praveenkumar I <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel