Add PCIe support for SM8250 SoC
Subsystems (6)
v5 cover Add PCIe support for SM8250 SoC
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support.
This series has been tested on RB5 board with QCA6391 chipset connected onboard.
Thanks,
Mani
Changes in v5:
* Added Review tags from Rob
* Cleaned up the bdf to sid patch after discussing with Tony
Changes in v4:
* Fixed an issue with tx_tbl_sec in PHY driver
Changes in v3:
* Rebased on top of phy/next
* Renamed ops_sm8250 to ops_1_9_0 to maintain uniformity
Changes in v2:
* Fixed the PHY and PCIe bindings
* Introduced secondary table in PHY driver to abstract out the common configs.
* Used a more generic way of configuring BDF to SID mapping
* Dropped ATU change in favor of a patch spotted by Rob
Manivannan Sadhasivam (5):
dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: qcom: Add SM8250 SoC support
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
.../devicetree/bindings/pci/qcom,pcie.txt | 6 +- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 + drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 92 ++++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 281 +++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp.h | 18 ++ 6 files changed, 398 insertions(+), 6 deletions(-)
Signature · 1 line
2.17.1
PATCH v5 1/5 dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
Add the below three PCIe PHYs found in SM8250 to the QMP binding:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
QMP Modem PHY - 2 lanes
--- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +6 -0
@@ -31,6 +31,9 @@ properties: - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy reg: items:
@@ -259,6 +262,9 @@ allOf: enum: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy then: properties: clocks:
Signature · 1 line
2.17.1
Re: [PATCH v5 1/5] dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
Quoted 6 lines · Manivannan Sadhasivam
Add the below three PCIe PHYs found in SM8250 to the QMP binding:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
QMP Modem PHY - 2 lanes
Applied, thanks
Signature · 1 line
~Vinod
PATCH v5 2/5 phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
In reply to Manivannan SadhasivamSM8250 has multiple different PHY versions:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
QMP Modem PHY - 2 lanes
Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence.
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 281 +++++++++++++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp.h | 18 ++ 2 files changed, 295 insertions(+), 4 deletions(-)
drivers/phy/qualcomm/phy-qcom-qmp.c +277 -4
@@ -217,6 +217,13 @@ static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_READY_STATUS] = 0x160, }; +static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE ] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x44 , + [QPHY_PCS_STATUS ] =0x14 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x40 , +}; +static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE ] = { [QPHY_START_CTRL ] =QPHY_V4_PCS_UFS_PHY_START , [QPHY_PCS_READY_STATUS ] =QPHY_V4_PCS_UFS_READY_STATUS ,
@@ -1824,6 +1831,149 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), }; +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SYSCLK_EN_SEL ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CLK_SELECT ,0x34 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CORECLK_DIV_MODE1 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_IVCO ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP_EN ,0x42 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE1_MODE0 ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE2_MODE1 ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE1_MODE1 ,0xb4 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_VCO_TUNE_MAP ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL ,0x11 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DEC_START_MODE0 ,0x82 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START3_MODE0 ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START2_MODE0 ,0x55 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START1_MODE0 ,0x55 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP2_MODE0 ,0x1a ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP1_MODE0 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DEC_START_MODE1 ,0x68 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START3_MODE1 ,0x02 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START2_MODE1 ,0xaa ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_DIV_FRAC_START1_MODE1 ,0xab ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP2_MODE1 ,0x34 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_LOCK_CMP1_MODE1 ,0x14 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_HSCLK_SEL ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CP_CTRL_MODE0 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_RCTRL_MODE0 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_CCTRL_MODE0 ,0x36 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CP_CTRL_MODE1 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_RCTRL_MODE1 ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_PLL_CCTRL_MODE1 ,0x36 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 ,0x1e ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 ,0xca ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 ,0x18 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 ,0xa2 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_EN_CENTER ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_PER1 ,0x31 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_PER2 ,0x01 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 ,0xde ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 ,0x07 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 ,0x4c ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 ,0x06 ), +QMP_PHY_INIT_CFG (QSERDES_V4_COM_CLK_ENABLE1 ,0x90 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_COM_SYSCLK_BUF_ENABLE ,0x07 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_LANE_MODE_1 ,0x35 ), +QMP_PHY_INIT_CFG (QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX ,0x11 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_FO_GAIN ,0x0c ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SO_GAIN ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_GM_CAL ,0x1b ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW ,0xc0 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE ,0x30 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_VGA_CAL_CNTRL1 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_VGA_CAL_CNTRL2 ,0x07 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_UCDR_PI_CONTROLS ,0x70 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4a ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_SIGDET_CNTRL ,0x03 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_SIGDET_ENABLES ,0x1c ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL ,0x1e ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x17 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_10_LOW ,0xd4 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_10_HIGH ,0x54 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_10_HIGH2 ,0xdb ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_10_HIGH3 ,0x3b ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_10_HIGH4 ,0x31 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_LOW ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH2 ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH3 ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DCC_CTRL1 ,0x0c ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH ,0xe4 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH2 ,0xec ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH3 ,0x3b ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_01_HIGH4 ,0x36 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RCLK_AUXDATA_SEL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DFE_EN_TIMER ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_LOW ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH4 ,0x14 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET ,0x30 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RX_SIGDET_LVL ,0x77 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RATE_SLEW_CNTRL1 ,0x0b ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_REFGEN_REQ_CONFIG1 ,0x0d ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG5 ,0x12 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L ,0x01 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE ,0x33 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_PRESET_P10_PRE ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_PRESET_P10_POST ,0x58 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE ,0xc1 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_EQ_CONFIG2 ,0x0f ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_TX_PI_QEC_CTRL ,0x20 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_LOW ,0xbf ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_RX_MODE_00_HIGH4 ,0x15 ), +QMP_PHY_INIT_CFG (QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET ,0x38 ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_REFGEN_REQ_CONFIG1 ,0x05 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG2 ,0x0f ), +}; + +static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 ,0x0d ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 ,0x07 ), +}; +/* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg {/* phy-type - PCIE/UFS/USB */
@@ -1834,14 +1984,24 @@ struct qmp_phy_cfg {/* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl;int serdes_tbl_num; +const struct qmp_phy_init_tbl *serdes_tbl_sec; +int serdes_tbl_num_sec;const struct qmp_phy_init_tbl *tx_tbl;int tx_tbl_num; +const struct qmp_phy_init_tbl *tx_tbl_sec; +int tx_tbl_num_sec;const struct qmp_phy_init_tbl *rx_tbl;int rx_tbl_num; +const struct qmp_phy_init_tbl *rx_tbl_sec; +int rx_tbl_num_sec;const struct qmp_phy_init_tbl *pcs_tbl;int pcs_tbl_num; +const struct qmp_phy_init_tbl *pcs_tbl_sec; +int pcs_tbl_num_sec;const struct qmp_phy_init_tbl *pcs_misc_tbl;int pcs_misc_tbl_num; +const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; +int pcs_misc_tbl_num_sec;/* Init sequence for DP PHY block link rates */ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
@@ -2245,6 +2405,83 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .pwrdn_delay_max = 1005, /* us */ }; +static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { + .type =PHY_TYPE_PCIE , + .nlanes =1 , + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks =ARRAY_SIZE (sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets =ARRAY_SIZE (sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl =PCS_START |SERDES_START , + .pwrdn_ctrl =SW_PWRDN |REFCLK_DRV_DSBL , + + .has_pwrdn_delay = true, + .pwrdn_delay_min =995 ,/* us */ + .pwrdn_delay_max =1005 ,/* us */ +}; + +static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { + .type =PHY_TYPE_PCIE , + .nlanes =2 , + + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_serdes_tbl), + .tx_tbl = sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =ARRAY_SIZE (sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =ARRAY_SIZE (sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks =ARRAY_SIZE (sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets =ARRAY_SIZE (sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl =PCS_START |SERDES_START , + .pwrdn_ctrl =SW_PWRDN |REFCLK_DRV_DSBL , + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min =995 ,/* us */ + .pwrdn_delay_max =1005 ,/* us */ +}; +static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .type =PHY_TYPE_USB3 , .nlanes =1 ,
@@ -2629,6 +2866,9 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)int ret;qcom_qmp_phy_configure (serdes, cfg->regs, serdes_tbl, serdes_tbl_num); +if (cfg->serdes_tbl_sec) +qcom_qmp_phy_configure (serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec);if (cfg->type ==PHY_TYPE_DP ) {switch (dp_opts->link_rate) {
@@ -3117,10 +3357,19 @@ static int qcom_qmp_phy_power_on(struct phy *phy)/* Tx, Rx, and PCS configurations */ qcom_qmp_phy_configure_lane (tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num,1 ); +if (cfg->tx_tbl_sec) +qcom_qmp_phy_configure_lane (tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec,1 ); +/* Configuration for other LANE for USB-DP combo PHY */ -if (cfg->is_dual_lane_phy) +if (cfg->is_dual_lane_phy) {qcom_qmp_phy_configure_lane (qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num,2 ); +if (cfg->tx_tbl_sec) +qcom_qmp_phy_configure_lane (qphy->tx2, cfg->regs, + cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec,2 ); + }/* Configure special DP tx tunings */ if (cfg->type ==PHY_TYPE_DP )
@@ -3128,16 +3377,28 @@ static int qcom_qmp_phy_power_on(struct phy *phy)qcom_qmp_phy_configure_lane (rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num,1 ); +if (cfg->rx_tbl_sec) +qcom_qmp_phy_configure_lane (rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec,1 ); -if (cfg->is_dual_lane_phy) +if (cfg->is_dual_lane_phy) {qcom_qmp_phy_configure_lane (qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num,2 ); +if (cfg->rx_tbl_sec) +qcom_qmp_phy_configure_lane (qphy->rx2, cfg->regs, + cfg->rx_tbl_sec, + cfg->rx_tbl_num_sec,2 ); + }/* Configure link rate, swing, etc. */ -if (cfg->type ==PHY_TYPE_DP ) +if (cfg->type ==PHY_TYPE_DP ) {qcom_qmp_phy_configure_dp_phy (qphy); -else + }else {qcom_qmp_phy_configure (pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); +if (cfg->pcs_tbl_sec) +qcom_qmp_phy_configure (pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + } ret =reset_control_deassert (qmp->ufs_reset);if (ret)
@@ -3145,6 +3406,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)qcom_qmp_phy_configure (pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); +if (cfg->pcs_misc_tbl_sec) +qcom_qmp_phy_configure (pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec);/* * Pull out PHY from POWER DOWN state.
@@ -3900,6 +4164,15 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-usb3-uni-phy", .data = &sm8250_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", + .data = &sm8250_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-modem-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, }, { }, };
drivers/phy/qualcomm/phy-qcom-qmp.h +18 -0
@@ -403,6 +403,7 @@#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V4_COM_CLK_ENABLE1 0x048#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050#define QSERDES_V4_COM_PLL_IVCO 0x058#define QSERDES_V4_COM_CMN_IPTRIM 0x060
@@ -432,6 +433,7 @@#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V4_COM_CLK_SELECT 0x154#define QSERDES_V4_COM_HSCLK_SEL 0x158#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
@@ -471,12 +473,14 @@#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068#define QSERDES_V4_RX_AC_JTAG_MODE 0x078#define QSERDES_V4_RX_RX_TERM_BW 0x080#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8#define QSERDES_V4_RX_GM_CAL 0x0dc +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
@@ -485,6 +489,7 @@#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V4_RX_SIGDET_ENABLES 0x118#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c#define QSERDES_V4_RX_SIGDET_LVL 0x120#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
@@ -806,4 +811,17 @@#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 +/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 +#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 +#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc +#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +#endif
Signature · 1 line
2.17.1
Re: [PATCH v5 2/5] phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
Quoted 9 lines · Manivannan Sadhasivam
SM8250 has multiple different PHY versions:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
QMP Modem PHY - 2 lanesAdd support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence.
Applied, thanks
Signature · 1 line
~Vinod
PATCH v5 3/5 dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
In reply to Manivannan SadhasivamDocument the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region.
--- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/qcom,pcie.txt +4 -2
@@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required
@@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required
@@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "aux" Auxiliary clock
@@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "pci" PCIe core reset
Signature · 1 line
2.17.1
Re: [PATCH v5 3/5] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
Quoted 6 lines · Manivannan Sadhasivam
Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region.
Signed-off-by Manivannan Sadhasivam <[email protected]>Acked-by Rob Herring <[email protected]>
Quoted 45 lines
--- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/pci/qcom,pcie.txt +4
-2@@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required@@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required@@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "aux" Auxiliary clock@@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "pci" PCIe core resetSignature · 1 line
2.17.1
PATCH v5 4/5 PCI: qcom: Add SM8250 SoC support
In reply to Manivannan SadhasivamThe PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of ops_2_7_0. The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid callback, which will be added in successive commit.
--- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
drivers/pci/controller/dwc/pcie-qcom.c +11 -0
@@ -1361,6 +1361,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_deinit = qcom_pcie_post_deinit_2_7_0, }; +/* Qcom IP rev.: 1.9.0 */ +static const struct qcom_pcie_ops ops_1_9_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; +static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, };
@@ -1474,6 +1484,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };
Signature · 1 line
2.17.1
Re: [PATCH v5 4/5] PCI: qcom: Add SM8250 SoC support
Quoted 7 lines · Manivannan Sadhasivam
The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the members of
ops_2_7_0. The key difference betweenops_2_7_0andops_1_9_0is theconfig_sidcallback, which will be added in successive commit.Signed-off-by Manivannan Sadhasivam <[email protected]>Reviewed-by Rob Herring <[email protected]>
Regards,
Bjorn
Quoted 36 lines
--- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+)drivers/pci/controller/dwc/pcie-qcom.c +11
-0@@ -1361,6 +1361,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_deinit = qcom_pcie_post_deinit_2_7_0, }; +/* Qcom IP rev.: 1.9.0 */ +static const struct qcom_pcie_ops ops_1_9_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; +static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, };@@ -1474,6 +1484,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };Signature · 1 line
2.17.1
PATCH v5 5/5 PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
In reply to Manivannan SadhasivamFor SM8250, we need to write the BDF to SID mapping in PCIe controller register space for proper working. This is accomplished by extracting the BDF and SID values from "iommu-map" property in DT and writing those in the register address calculated from the hash value of BDF. In case of collisions, the index of the next entry will also be written.
For the sake of it, let's introduce a "config_sid" callback and do it conditionally for SM8250.
---
Rob: I've dropped your review tag as this patch has gone through some change (mostly cleanups though)
drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++ 2 files changed, 82 insertions(+)
drivers/pci/controller/dwc/Kconfig +1 -0
@@ -169,6 +169,7 @@ config PCIE_QCOM depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST + select CRC8 help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific
drivers/pci/controller/dwc/pcie-qcom.c +81 -0
123 lines not on this page · raw message
Signature · 1 line
2.17.1
Re: [PATCH v5 5/5] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
Quoted 10 lines · Manivannan Sadhasivam
For SM8250, we need to write the BDF to SID mapping in PCIe controller register space for proper working. This is accomplished by extracting the BDF and SID values from "iommu-map" property in DT and writing those in the register address calculated from the hash value of BDF. In case of collisions, the index of the next entry will also be written.
For the sake of it, let's introduce a "
config_sid" callback and do it conditionally for SM8250.Signed-off-by Manivannan Sadhasivam <[email protected]>
Regards,
Bjorn
Quoted 158 lines
---
Rob: I've dropped your review tag as this patch has gone through some change (mostly cleanups though)
drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++ 2 files changed, 82 insertions(+)drivers/pci/controller/dwc/Kconfig +1
-0@@ -169,6 +169,7 @@ config PCIE_QCOM depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST + select CRC8 help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specificdrivers/pci/controller/dwc/pcie-qcom.c +81
-0@@ -9,6 +9,7 @@*/ #include <linux/clk.h> +#include <linux/crc8.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/interrupt.h> @@ -57,6 +58,7 @@#define PCIE20_PARF_SID_OFFSET 0x234#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C#define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000#define PCIE20_ELBI_SYS_CTRL 0x04#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)@@ -97,6 +99,9 @@#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 + +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +struct qcom_pcie_resources_2_1_0 {struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS ];struct reset_control *pci_reset;@@ -179,6 +184,7 @@ struct qcom_pcie_ops {void (*deinit)(struct qcom_pcie *pcie);void (*post_deinit)(struct qcom_pcie *pcie);void (*ltssm_enable)(struct qcom_pcie *pcie); +int (*config_sid)(struct qcom_pcie *pcie); };struct qcom_pcie {@@ -1261,6 +1267,74 @@ static int qcom_pcie_link_up(struct dw_pcie *pci)return !!(val &PCI_EXP_LNKSTA_DLLLA ); } +static int qcom_pcie_config_sid_sm8250 (struct qcom_pcie *pcie) +{ +/* iommu map structure */ +struct { +u32 bdf; +u32 phandle; +u32 smmu_sid; +u32 smmu_sid_len; + } *map; +void __iomem *bdf_to_sid_base = pcie->parf +PCIE20_PARF_BDF_TO_SID_TABLE_N ; +struct device *dev = pcie->pci->dev; +u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE ]; +int i, nr_map, size =0 ; +u32 smmu_sid_base; + +of_get_property (dev->of_node,"iommu-map" , &size); +if (!size) +return 0 ; + + map =kzalloc (size,GFP_KERNEL ); +if (!map) +return -ENOMEM ; + +of_property_read_u32_array (dev->of_node, +"iommu-map" , (u32 *)map, size /sizeof (u32)); + + nr_map = size / (sizeof (*map)); + +crc8_populate_msb (qcom_pcie_crc8_table,QCOM_PCIE_CRC8_POLYNOMIAL ); + +/* Registers need to be zero out first */ +memset_io (bdf_to_sid_base,0 ,CRC8_TABLE_SIZE *sizeof (u32)); + +/* Look for an available entry to hold the mapping */ +for (i =0 ; i < nr_map; i++) { +u16 bdf_be =cpu_to_be16 (map[i].bdf); +u32 val; +u8 hash; + + hash =crc8 (qcom_pcie_crc8_table, (u8 *)&bdf_be,sizeof (bdf_be), +0 ); + + val =readl (bdf_to_sid_base + hash *sizeof (u32)); + +/* If the register is already populated, look for next available entry */ +while (val) { +u8 current_hash = hash++; +u8 next_mask =0xff ; + +/* If NEXT field is NULL then update it with next hash */ +if (!(val & next_mask)) { + val |= (u32 )hash; +writel (val, bdf_to_sid_base + current_hash *sizeof (u32)); + } + + val =readl (bdf_to_sid_base + hash *sizeof (u32)); + } + +/* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val = map[i].bdf <<16 | (map[i].smmu_sid - smmu_sid_base) <<8 |0 ; +writel (val, bdf_to_sid_base + hash *sizeof (u32)); + } + +kfree (map); + +return 0 ; +} +static int qcom_pcie_host_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp);@@ -1292,6 +1366,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp)if (ret) goto err; +if (pcie->ops->config_sid) { + ret = pcie->ops->config_sid (pcie); +if (ret) + goto err; + } +return 0 ; err:qcom_ep_reset_assert (pcie);@@ -1369,6 +1449,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, + .config_sid = qcom_pcie_config_sid_sm8250, };static const struct dw_pcie_ops dw_pcie_ops = {Signature · 1 line
2.17.1
Quoted 9 lines · Manivannan Sadhasivam
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support.
This series has been tested on RB5 board with QCA6391 chipset connected onboard.
Hi,
I would be merging this series, I understand patch {2) was already taken by Vinod - should I take {1,3,4,5} via the pci tree ?
Thanks,
Lorenzo
Quoted 42 lines
Thanks,
ManiChanges in v5:
* Added Review tags from Rob
* Cleaned up the bdf to sid patch after discussing with TonyChanges in v4:
* Fixed an issue with
tx_tbl_secin PHY driverChanges in v3:
* Rebased on top of phy/next
* Renamedops_sm8250toops_1_9_0to maintain uniformityChanges in v2:
* Fixed the PHY and PCIe bindings
* Introduced secondary table in PHY driver to abstract out the common configs.
* Used a more generic way of configuring BDF to SID mapping
* Dropped ATU change in favor of a patch spotted by RobManivannan Sadhasivam (5):
dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: qcom: Add SM8250 SoC support
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250.../devicetree/bindings/pci/qcom,pcie.txt | 6 +- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 + drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 92 ++++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 281 +++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp.h | 18 ++ 6 files changed, 398 insertions(+), 6 deletions(-)Signature · 1 line
2.17.1
Hi Lorenzo,
Quoted 8 lines · Lorenzo Pieralisi
Quoted 7 lines · Manivannan Sadhasivam
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support.
Quoted 8 lines
Quoted 2 lines
This series has been tested on RB5 board with QCA6391 chipset connected onboard.
Hi,
I would be merging this series, I understand patch {2) was already taken by Vinod - should I take {1,3,4,5} via the pci tree ?
Vinod merged patches 1/5 and 2/5 as they belong to phy subsystem. You can take the rest of the patches via pci tree.
Thanks,
Mani
Quoted 45 lines
Thanks,
LorenzoQuoted 42 lines
Thanks,
ManiChanges in v5:
* Added Review tags from Rob
* Cleaned up the bdf to sid patch after discussing with TonyChanges in v4:
* Fixed an issue with
tx_tbl_secin PHY driverChanges in v3:
* Rebased on top of phy/next
* Renamedops_sm8250toops_1_9_0to maintain uniformityChanges in v2:
* Fixed the PHY and PCIe bindings
* Introduced secondary table in PHY driver to abstract out the common configs.
* Used a more generic way of configuring BDF to SID mapping
* Dropped ATU change in favor of a patch spotted by RobManivannan Sadhasivam (5):
dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: qcom: Add SM8250 SoC support
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250.../devicetree/bindings/pci/qcom,pcie.txt | 6 +- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 + drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 92 ++++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 281 +++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp.h | 18 ++ 6 files changed, 398 insertions(+), 6 deletions(-)Signature · 1 line
2.17.1
Quoted 14 lines · Manivannan Sadhasivam
Hi Lorenzo,
Quoted 11 lines · Lorenzo Pieralisi
Quoted 9 lines · Manivannan Sadhasivam
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support.
This series has been tested on RB5 board with QCA6391 chipset connected onboard.
Quoted 8 lines
Quoted 5 lines
Hi,
I would be merging this series, I understand patch {2) was already taken by Vinod - should I take {1,3,4,5} via the pci tree ?
Vinod merged patches 1/5 and 2/5 as they belong to phy subsystem. You can take the rest of the patches via pci tree.
Would you mind rebasing them on top of my pci/dwc branch (with Bjorn's tags) and resend them, I will apply them then.
Thanks,
Lorenzo
Quoted 21 lines · Lorenzo Pieralisi
Quoted 20 lines · Manivannan Sadhasivam
Hi Lorenzo,
Quoted 16 lines · Lorenzo Pieralisi
Quoted 9 lines · Manivannan Sadhasivam
Hello,
This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support.
This series has been tested on RB5 board with QCA6391 chipset connected onboard.
Hi,
I would be merging this series, I understand patch {2) was already taken by Vinod - should I take {1,3,4,5} via the pci tree ?
Quoted 6 lines
Quoted 2 lines
Vinod merged patches 1/5 and 2/5 as they belong to phy subsystem. You can take the rest of the patches via pci tree.
Would you mind rebasing them on top of my pci/dwc branch (with Bjorn's tags) and resend them, I will apply them then.
Sure, will send now.
Thanks,
Mani
Quoted 2 lines
Thanks,
Lorenzo