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intel_gpu_top: Support exiting the tool by pressing 'q'

PATCH Superseded Tvrtko Ursulin 3 participants 13 messages Dec 16, 2020 – Dec 17, 2020

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#0 lore raw

PATCH 1/2 intel_gpu_top: Support exiting the tool by pressing 'q'

From: Tvrtko Ursulin <[email protected]>

Analoguous to top(1) we can enable the user to exit from the tool by pressing 'q' on the console.

---
 man/intel_gpu_top.rst |  6 ++++
 tools/intel_gpu_top.c | 77 +++++++++++++++++++++++++++++++++++--------
 2 files changed, 70 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +6 -0
index 5552e9699d26..2e0c3a05acc1 100644
@@ -48,6 +48,12 @@ OPTIONS
 -d
     Select a specific GPU using supported filter.
 
+RUNTIME CONTROL
+===============
+
+Supported keys:
+
+    'q'    Exit from the tool.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +64 -13

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#1 lore raw

PATCH 2/2 intel_gpu_top: Aggregate engine busyness per class

From: Tvrtko Ursulin <[email protected]>

Similarly to how top(1) handles SMP, we can default to showing engines of a same class as a single bar graph entry.

To achieve this a little bit of hackery is employed. PMU sampling is left as is and only at the presentation layer we create a fake set of engines, one for each class, summing and normalizing the load respectively.

---
 man/intel_gpu_top.rst |   1 +
 tools/intel_gpu_top.c | 192 +++++++++++++++++++++++++++++++++++++++---
 2 files changed, 180 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +1 -0
index 2e0c3a05acc1..35ab10da9bb4 100644
@@ -54,6 +54,7 @@ RUNTIME CONTROL
 Supported keys:
 
     'q'    Exit from the tool.
+    '1'    Toggle between aggregated engine class and physical engine mode.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +179 -13

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#2 lore raw

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class

Quoting Tvrtko Ursulin (2020-12-16 15:28:09)

Quoted 103 lines

From: Tvrtko Ursulin <[email protected]>

Similarly to how top(1) handles SMP, we can default to showing engines of a same class as a single bar graph entry.

To achieve this a little bit of hackery is employed. PMU sampling is left as is and only at the presentation layer we create a fake set of engines, one for each class, summing and normalizing the load respectively.

---
 man/intel_gpu_top.rst |   1 +
 tools/intel_gpu_top.c | 192 +++++++++++++++++++++++++++++++++++++++---
 2 files changed, 180 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +1 -0
index 2e0c3a05acc1..35ab10da9bb4 100644
@@ -54,6 +54,7 @@ RUNTIME CONTROL
 Supported keys:
 
     'q'    Exit from the tool.
+    '1'    Toggle between aggregated engine class and physical engine mode.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +43 -1
index 68911940f1d0..8c4280aa19b9 100644
@@ -76,8 +76,16 @@ struct engine {
        struct pmu_counter sema;
 };
 
+struct engine_class {
+       unsigned int class;
+       const char *name;
+       unsigned int num_engines;
+};
+
 struct engines {
        unsigned int num_engines;
+       unsigned int num_classes;
+       struct engine_class *class;
        unsigned int num_counters;
        DIR *root;
        int fd;
@@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines, int con_w, int con_h)
        return lines;
 }
 
+static bool class_view;
+
 static int
 print_engines_header(struct engines *engines, double t,
                     int lines, int con_w, int con_h)
@@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
                pops->open_struct("engines");
 
                if (output_mode == INTERACTIVE) {
-                       const char *a = "          ENGINE      BUSY ";
                        const char *b = " MI_SEMA MI_WAIT";
+                       const char *a;
+
+                       if (class_view)
+                               a = "         ENGINES     BUSY  ";
+                       else
+                               a = "          ENGINE     BUSY  ";
 
                        printf("\033[7m%s%*s%s\033[0m\n",
                               a, (int)(con_w - 1 - strlen(a) - strlen(b)),
@@ -1214,6 +1229,164 @@ print_engines_footer(struct engines *engines, double t,
        return lines;
 }
 
+static int class_cmp(const void *_a, const void *_b)
+{
+       const struct engine_class *a = _a;
+       const struct engine_class *b = _b;
+
+       return a->class - b->class;
+}
+
+static void init_engine_classes(struct engines *engines)
+{
+       struct engine_class *classes;
+       unsigned int i, num;
+       int max = -1;
+
+       for (i = 0; i < engines->num_engines; i++) {
+               struct engine *engine = engine_ptr(engines, i);
+
+               if ((int)engine->class > max)
+                       max = engine->class;
+       }
+       assert(max >= 0);
+
+       num = max + 1;
+
+       classes = calloc(num, sizeof(*classes));
+       assert(classes);
+

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1268

Quoted 10 lines
tools/intel_gpu_top.c +10 -0
+       for (i = 0; i < engines->num_engines; i++) {
+               struct engine *engine = engine_ptr(engines, i);
+
+               classes[engine->class].num_engines++;
+       }
+
+       for (i = 0; i < num; i++) {
+               classes[i].class = i;
+               classes[i].name = class_display_name(i);
+       }

Do you want to remove empty classes at this point?

Quoted 7 lines
tools/intel_gpu_top.c +7 -0
+
+       qsort(classes, num, sizeof(*classes), class_cmp);
+
+       engines->num_classes = num;
+       engines->class = classes;
+}
+

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1285

Quoted 10 lines
tools/intel_gpu_top.c +10 -0
+static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
+{
+       dst->prev += src->prev;
+       dst->cur += src->cur;
+}
+
+static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
+{
+       val->prev /= n;
+       val->cur /= n;

I was expecting just the delta to be normalized. This works as well.

Quoted 68 lines
tools/intel_gpu_top.c +68 -0
+}
+
+static struct engines *init_classes(struct engines *engines)
+{
+       struct engines *classes;
+       unsigned int i, j;
+
+       init_engine_classes(engines);
+
+       classes = calloc(1, sizeof(struct engines) +
+                           engines->num_classes * sizeof(struct engine));
+       assert(classes);
+
+       classes->num_engines = engines->num_classes;
+       classes->num_classes = engines->num_classes;
+       classes->class = engines->class;
+
+       for (i = 0; i < engines->num_classes; i++) {
+               struct engine *engine = engine_ptr(classes, i);
+
+               engine->class = i;
+               engine->instance = -1;
+
+               if (!engines->class[i].num_engines)
+                       continue;
+
+               engine->display_name = strdup(class_display_name(i));
+               assert(engine->display_name);
+               engine->short_name = strdup(class_short_name(i));
+               assert(engine->short_name);
+
+               for (j = 0; j < engines->num_engines; j++) {
+                       struct engine *e = engine_ptr(engines, j);
+
+                       if (e->class == i) {
+                               engine->num_counters = e->num_counters;
+                               engine->busy = e->busy;
+                               engine->sema = e->sema;
+                               engine->wait = e->wait;
+                       }
+               }
+       }
+
+       return classes;
+}
+
+static struct engines *
+update_classes(struct engines *classes, struct engines *engines)
+{
+       unsigned int i, j;
+
+       if (!classes)
+               classes = init_classes(engines);
+
+       for (i = 0; i < classes->num_engines; i++) {
+               unsigned int num_engines = classes->class[i].num_engines;
+               struct engine *engine = engine_ptr(classes, i);
+
+               if (!num_engines)
+                       continue;
+
+               memset(&engine->busy.val, 0, sizeof(engine->busy.val));
+               memset(&engine->sema.val, 0, sizeof(engine->sema.val));
+               memset(&engine->wait.val, 0, sizeof(engine->wait.val));
+
+               for (j = 0; j < engines->num_engines; j++) {
+                       struct engine *e = engine_ptr(engines, j);
+

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1363

Quoted 10 lines
tools/intel_gpu_top.c +10 -0
+                       if (e->class == i) {
+                               __pmu_sum(&engine->busy.val, &e->busy.val);
+                               __pmu_sum(&engine->sema.val, &e->sema.val);
+                               __pmu_sum(&engine->wait.val, &e->wait.val);
+                       }
+               }
+
+               __pmu_normalize(&engine->busy.val, num_engines);
+               __pmu_normalize(&engine->sema.val, num_engines);
+               __pmu_normalize(&engine->wait.val, num_engines);

Ok. So you wrap the normal engines with class_view, where each engine in that class_view is an average of all engines within it.

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1376

Quoted 13 lines
tools/intel_gpu_top.c +13 -0
+       }
+
+       return classes;
+}
+
+static int
+print_engines(struct engines *engines, double t, int lines, int w, int h)
+{
+       static struct engines *classes;
+       struct engines *show;
+
+       if (class_view)
+               classes = show = update_classes(classes, engines);

Something is not right here. Oh static, nvm.

Quoted 69 lines
tools/intel_gpu_top.c +18 -12
+       else
+               show = engines;
+
+       lines = print_engines_header(show, t, lines, w,  h);
+
+       for (unsigned int i = 0; i < show->num_engines && lines < h; i++)
+               lines = print_engine(show, i, t, lines, w, h);
+
+       lines = print_engines_footer(show, t, lines, w, h);
+
+       return lines;
+}
+
 static bool stop_top;
 
 static void sigint_handler(int  sig)
@@ -1292,6 +1465,9 @@ static void process_stdin(unsigned int timeout_us)
                case 'q':
                        stop_top = true;
                        break;
+               case '1':
+                       class_view ^= true;
+                       break;
                };
        }
 }
@@ -1302,7 +1478,6 @@ int main(int argc, char **argv)
        int con_w = -1, con_h = -1;
        char *output_path = NULL;
        struct engines *engines;
-       unsigned int i;
        int ret = 0, ch;
        bool list_device = false;
        char *pmu_device, *opt_device = NULL;
@@ -1366,6 +1541,7 @@ int main(int argc, char **argv)
        case INTERACTIVE:
                pops = &term_pops;
                interactive_stdin();
+               class_view = true;
                break;
        case STDOUT:
                pops = &stdout_pops;
@@ -1462,17 +1638,7 @@ int main(int argc, char **argv)
 
                        lines = print_imc(engines, t, lines, con_w, con_h);
 
-                       lines = print_engines_header(engines, t, lines, con_w,
-                                                    con_h);
-
-                       for (i = 0;
-                            i < engines->num_engines && lines < con_h;
-                            i++)
-                               lines = print_engine(engines, i, t, lines,
-                                                    con_w, con_h);
-
-                       lines = print_engines_footer(engines, t, lines, con_w,
-                                                    con_h);
+                       lines = print_engines(engines, t, lines, con_w, con_h);
                }
 
                if (stop_top)
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Reviewed-by
#3 lore raw

Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class

Quoting Chris Wilson (2020-12-16 15:51:59)

Quoted 11 lines

Quoting Tvrtko Ursulin (2020-12-16 15:28:09)

Quoted 10 lines

From: Tvrtko Ursulin <[email protected]>

Similarly to how top(1) handles SMP, we can default to showing engines of a same class as a single bar graph entry.

To achieve this a little bit of hackery is employed. PMU sampling is left as is and only at the presentation layer we create a fake set of engines, one for each class, summing and normalizing the load respectively.

Where were my manners?

-Chris
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#4 lore raw

Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class

In reply to Chris Wilson
Quoted 108 lines · Chris Wilson

Quoting Tvrtko Ursulin (2020-12-16 15:28:09)

Quoted 107 lines

From: Tvrtko Ursulin <[email protected]>

Similarly to how top(1) handles SMP, we can default to showing engines of a same class as a single bar graph entry.

To achieve this a little bit of hackery is employed. PMU sampling is left as is and only at the presentation layer we create a fake set of engines, one for each class, summing and normalizing the load respectively.

---
  man/intel_gpu_top.rst |   1 +
  tools/intel_gpu_top.c | 192 +++++++++++++++++++++++++++++++++++++++---
  2 files changed, 180 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +1 -0
index 2e0c3a05acc1..35ab10da9bb4 100644
@@ -54,6 +54,7 @@ RUNTIME CONTROL
  Supported keys:
 
      'q'    Exit from the tool.
+    '1'    Toggle between aggregated engine class and physical engine mode.
 
  DEVICE SELECTION
  ================
tools/intel_gpu_top.c +47 -1
index 68911940f1d0..8c4280aa19b9 100644
@@ -76,8 +76,16 @@ struct engine {
         struct pmu_counter sema;
  };
 
+struct engine_class {
+       unsigned int class;
+       const char *name;
+       unsigned int num_engines;
+};
+
  struct engines {
         unsigned int num_engines;
+       unsigned int num_classes;
+       struct engine_class *class;
         unsigned int num_counters;
         DIR *root;
         int fd;
@@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines, int con_w, int con_h)
         return lines;
  }
 
+static bool class_view;
+
  static int
  print_engines_header(struct engines *engines, double t,
                      int lines, int con_w, int con_h)
@@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
                 pops->open_struct("engines");
 
                 if (output_mode == INTERACTIVE) {
-                       const char *a = "          ENGINE      BUSY ";
                         const char *b = " MI_SEMA MI_WAIT";
+                       const char *a;
+
+                       if (class_view)
+                               a = "         ENGINES     BUSY  ";
+                       else
+                               a = "          ENGINE     BUSY  ";
 
                         printf("\033[7m%s%*s%s\033[0m\n",
                                a, (int)(con_w - 1 - strlen(a) - strlen(b)),
@@ -1214,6 +1229,164 @@ print_engines_footer(struct engines *engines, double t,
         return lines;
  }
 
+static int class_cmp(const void *_a, const void *_b)
+{
+       const struct engine_class *a = _a;
+       const struct engine_class *b = _b;
+
+       return a->class - b->class;
+}
+
+static void init_engine_classes(struct engines *engines)
+{
+       struct engine_class *classes;
+       unsigned int i, num;
+       int max = -1;
+
+       for (i = 0; i < engines->num_engines; i++) {
+               struct engine *engine = engine_ptr(engines, i);
+
+               if ((int)engine->class > max)
+                       max = engine->class;
+       }
+       assert(max >= 0);
+
+       num = max + 1;
+
+       classes = calloc(num, sizeof(*classes));
+       assert(classes);
+
+       for (i = 0; i < engines->num_engines; i++) {
+               struct engine *engine = engine_ptr(engines, i);
+
+               classes[engine->class].num_engines++;
Quoted 8 lines

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1268

Quoted 6 lines
tools/intel_gpu_top.c +6 -0
+       }
+
+       for (i = 0; i < num; i++) {
+               classes[i].class = i;
+               classes[i].name = class_display_name(i);
+       }

Do you want to remove empty classes at this point?

I need this array 1:1 with class ids so no. I didn't find yet that "empty" entries would cause a problem anywhere in the code. Hm actually there wouldn't be any empty classes, since class generation is driven of discovered engines.

I need to sprinkle some more asserts and comments around.

Quoted 12 lines
Quoted 12 lines
tools/intel_gpu_top.c +11 -0
+
+       qsort(classes, num, sizeof(*classes), class_cmp);
+
+       engines->num_classes = num;
+       engines->class = classes;
+}
+
+static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
+{
+       dst->prev += src->prev;
+       dst->cur += src->cur;
Quoted 8 lines

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1285

Quoted 6 lines
tools/intel_gpu_top.c +6 -0
+}
+
+static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
+{
+       val->prev /= n;
+       val->cur /= n;

I was expecting just the delta to be normalized. This works as well.

Yeah, this allows basically no changes to existing code.

Maybe a running average algorithm would be better to not overflow the u64 but I haven't bothered calculating if that is a theoretical possibility or not.

Quoted 74 lines
Quoted 74 lines
tools/intel_gpu_top.c +73 -0
+}
+
+static struct engines *init_classes(struct engines *engines)
+{
+       struct engines *classes;
+       unsigned int i, j;
+
+       init_engine_classes(engines);
+
+       classes = calloc(1, sizeof(struct engines) +
+                           engines->num_classes * sizeof(struct engine));
+       assert(classes);
+
+       classes->num_engines = engines->num_classes;
+       classes->num_classes = engines->num_classes;
+       classes->class = engines->class;
+
+       for (i = 0; i < engines->num_classes; i++) {
+               struct engine *engine = engine_ptr(classes, i);
+
+               engine->class = i;
+               engine->instance = -1;
+
+               if (!engines->class[i].num_engines)
+                       continue;
+
+               engine->display_name = strdup(class_display_name(i));
+               assert(engine->display_name);
+               engine->short_name = strdup(class_short_name(i));
+               assert(engine->short_name);
+
+               for (j = 0; j < engines->num_engines; j++) {
+                       struct engine *e = engine_ptr(engines, j);
+
+                       if (e->class == i) {
+                               engine->num_counters = e->num_counters;
+                               engine->busy = e->busy;
+                               engine->sema = e->sema;
+                               engine->wait = e->wait;
+                       }
+               }
+       }
+
+       return classes;
+}
+
+static struct engines *
+update_classes(struct engines *classes, struct engines *engines)
+{
+       unsigned int i, j;
+
+       if (!classes)
+               classes = init_classes(engines);
+
+       for (i = 0; i < classes->num_engines; i++) {
+               unsigned int num_engines = classes->class[i].num_engines;
+               struct engine *engine = engine_ptr(classes, i);
+
+               if (!num_engines)
+                       continue;
+
+               memset(&engine->busy.val, 0, sizeof(engine->busy.val));
+               memset(&engine->sema.val, 0, sizeof(engine->sema.val));
+               memset(&engine->wait.val, 0, sizeof(engine->wait.val));
+
+               for (j = 0; j < engines->num_engines; j++) {
+                       struct engine *e = engine_ptr(engines, j);
+
+                       if (e->class == i) {
+                               __pmu_sum(&engine->busy.val, &e->busy.val);
+                               __pmu_sum(&engine->sema.val, &e->sema.val);
+                               __pmu_sum(&engine->wait.val, &e->wait.val);
+                       }
Quoted 8 lines

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1363

Quoted 5 lines
tools/intel_gpu_top.c +5 -0
+               }
+
+               __pmu_normalize(&engine->busy.val, num_engines);
+               __pmu_normalize(&engine->sema.val, num_engines);
+               __pmu_normalize(&engine->wait.val, num_engines);

Ok. So you wrap the normal engines with class_view, where each engine in that class_view is an average of all engines within it.

Yes, and then just pass this wrapped/aggregated struct engines * to the existing code.

Quoted 7 lines
Quoted 7 lines
tools/intel_gpu_top.c +7 -0
+       }
+
+       return classes;
+}
+
+static int
+print_engines(struct engines *engines, double t, int lines, int w, int h)
Quoted 8 lines

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1376

Quoted 6 lines
tools/intel_gpu_top.c +6 -0
+{
+       static struct engines *classes;
+       struct engines *show;
+
+       if (class_view)
+               classes = show = update_classes(classes, engines);

Something is not right here. Oh static, nvm.

Too hacky? Maybe "show = classes = update_classes()"would read better.

Regards,

Tvrtko
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#5 lore raw

Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class

Quoting Tvrtko Ursulin (2020-12-16 16:01:30)

Quoted 14 lines · Chris Wilson
Quoted 11 lines

Quoting Tvrtko Ursulin (2020-12-16 15:28:09)

tools/intel_gpu_top.c print_engines_footer(struct engines *engines, double t, · line 1376

Quoted 8 lines
tools/intel_gpu_top.c +8 -0
+static int
+print_engines(struct engines *engines, double t, int lines, int w, int h)
+{
+       static struct engines *classes;
+       struct engines *show;
+
+       if (class_view)
+               classes = show = update_classes(classes, engines);

Something is not right here. Oh static, nvm.

Quoted 1 line

Too hacky? Maybe "show = classes = update_classes()"would read better.

show = update_classes(engines);

with update_classes doing the if (once) classes = init_classes(engines) ? -Chris
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#6 lore raw

PATCH v2 2/2 intel_gpu_top: Aggregate engine busyness per class

From: Tvrtko Ursulin <[email protected]>

Similarly to how top(1) handles SMP, we can default to showing engines of a same class as a single bar graph entry.

To achieve this a little bit of hackery is employed. PMU sampling is left as is and only at the presentation layer we create a fake set of engines, one for each class, summing and normalizing the load respectively.

v2:
* Fix building the aggregated engines.
* Tidy static variable handling.

---
 man/intel_gpu_top.rst |   1 +
 tools/intel_gpu_top.c | 208 +++++++++++++++++++++++++++++++++++++++---
 2 files changed, 196 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +1 -0
index 2e0c3a05acc1..35ab10da9bb4 100644
@@ -54,6 +54,7 @@ RUNTIME CONTROL
 Supported keys:
 
     'q'    Exit from the tool.
+    '1'    Toggle between aggregated engine class and physical engine mode.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +195 -13

259 lines not on this page · raw message

Signature · 6 lines
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#7 lore raw
In reply to Tvrtko Ursulin

Quoting Tvrtko Ursulin (2020-12-16 15:28:08)

Quoted 74 lines

From: Tvrtko Ursulin <[email protected]>

Analoguous to top(1) we can enable the user to exit from the tool by pressing 'q' on the console.

---
 man/intel_gpu_top.rst |  6 ++++
 tools/intel_gpu_top.c | 77 +++++++++++++++++++++++++++++++++++--------
 2 files changed, 70 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +6 -0
index 5552e9699d26..2e0c3a05acc1 100644
@@ -48,6 +48,12 @@ OPTIONS
 -d
     Select a specific GPU using supported filter.
 
+RUNTIME CONTROL
+===============
+
+Supported keys:
+
+    'q'    Exit from the tool.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +14 -12
index dbd353673e55..68911940f1d0 100644
@@ -23,24 +23,26 @@
 
 #include "igt_device_scan.h"
 
-#include <stdio.h>
-#include <sys/types.h>
-#include <dirent.h>
-#include <stdint.h>
 #include <assert.h>
-#include <string.h>
 #include <ctype.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <sys/stat.h>
+#include <dirent.h>
+#include <errno.h>
 #include <fcntl.h>
 #include <inttypes.h>
-#include <sys/ioctl.h>
-#include <errno.h>
-#include <math.h>
-#include <locale.h>
 #include <limits.h>
+#include <locale.h>
+#include <math.h>
+#include <poll.h>
 #include <signal.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <termios.h>
 
 #include "igt_perf.h"
 
@@ -1246,6 +1248,54 @@ static char *tr_pmu_name(struct igt_device_card *card)
        return device;
 }

tools/intel_gpu_top.c static char *tr_pmu_name(struct igt_device_card *card) · line 1259

Quoted 10 lines
tools/intel_gpu_top.c +9 -0
 
+static void interactive_stdin(void)
+{
+       struct termios termios = { };
+       int ret;
+
+       ret = fcntl(0, F_GETFL, NULL);
+       ret |= O_NONBLOCK;
+       ret = fcntl(0, F_SETFL, ret);
+       assert(ret == 0);

I always have to double check that O_NONBLOCK is in F_SETFL and not F_SETFD.

Quoted 8 lines
tools/intel_gpu_top.c +8 -0
+
+       ret = tcgetattr(0, &termios);
+       assert(ret == 0);
+
+       termios.c_lflag &= ~ICANON;
+       termios.c_cc[VMIN] = 1;
+       termios.c_cc[VTIME] = 0; /* Deciseconds only - we'll use poll. */
+

tools/intel_gpu_top.c static char *tr_pmu_name(struct igt_device_card *card) · line 1277

Quoted 10 lines
tools/intel_gpu_top.c +10 -0
+       ret = tcsetattr(0, TCSAFLUSH, &termios);
+       assert(ret == 0);
+}
+
+static void process_stdin(unsigned int timeout_us)
+{
+       struct pollfd p = { .fd = 0, .events = POLLIN };
+       int ret;
+
+       ret = poll(&p, 1, timeout_us / 1000);

Replacing the usleep in the mainloop.

Hmm. Won't this have a problem if this run as a daemon (with stdin closed)?

tools/intel_gpu_top.c static char *tr_pmu_name(struct igt_device_card *card) · line 1289

Quoted 12 lines
tools/intel_gpu_top.c +12 -0
+       if (ret <= 0) {
+               if (ret < 0)
+                       stop_top = true;
+               return;
+       }
+
+       for (;;) {
+               char c;
+
+               ret = read(0, &c, 1);
+               if (ret <= 0)
+                       break;

O_NONBLOCK on 0.

So on each mainloop, we check for a key press, consume all that are in the buffer, then return to the mainloop.

Quoted 13 lines
tools/intel_gpu_top.c +9 -0
+
+               switch (c) {
+               case 'q':
+                       stop_top = true;
+                       break;
+               };
+       }
+}
+
 int main(int argc, char **argv)
 {
        unsigned int period_us = DEFAULT_PERIOD_MS * 1000;

tools/intel_gpu_top.c int main(int argc, char **argv) · line 1366

Quoted 2 lines
tools/intel_gpu_top.c +0 -0
@@ -1315,6 +1365,7 @@ int main(int argc, char **argv)
        switch (output_mode) {
        case INTERACTIVE:

INTERACTIVE is the default mode when run in a terminal.

tools/intel_gpu_top.c int main(int argc, char **argv) · line 1481

Quoted 11 lines
tools/intel_gpu_top.c +2 -1
                pops = &term_pops;
+               interactive_stdin();
                break;
        case STDOUT:
                pops = &stdout_pops;
@@ -1427,7 +1478,7 @@ int main(int argc, char **argv)
                if (stop_top)
                        break;
 
-               usleep(period_us);
+               process_stdin(period_us);

Just the question about what happens if run with 0 closed...

if (!process_stdin(period_us))

	usleep(period_us);

?

Quoted 11 lines
tools/intel_gpu_top.c +0 -0
        }
 
        free(codename);
Signature · 6 lines
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#8 lore raw

PATCH v2 1/2 intel_gpu_top: Support exiting the tool by pressing 'q'

From: Tvrtko Ursulin <[email protected]>

Analoguous to top(1) we can enable the user to exit from the tool by pressing 'q' on the console.

v2:
* Fix sleep period with closed stdin. (Chris)

---
 man/intel_gpu_top.rst |  6 ++++
 tools/intel_gpu_top.c | 80 ++++++++++++++++++++++++++++++++++++-------
 2 files changed, 73 insertions(+), 13 deletions(-)
man/intel_gpu_top.rst +6 -0
index 5552e9699d26..2e0c3a05acc1 100644
@@ -48,6 +48,12 @@ OPTIONS
 -d
     Select a specific GPU using supported filter.
 
+RUNTIME CONTROL
+===============
+
+Supported keys:
+
+    'q'    Exit from the tool.
 
 DEVICE SELECTION
 ================
tools/intel_gpu_top.c +67 -13

110 lines not on this page · raw message

Signature · 6 lines
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Reviewed-by on v2 1/2
#9 lore raw

Quoting Tvrtko Ursulin (2020-12-16 15:54:20)

Quoted 9 lines

From: Tvrtko Ursulin <[email protected]>

Analoguous to top(1) we can enable the user to exit from the tool by pressing 'q' on the console.

v2:
* Fix sleep period with closed stdin. (Chris)

-Chris
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#10 lore raw

Quoting Chris Wilson (2020-12-16 15:57:53)

Quoted 11 lines

Quoting Tvrtko Ursulin (2020-12-16 15:54:20)

Quoted 9 lines

From: Tvrtko Ursulin <[email protected]>

Analoguous to top(1) we can enable the user to exit from the tool by pressing 'q' on the console.

v2:
* Fix sleep period with closed stdin. (Chris)

I've only used this once, and I already miss it.
-Chris
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#11 lore raw

[igt-dev] ✓ Fi.CI.BAT: success for series starting with [v2,i-g-t,1/2] intel_gpu_top: Support exiting the tool by pressing 'q' (rev3)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: series starting with [v2,i-g-t,1/2] intel_gpu_top: Support exiting the tool by pressing 'q' (rev3)
URL : https://patchwork.freedesktop.org/series/85009/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9493 -> IGTPW_5300
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html

Known issues
------------

Here are the changes found in IGTPW_5300 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-tgl-y/igt@debugfs_test@read_all_entries.html

* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: NOTRUN -> [DMESG-FAIL][3] ([i915#1759])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-tgl-y/igt@i915_selftest@live@gt_pm.html

* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#2750])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#2029] / [i915#2722])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-bdw-5557u/igt@[email protected]

#### Possible fixes ####

* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][7] ([i915#2411] / [i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/fi-tgl-y/igt@[email protected]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-tgl-y/igt@[email protected]

* igt@vgem_basic@setversion:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/fi-tgl-y/igt@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-tgl-y/igt@[email protected]

#### Warnings ####

* igt@i915_selftest@live@gt_lrc:
- fi-tgl-y: [INCOMPLETE][11] -> [DMESG-FAIL][12] ([i915#2373])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html

[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2750]: https://gitlab.freedesktop.org/drm/intel/issues/2750
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402

Participating hosts (42 -> 38)
------------------------------

Missing (4): fi-dg1-1 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u

Build changes
-------------

* CI: CI-20190529 -> None
* IGT: IGT_5905 -> IGTPW_5300

CI-20190529: 20190529
CI_DRM_9493: 27c8bb9a6204aea5be2a779ca1f36482149de9bf @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5300: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html
IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html

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#12 lore raw

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [v2,i-g-t,1/2] intel_gpu_top: Support exiting the tool by pressing 'q' (rev3)

In reply to Tvrtko Ursulin
== Series Details ==

== Series Details ==

Series: series starting with [v2,i-g-t,1/2] intel_gpu_top: Support exiting the tool by pressing 'q' (rev3)
URL : https://patchwork.freedesktop.org/series/85009/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9493_full -> IGTPW_5300_full
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html

New tests
---------

New tests have been introduced between CI_DRM_9493_full and IGTPW_5300_full:

### New IGT tests (4) ###

* igt@kms_atomic_transition@modeset-transition:
- Statuses :
- Exec time: [None] s

* igt@kms_atomic_transition@modeset-transition-fencing:
- Statuses :
- Exec time: [None] s

* igt@kms_atomic_transition@modeset-transition-nonblocking:
- Statuses :
- Exec time: [None] s

* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- Statuses :
- Exec time: [None] s

Known issues
------------

Here are the changes found in IGTPW_5300_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_fence@basic-wait@bcs0:
- shard-glk: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-glk1/igt@gem_exec_fence@[email protected]

* igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][2] ([fdo#112283])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb1/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][3] ([fdo#112283])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb3/igt@[email protected]

* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-kbl: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1699]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl7/igt@gem_userptr_blits@[email protected]

* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb6/igt@[email protected]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb2/igt@[email protected]

* igt@i915_suspend@sysfs-reader:
- shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-tglb1/igt@[email protected]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb3/igt@[email protected]
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1602] / [i915#2635])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-apl3/igt@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl4/igt@[email protected]
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1602] / [i915#2635])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-glk8/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-glk8/igt@[email protected]
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([i915#2637])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw6/igt@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw6/igt@[email protected]
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#1602])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl1/igt@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl3/igt@[email protected]
- shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1602])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb5/igt@[email protected]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb4/igt@[email protected]

* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#111615]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb5/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#110723])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb2/igt@[email protected]

* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-hsw: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw4/igt@[email protected]

* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl2/igt@[email protected]

* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][23] -> [FAIL][24] ([i915#96])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw1/igt@[email protected]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw6/igt@[email protected]

* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#109274]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb1/igt@[email protected]

* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-tglb: [PASS][26] -> [FAIL][27] ([i915#2122])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-tglb5/igt@kms_flip@[email protected]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb5/igt@kms_flip@[email protected]

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#2672])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111825]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb6/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109280])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb8/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271]) +14 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

* igt@kms_frontbuffer_tracking@psr-farfromfence:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271]) +48 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl4/igt@[email protected]

* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#1187])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb8/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][34] ([i915#1187])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb7/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][35] ([fdo#108145] / [i915#265])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl2/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-hsw: NOTRUN -> [SKIP][36] ([fdo#109271]) +14 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw1/igt@[email protected]

#### Possible fixes ####

* {igt@gem_exec_balancer@fairslice}:
- shard-tglb: [FAIL][37] ([i915#2802]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-tglb7/igt@[email protected]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb2/igt@[email protected]
- shard-iclb: [FAIL][39] ([i915#2802]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb2/igt@[email protected]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb6/igt@[email protected]

* igt@gen9_exec_parse@allowed-all:
- shard-kbl: [DMESG-WARN][41] ([i915#1436] / [i915#716]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl1/igt@[email protected]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl1/igt@[email protected]

* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][43] ([i915#2635]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-apl2/igt@[email protected]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl2/igt@[email protected]
- shard-iclb: [DMESG-WARN][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb6/igt@[email protected]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb6/igt@[email protected]
- shard-glk: [DMESG-WARN][47] ([i915#2635]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-glk2/igt@[email protected]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-glk7/igt@[email protected]
- shard-hsw: [DMESG-WARN][49] ([i915#2637]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw1/igt@[email protected]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw2/igt@[email protected]
- shard-kbl: [DMESG-WARN][51] -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl3/igt@[email protected]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl6/igt@[email protected]
- shard-tglb: [INCOMPLETE][53] ([i915#1436] / [i915#1798] / [i915#1982] / [i915#456]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-tglb2/igt@[email protected]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb2/igt@[email protected]

* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][55] ([i915#96]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw1/igt@[email protected]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw2/igt@[email protected]

* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [FAIL][57] ([i915#79]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-apl2/igt@kms_flip@[email protected]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl7/igt@kms_flip@[email protected]

* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb8/igt@kms_psr@psr2_suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb2/igt@kms_psr@psr2_suspend.html

* igt@kms_vblank@pipe-b-query-forked-busy-hang:
- shard-hsw: [INCOMPLETE][61] -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw2/igt@[email protected]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw4/igt@[email protected]

* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- shard-hsw: [SKIP][63] ([fdo#109271]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw8/igt@[email protected]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw1/igt@[email protected]

#### Warnings ####

* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][65] ([i915#1804] / [i915#2684]) -> [WARN][66] ([i915#2684])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb4/igt@[email protected]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb5/igt@[email protected]

* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: [SKIP][67] ([i915#579]) -> [SKIP][68] ([fdo#109293] / [fdo#109506])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb8/igt@[email protected]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb6/igt@[email protected]
- shard-tglb: [SKIP][69] ([i915#579]) -> [SKIP][70] ([fdo#109506] / [i915#2411])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-tglb5/igt@[email protected]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-tglb2/igt@[email protected]

* igt@runner@aborted:
- shard-hsw: [FAIL][71] ([i915#2295] / [i915#483]) -> [FAIL][72] ([i915#2295])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-hsw1/igt@[email protected]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-hsw6/igt@[email protected]
- shard-kbl: ([FAIL][73], [FAIL][74], [FAIL][75]) ([fdo#109271] / [i915#1436] / [i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [i915#716]) -> ([FAIL][76], [FAIL][77]) ([i915#2295] / [i915#2722] / [i915#483])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl1/igt@[email protected]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl3/igt@[email protected]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-kbl2/igt@[email protected]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl3/igt@[email protected]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-kbl6/igt@[email protected]
- shard-iclb: ([FAIL][78], [FAIL][79]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724] / [i915#483]) -> ([FAIL][80], [FAIL][81]) ([i915#2295] / [i915#2722] / [i915#2724])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb6/igt@[email protected]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-iclb8/igt@[email protected]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb4/igt@[email protected]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-iclb2/igt@[email protected]
- shard-apl: ([FAIL][82], [FAIL][83]) ([i915#1814] / [i915#2295] / [i915#2722]) -> ([FAIL][84], [FAIL][85]) ([i915#2295] / [i915#2722])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-apl6/igt@[email protected]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-apl2/igt@[email protected]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl4/igt@[email protected]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-apl1/igt@[email protected]
- shard-glk: ([FAIL][86], [FAIL][87]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][88], [FAIL][89]) ([i915#2295] / [i915#2722] / [k.org#202321])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-glk2/igt@[email protected]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9493/shard-glk7/igt@[email protected]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-glk8/igt@[email protected]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/shard-glk2/igt@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699
[i915#1798]: https://gitlab.freedesktop.org/drm/intel/issues/1798
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
[i915#2637]: https://gitlab.freedesktop.org/drm/intel/issues/2637
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2802]: https://gitlab.freedesktop.org/drm/intel/issues/2802
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321

Participating hosts (10 -> 8)
------------------------------

Missing (2): pig-skl-6260u pig-glk-j5005

Build changes
-------------

* CI: CI-20190529 -> None
* IGT: IGT_5905 -> IGTPW_5300
* Piglit: piglit_4509 -> None

CI-20190529: 20190529
CI_DRM_9493: 27c8bb9a6204aea5be2a779ca1f36482149de9bf @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5300: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html
IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5300/index.html

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