xhci: tegra: Delay for disabling LFPS detector

PATCH Superseded JC Kuo 3 participants 5 messages Dec 18, 2020 – Jan 8, 2021

Subsystems (3)

USB Tegra architecture support USB xHCI driver

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JC Kuo

author

2020-12-18 16:44 UTC #0 lore raw

PATCH 1/1 xhci: tegra: Delay for disabling LFPS detector

Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware.

[   16.099363] tegra-xusb 70090000.usb: entering ELPG
[   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
[   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
[   16.120789] tegra-xusb 70090000.usb: entering ELPG failed

Signed-off-by JC Kuo <[email protected]>

---
 drivers/usb/host/xhci-tegra.c | 6 ++++++
 1 file changed, 6 insertions(+)

drivers/usb/host/xhci-tegra.c +6 -0

index 934be1686352..20cdc11f7dc6 100644
@@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 								     enable);
 			if (err < 0)
 				break;
+
+			/*
+			 * wait 500us for LFPS detector to be disabled before sending ACK
+			 */
+			if (!enable)
+				usleep_range(500, 1000);
 		}
 
 		if (err < 0) {

Signature · 1 line

2.25.1

Greg KH

maintainer

2020-12-18 16:52 UTC #1 lore raw

Quoted 19 lines · JC Kuo

Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware.
[   16.099363] tegra-xusb 70090000.usb: entering ELPG
[   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
[   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
[   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
Signed-off-by JC Kuo <[email protected]>
---
 drivers/usb/host/xhci-tegra.c | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/usb/host/xhci-tegra.c +0 -0
index 934be1686352..20cdc11f7dc6 100644

drivers/usb/host/xhci-tegra.c static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, · line 631

Quoted 9 lines

drivers/usb/host/xhci-tegra.c +6 -0

@@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 								     enable);
 			if (err < 0)
 				break;
+
+			/*
+			 * wait 500us for LFPS detector to be disabled before sending ACK
+			 */
+			if (!enable)
+				usleep_range(500, 1000);

Where does the magic 500us come from? How can we "know" this is long enough?

thanks,

greg k-h

JC Kuo

author

2021-01-06 06:06 UTC #2 lore raw

Quoted 24 lines · Greg KH

Quoted 23 lines · JC Kuo
Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware.
[   16.099363] tegra-xusb 70090000.usb: entering ELPG
[   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
[   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
[   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
Signed-off-by JC Kuo <[email protected]>
---
 drivers/usb/host/xhci-tegra.c | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/usb/host/xhci-tegra.c +1 -0
index 934be1686352..20cdc11f7dc6 100644
@@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 								     enable);
 			if (err < 0)
 				break;
+

Quoted 8 lines

drivers/usb/host/xhci-tegra.c static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, · line 631
Quoted 5 lines
drivers/usb/host/xhci-tegra.c +5 -0
+			/*
+			 * wait 500us for LFPS detector to be disabled before sending ACK
+			 */
+			if (!enable)
+				usleep_range(500, 1000);
Where does the magic 500us come from? How can we "know" this is long enough?

Hi Greg,
The register write passes through a few flop stages of 32KHz clock domain. Our ASIC designer reviewed RTL and suggests 500us delay. It has also been verified thoroughly.

Thanks,
JC

Quoted 5 lines

thanks,
greg k-h

Mathias Nyman

2021-01-07 09:53 UTC #3 lore raw

Quoted 34 lines · JC Kuo

Quoted 24 lines · Greg KH
Quoted 23 lines · JC Kuo
Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware.
[   16.099363] tegra-xusb 70090000.usb: entering ELPG
[   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
[   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
[   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
Signed-off-by JC Kuo <[email protected]>
---
 drivers/usb/host/xhci-tegra.c | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/usb/host/xhci-tegra.c +1 -0
index 934be1686352..20cdc11f7dc6 100644
@@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 								     enable);
 			if (err < 0)
 				break;
+
Quoted 8 lines
drivers/usb/host/xhci-tegra.c static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, · line 631
Quoted 5 lines
drivers/usb/host/xhci-tegra.c +5 -0
+			/*
+			 * wait 500us for LFPS detector to be disabled before sending ACK
+			 */
+			if (!enable)
+				usleep_range(500, 1000);
Where does the magic 500us come from? How can we "know" this is long enough?

Quoted 5 lines

Hi Greg,
The register write passes through a few flop stages of 32KHz clock domain. Our ASIC designer reviewed RTL and suggests 500us delay. It has also been verified thoroughly.

Could you add that comment to the commit message? I can pick it up then. Should this go to stable as well?

Thanks
-Mathias

JC Kuo

author

2021-01-08 06:33 UTC #4 lore raw

Quoted 35 lines · Mathias Nyman

Quoted 34 lines · JC Kuo
Quoted 32 lines · Greg KH
Quoted 19 lines · JC Kuo
Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware.
[   16.099363] tegra-xusb 70090000.usb: entering ELPG
[   16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203
[   16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16
[   16.120789] tegra-xusb 70090000.usb: entering ELPG failed
Signed-off-by JC Kuo <[email protected]>
---
 drivers/usb/host/xhci-tegra.c | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/usb/host/xhci-tegra.c +0 -0
index 934be1686352..20cdc11f7dc6 100644
drivers/usb/host/xhci-tegra.c static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, · line 631
Quoted 9 lines
drivers/usb/host/xhci-tegra.c +6 -0
@@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 								     enable);
 			if (err < 0)
 				break;
+
+			/*
+			 * wait 500us for LFPS detector to be disabled before sending ACK
+			 */
+			if (!enable)
+				usleep_range(500, 1000);
Where does the magic 500us come from? How can we "know" this is long enough?

Quoted 9 lines

Quoted 5 lines
Hi Greg,
The register write passes through a few flop stages of 32KHz clock domain. Our ASIC designer reviewed RTL and suggests 500us delay. It has also been verified thoroughly.
Could you add that comment to the commit message? I can pick it up then. Should this go to stable as well?

Hi Mathias,
Yes, I will send v2 with the information in commit message. Yes, this should go to stable as well.

Thanks,
JC

Quoted 3 lines

Thanks
-Mathias