eMMC inline encryption support
Subsystems (7)
Eric Biggers
maintainerv4 cover eMMC inline encryption support
Hello,
This patchset adds support for eMMC inline encryption, as specified by the upcoming version of the eMMC specification and as already implemented and used on many devices. Building on that, it then adds Qualcomm ICE support and wires it up for the Snapdragon 630 SoC.
Inline encryption hardware improves the performance of storage encryption and reduces power usage. See Documentation/block/inline-encryption.rst for more information about inline encryption and the blk-crypto framework (upstreamed in v5.8) which supports it. Most mobile devices already use UFS or eMMC inline encryption hardware; UFS support was already upstreamed in v5.9.
Patches 1-4 add support for the standard eMMC inline encryption.
However, as with UFS, host controller-specific patches are needed on top of the standard support. Therefore, patches 5-9 add Qualcomm ICE (Inline Crypto Engine) support and wire it up on the Snapdragon 630 SoC.
To test this I took advantage of the recently upstreamed support for the Snapdragon 630 SoC, plus work-in-progress patches from the SoMainline project (https://github.com/SoMainline/linux/tree/konrad/v5.10-rc3). In particular, I was able to run the fscrypt xfstests for ext4 and f2fs in a Debian chroot. Among other things, these tests verified that the correct ciphertext is written to disk (the same as software encryption).
It will also be possible to add support for Mediatek eMMC inline encryption hardware in mtk-sd, and it should be easier than the Qualcomm hardware since the Mediatek hardware follows the standard more closely. I.e., patches 1-4 should be almost enough for the Mediatek hardware. However, I don't have the hardware to do this yet.
This patchset is based on v5.11-rc2, and it can also be retrieved from tag "mmc-crypto-v4" of
https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git
Changed since v3:
- Added Acked-by and Reviewed-and-tested-by tags.
- Rebased onto v5.11-rc2.
Changed since v2:
- Improved comment for sdhci_msm_ice_wait_bist_status()
- Removed an unhelpful comment in union cqhci_crypto_cfg_entry.
- Fixed the commit message of "mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors".
- Added Reviewed-by's and Acked-by's.
Changed since v1:
- Only select QCOM_SCM if ARCH_QCOM. (Fixes a build break.)
- Split most of the cqhci_prep_task_desc() change into its own patch.
- Made sdhci_msm_ice_wait_bist_status() use readl_poll_timeout().
- Added a couple more comments.
- Added some Acked-by's.
Eric Biggers (9):
mmc: add basic support for inline encryption
mmc: cqhci: rename cqhci.c to cqhci-core.c
mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors
mmc: cqhci: add support for inline encryption
mmc: cqhci: add cqhci_host_ops::program_key
firmware: qcom_scm: update comment for ICE-related functions
dt-bindings: mmc: sdhci-msm: add ICE registers and clock
arm64: dts: qcom: sdm630: add ICE registers and clocks
mmc: sdhci-msm: add Inline Crypto Engine support
.../devicetree/bindings/mmc/sdhci-msm.txt | 3 +
arch/arm64/boot/dts/qcom/sdm630.dtsi | 10 +-
drivers/firmware/qcom_scm.c | 16 +-
drivers/mmc/core/Kconfig | 8 +
drivers/mmc/core/Makefile | 1 +
drivers/mmc/core/block.c | 3 +
drivers/mmc/core/core.c | 3 +
drivers/mmc/core/crypto.c | 54 ++++
drivers/mmc/core/crypto.h | 46 +++
drivers/mmc/core/host.c | 2 +
drivers/mmc/core/queue.c | 3 +
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/Makefile | 2 +
drivers/mmc/host/{cqhci.c => cqhci-core.c} | 69 ++++-
drivers/mmc/host/cqhci-crypto.c | 245 ++++++++++++++++
drivers/mmc/host/cqhci-crypto.h | 47 +++
drivers/mmc/host/cqhci.h | 84 +++++-
drivers/mmc/host/sdhci-msm.c | 276 +++++++++++++++++-
include/linux/mmc/core.h | 6 +
include/linux/mmc/host.h | 7 +
20 files changed, 861 insertions(+), 25 deletions(-)
create mode 100644 drivers/mmc/core/crypto.c
create mode 100644 drivers/mmc/core/crypto.h
rename drivers/mmc/host/{cqhci.c => cqhci-core.c} (94%)
create mode 100644 drivers/mmc/host/cqhci-crypto.c
create mode 100644 drivers/mmc/host/cqhci-crypto.hbase-commit: e71ba9452f0b5b2e8dc8aa5445198cd9214a6a62
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 1/9 mmc: add basic support for inline encryption
From: Eric Biggers <[email protected]>
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make mmc_core and mmc_block aware of inline encryption. Specifically:
- Add a capability flag MMC_CAP2_CRYPTO to struct mmc_host. Drivers will set this if the host and driver support inline encryption.
- Embed a blk_keyslot_manager in struct mmc_host. Drivers will initialize this if the host and driver support inline encryption. mmc_block registers this keyslot manager with the request_queue of any MMC card attached to the host. mmc_core destroys this keyslot manager when freeing the mmc_host.
- Make mmc_block copy the crypto keyslot and crypto data unit number from struct request to struct mmc_request, so that drivers will have access to them.
- If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state.
--- drivers/mmc/core/Kconfig | 8 ++++++ drivers/mmc/core/Makefile | 1 + drivers/mmc/core/block.c | 3 +++ drivers/mmc/core/core.c | 3 +++ drivers/mmc/core/crypto.c | 54 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/core/crypto.h | 46 +++++++++++++++++++++++++++++++++ drivers/mmc/core/host.c | 2 ++ drivers/mmc/core/queue.c | 3 +++ include/linux/mmc/core.h | 6 +++++ include/linux/mmc/host.h | 7 +++++ 10 files changed, 133 insertions(+) create mode 100644 drivers/mmc/core/crypto.c create mode 100644 drivers/mmc/core/crypto.h
drivers/mmc/core/Kconfig +8 -0
@@ -81,3 +81,11 @@ config MMC_TEST This driver is only of interest to those developing or testing a host driver. Most people should say N here. +config MMC_CRYPTO + bool "MMC Crypto Engine Support" + depends on BLK_INLINE_ENCRYPTION + help + Enable Crypto Engine Support in MMC. + Enabling this makes it possible for the kernel to use the crypto + capabilities of the MMC device (if present) to perform crypto + operations on data being transferred to/from the device.
drivers/mmc/core/Makefile +1 -0
@@ -18,3 +18,4 @@ obj-$(CONFIG_MMC_BLOCK) += mmc_block.o mmc_block-objs := block.o queue.o obj-$(CONFIG_MMC_TEST) += mmc_test.o obj-$(CONFIG_SDIO_UART) += sdio_uart.o +mmc_core-$(CONFIG_MMC_CRYPTO) += crypto.o
drivers/mmc/core/block.c +3 -0
@@ -51,6 +51,7 @@#include "block.h" #include "core.h" #include "card.h" +#include "crypto.h" #include "host.h" #include "bus.h" #include "mmc_ops.h"
@@ -1247,6 +1248,8 @@ static void mmc_blk_data_prep(struct mmc_queue *mq, struct mmc_queue_req *mqrq,memset (brq,0 ,sizeof (struct mmc_blk_request )); +mmc_crypto_prepare_req (mqrq); + brq->mrq.data = &brq->data; brq->mrq.tag = req->tag;
drivers/mmc/core/core.c +3 -0
@@ -37,6 +37,7 @@#include "core.h" #include "card.h" +#include "crypto.h" #include "bus.h" #include "host.h" #include "sdio_bus.h"
@@ -992,6 +993,8 @@ void mmc_set_initial_state(struct mmc_host *host) host->ops->hs400_enhanced_strobe (host, &host->ios);mmc_set_ios (host); + +mmc_crypto_set_initial_state (host); }/**
drivers/mmc/core/crypto.c new file +54 -0
54 lines not on this page · raw message
drivers/mmc/core/crypto.h new file +46 -0
46 lines not on this page · raw message
drivers/mmc/core/host.c +2 -0
@@ -25,6 +25,7 @@#include <linux/mmc/slot-gpio.h> #include "core.h" +#include "crypto.h" #include "host.h" #include "slot-gpio.h" #include "pwrseq.h"
@@ -532,6 +533,7 @@ EXPORT_SYMBOL(mmc_remove_host);*/ void mmc_free_host (struct mmc_host *host) { +mmc_crypto_free_host (host);mmc_pwrseq_free (host);put_device (&host->class_dev); }
drivers/mmc/core/queue.c +3 -0
@@ -19,6 +19,7 @@#include "block.h" #include "core.h" #include "card.h" +#include "crypto.h" #include "host.h" #define MMC_DMA_MAP_MERGE_SEGMENTS 512
@@ -405,6 +406,8 @@ static void mmc_setup_queue(struct mmc_queue *mq, struct mmc_card *card)mutex_init (&mq->complete_lock);init_waitqueue_head (&mq->wait); + +mmc_crypto_setup_queue (mq->queue, host); }static inline bool mmc_merge_capable (struct mmc_host *host)
include/linux/mmc/core.h +6 -0
@@ -162,6 +162,12 @@ struct mmc_request {bool cap_cmd_during_tfr;int tag; + +#ifdef CONFIG_MMC_CRYPTO +bool crypto_enabled; +int crypto_key_slot; +u32 data_unit_num; +#endif };struct mmc_card ;
include/linux/mmc/host.h +7 -0
@@ -15,6 +15,7 @@#include <linux/mmc/card.h> #include <linux/mmc/pm.h> #include <linux/dma-direction.h> +#include <linux/keyslot-manager.h> struct mmc_ios {unsigned int clock;/* clock rate */
@@ -384,6 +385,7 @@ struct mmc_host {#define MMC_CAP2_CQE_DCMD (1 << 24)/* CQE can issue a direct command */ #define MMC_CAP2_AVOID_3_3V (1 << 25)/* Host must negotiate down from 3.3V */ #define MMC_CAP2_MERGE_CAPABLE (1 << 26)/* Host can merge a segment over the segment size */ +#define MMC_CAP2_CRYPTO (1 << 27)/* Host supports inline encryption */ int fixed_drv_type;/* fixed driver type for non-removable media */
@@ -478,6 +480,11 @@ struct mmc_host {bool cqe_enabled;bool cqe_on; +/* Inline encryption support */ +#ifdef CONFIG_MMC_CRYPTO +struct blk_keyslot_manager ksm; +#endif +/* Host Software Queue support */ bool hsq_enabled;
Signature · 1 line
2.30.0
Re: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 23 lines · Eric Biggers
From: Eric Biggers <[email protected]>
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make
mmc_coreandmmc_blockaware of inline encryption. Specifically:- Add a capability flag
MMC_CAP2_CRYPTOto structmmc_host. Drivers will set this if the host and driver support inline encryption.- Embed a
blk_keyslot_managerin structmmc_host. Drivers will initialize this if the host and driver support inline encryption.mmc_blockregisters this keyslot manager with therequest_queueof any MMC card attached to the host.mmc_coredestroys this keyslot manager when freeing themmc_host.- Make
mmc_blockcopy the crypto keyslot and crypto data unit number from struct request to structmmc_request, so that drivers will have access to them.- If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state.
Quoted 6 lines
Co-developed-by Satya Tangirala <[email protected]>Signed-off-by Satya Tangirala <[email protected]>Acked-by Adrian Hunter <[email protected]>Reviewed-by Satya Tangirala <[email protected]>Reviewed-and-tested-by Peng Zhou <[email protected]>Signed-off-by Eric Biggers <[email protected]>
Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct blk_keyslot_manager ksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
Uffe
Quoted 20 lines
--- drivers/mmc/core/Kconfig | 8 ++++++ drivers/mmc/core/Makefile | 1 + drivers/mmc/core/block.c | 3 +++ drivers/mmc/core/core.c | 3 +++ drivers/mmc/core/crypto.c | 54 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/core/crypto.h | 46 +++++++++++++++++++++++++++++++++ drivers/mmc/core/host.c | 2 ++ drivers/mmc/core/queue.c | 3 +++ include/linux/mmc/core.h | 6 +++++ include/linux/mmc/host.h | 7 +++++ 10 files changed, 133 insertions(+) create mode 100644 drivers/mmc/core/crypto.c create mode 100644 drivers/mmc/core/crypto.hdrivers/mmc/core/Kconfig +0
-0
drivers/mmc/core/Kconfig config MMC_TEST · line 86
Quoted 6 lines
drivers/mmc/core/Kconfig +3
-0@@ -81,3 +81,11 @@ config MMC_TEST This driver is only of interest to those developing or testing a host driver. Most people should say N here. +config MMC_CRYPTO + bool "MMC Crypto Engine Support" + depends on BLK_INLINE_ENCRYPTION
What about making this "default y" as well.
Quoted 261 lines
drivers/mmc/core/Kconfig +5
-0+ help + Enable Crypto Engine Support in MMC. + Enabling this makes it possible for the kernel to use the crypto + capabilities of the MMC device (if present) to perform crypto + operations on data being transferred to/from the device.drivers/mmc/core/Makefile +1
-0@@ -18,3 +18,4 @@ obj-$(CONFIG_MMC_BLOCK) += mmc_block.o mmc_block-objs := block.o queue.o obj-$(CONFIG_MMC_TEST) += mmc_test.o obj-$(CONFIG_SDIO_UART) += sdio_uart.o +mmc_core-$(CONFIG_MMC_CRYPTO) += crypto.odrivers/mmc/core/block.c +3
-0@@ -51,6 +51,7 @@#include "block.h" #include "core.h" #include "card.h" +#include "crypto.h" #include "host.h" #include "bus.h" #include "mmc_ops.h" @@ -1247,6 +1248,8 @@ static void mmc_blk_data_prep(struct mmc_queue *mq, struct mmc_queue_req *mqrq,memset (brq,0 ,sizeof (struct mmc_blk_request )); +mmc_crypto_prepare_req (mqrq); + brq->mrq.data = &brq->data; brq->mrq.tag = req->tag;drivers/mmc/core/core.c +3
-0@@ -37,6 +37,7 @@#include "core.h" #include "card.h" +#include "crypto.h" #include "bus.h" #include "host.h" #include "sdio_bus.h" @@ -992,6 +993,8 @@ void mmc_set_initial_state(struct mmc_host *host) host->ops->hs400_enhanced_strobe (host, &host->ios);mmc_set_ios (host); + +mmc_crypto_set_initial_state (host); }/** drivers/mmc/core/crypto.c new file +54
-0@@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* MMC crypto engine (inline encryption) support +* +* Copyright 2020 Google LLC +*/ + +#include <linux/blk-crypto.h> +#include <linux/mmc/host.h> + +#include "core.h" +#include "crypto.h" +#include "queue.h" + +void mmc_crypto_set_initial_state (struct mmc_host *host) +{ +/* Reset might clear all keys, so reprogram all the keys. */ +if (host->caps2 &MMC_CAP2_CRYPTO ) +blk_ksm_reprogram_all_keys (&host->ksm); +} + +void mmc_crypto_free_host (struct mmc_host *host) +{ +if (host->caps2 &MMC_CAP2_CRYPTO ) +blk_ksm_destroy (&host->ksm); +} + +void mmc_crypto_setup_queue (struct request_queue *q,struct mmc_host *host) +{ +if (host->caps2 &MMC_CAP2_CRYPTO ) +blk_ksm_register (&host->ksm, q); +} +EXPORT_SYMBOL_GPL (mmc_crypto_setup_queue); + +void mmc_crypto_prepare_req (struct mmc_queue_req *mqrq) +{ +struct request *req =mmc_queue_req_to_req (mqrq); +struct mmc_request *mrq = &mqrq->brq.mrq; + +if (!req->crypt_keyslot) +return ; + + mrq->crypto_enabled = true; + mrq->crypto_key_slot =blk_ksm_get_slot_idx (req->crypt_keyslot); + +/* +* For now we assume that all MMC drivers set max_dun_bytes_supported=4, +* which is the limit for CQHCI crypto. So all DUNs should be 32-bit. +*/ +WARN_ON_ONCE (req->crypt_ctx->bc_dun[0 ] >U32_MAX ); + + mrq->data_unit_num = req->crypt_ctx->bc_dun[0 ]; +} +EXPORT_SYMBOL_GPL (mmc_crypto_prepare_req);drivers/mmc/core/crypto.h new file +46
-0@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* MMC crypto engine (inline encryption) support +* +* Copyright 2020 Google LLC +*/ + +#ifndef _MMC_CORE_CRYPTO_H +#define _MMC_CORE_CRYPTO_H + +struct mmc_host ; +struct mmc_queue_req ; +struct request_queue ; + +#ifdef CONFIG_MMC_CRYPTO + +void mmc_crypto_set_initial_state (struct mmc_host *host); + +void mmc_crypto_free_host (struct mmc_host *host); + +void mmc_crypto_setup_queue (struct request_queue *q,struct mmc_host *host); + +void mmc_crypto_prepare_req (struct mmc_queue_req *mqrq); + +#else /* CONFIG_MMC_CRYPTO */ + +static inline void mmc_crypto_set_initial_state (struct mmc_host *host) +{ +} + +static inline void mmc_crypto_free_host (struct mmc_host *host) +{ +} + +static inline void mmc_crypto_setup_queue (struct request_queue *q, +struct mmc_host *host) +{ +} + +static inline void mmc_crypto_prepare_req (struct mmc_queue_req *mqrq) +{ +} + +#endif /* !CONFIG_MMC_CRYPTO */ + +#endif /* _MMC_CORE_CRYPTO_H */ drivers/mmc/core/host.c +2
-0@@ -25,6 +25,7 @@#include <linux/mmc/slot-gpio.h> #include "core.h" +#include "crypto.h" #include "host.h" #include "slot-gpio.h" #include "pwrseq.h" @@ -532,6 +533,7 @@ EXPORT_SYMBOL(mmc_remove_host);*/ void mmc_free_host (struct mmc_host *host) { +mmc_crypto_free_host (host);mmc_pwrseq_free (host);put_device (&host->class_dev); }drivers/mmc/core/queue.c +3
-0@@ -19,6 +19,7 @@#include "block.h" #include "core.h" #include "card.h" +#include "crypto.h" #include "host.h" #define MMC_DMA_MAP_MERGE_SEGMENTS 512@@ -405,6 +406,8 @@ static void mmc_setup_queue(struct mmc_queue *mq, struct mmc_card *card)mutex_init (&mq->complete_lock);init_waitqueue_head (&mq->wait); + +mmc_crypto_setup_queue (mq->queue, host); }static inline bool mmc_merge_capable (struct mmc_host *host)include/linux/mmc/core.h +6
-0@@ -162,6 +162,12 @@ struct mmc_request {bool cap_cmd_during_tfr;int tag; + +#ifdef CONFIG_MMC_CRYPTO +bool crypto_enabled; +int crypto_key_slot; +u32 data_unit_num; +#endif };struct mmc_card ;include/linux/mmc/host.h +7
-1@@ -15,6 +15,7 @@#include <linux/mmc/card.h> #include <linux/mmc/pm.h> #include <linux/dma-direction.h> +#include <linux/keyslot-manager.h> struct mmc_ios {unsigned int clock;/* clock rate */ @@ -384,6 +385,7 @@ struct mmc_host {#define MMC_CAP2_CQE_DCMD (1 << 24)/* CQE can issue a direct command */ #define MMC_CAP2_AVOID_3_3V (1 << 25)/* Host must negotiate down from 3.3V */ #define MMC_CAP2_MERGE_CAPABLE (1 << 26)/* Host can merge a segment over the segment size */ +#define MMC_CAP2_CRYPTO (1 << 27)/* Host supports inline encryption */ int fixed_drv_type;/* fixed driver type for non-removable media */ @@ -478,6 +480,11 @@ struct mmc_host {bool cqe_enabled;bool cqe_on; +/* Inline encryption support */ +#ifdef CONFIG_MMC_CRYPTO +struct blk_keyslot_manager ksm; +#endif +/* Host Software Queue support */ bool hsq_enabled; --2.30.0
Eric Biggers
maintainerRe: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 39 lines · Ulf Hansson
Quoted 23 lines · Eric Biggers
From: Eric Biggers <[email protected]>
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make
mmc_coreandmmc_blockaware of inline encryption. Specifically:- Add a capability flag
MMC_CAP2_CRYPTOto structmmc_host. Drivers will set this if the host and driver support inline encryption.- Embed a
blk_keyslot_managerin structmmc_host. Drivers will initialize this if the host and driver support inline encryption.mmc_blockregisters this keyslot manager with therequest_queueof any MMC card attached to the host.mmc_coredestroys this keyslot manager when freeing themmc_host.- Make
mmc_blockcopy the crypto keyslot and crypto data unit number from struct request to structmmc_request, so that drivers will have access to them.- If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state.
Quoted 6 lines
Co-developed-by Satya Tangirala <[email protected]>Signed-off-by Satya Tangirala <[email protected]>Acked-by Adrian Hunter <[email protected]>Reviewed-by Satya Tangirala <[email protected]>Reviewed-and-tested-by Peng Zhou <[email protected]>Signed-off-by Eric Biggers <[email protected]>Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct
blk_keyslot_managerksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.
Quoted 5 lines
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
Uffe
The blk_keyslot_manager is initialized early on when the other host structures (struct mmc_host, struct cqhci_host, struct sdhci_host, struct sdhci_msm_host) are initialized, prior to mmc_add_host().
It is destroyed when the struct mmc_host is freed by mmc_free_host().
So it should just work; it's the same lifecycle as the existing host structures. Is there something you think I'm overlooking?
- Eric
Re: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 47 lines · Eric Biggers
Quoted 39 lines · Ulf Hansson
Quoted 23 lines · Eric Biggers
From: Eric Biggers <[email protected]>
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make
mmc_coreandmmc_blockaware of inline encryption. Specifically:- Add a capability flag
MMC_CAP2_CRYPTOto structmmc_host. Drivers will set this if the host and driver support inline encryption.- Embed a
blk_keyslot_managerin structmmc_host. Drivers will initialize this if the host and driver support inline encryption.mmc_blockregisters this keyslot manager with therequest_queueof any MMC card attached to the host.mmc_coredestroys this keyslot manager when freeing themmc_host.- Make
mmc_blockcopy the crypto keyslot and crypto data unit number from struct request to structmmc_request, so that drivers will have access to them.- If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state.
Quoted 6 lines
Co-developed-by Satya Tangirala <[email protected]>Signed-off-by Satya Tangirala <[email protected]>Acked-by Adrian Hunter <[email protected]>Reviewed-by Satya Tangirala <[email protected]>Reviewed-and-tested-by Peng Zhou <[email protected]>Signed-off-by Eric Biggers <[email protected]>Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct
blk_keyslot_managerksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.Quoted 5 lines
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
Uffe
Quoted 8 lines
The
blk_keyslot_manageris initialized early on when the other host structures (structmmc_host, structcqhci_host, structsdhci_host, structsdhci_msm_host) are initialized, prior tommc_add_host().It is destroyed when the struct
mmc_hostis freed bymmc_free_host().So it should just work; it's the same lifecycle as the existing host structures. Is there something you think I'm overlooking?
I think so, but let me elaborate a bit.
As I understand it, to initialize the data structures, blk_ksm_init() is getting called and via cqhci_init().
To hook up the block request queue, blk_ksm_register() is called via mmc_setup_queue(), which means this happens when the mmc block device driver is probed.
To free up the data structures, blk_ksm_destroy() is called from mmc_free_host().
To me, this can be made more consistent. For example, it looks like blk_ksm_destroy() could be called, even if blk_ksm_init() hasn't been called (depending on the probe error path of the mmc host).
There are a couple of options to better deal with this.
1) Extend the blk_ksm interface with a devm_blk_ksm_init() function (thus let it deal with lifecycle problems for us) and simply drop the call to blk_ksm_destroy().
2) Extend the cqhci interface with a cleanup function (perhaps "cqhci_deinit") and let it call blk_ksm_destroy().
3) Convert to let blk_ksm_init() to be called from mmc_add_host() and blk_ksm_destroy() from mmc_remove_host().
Moreover, even if there seems to be no real need to call blk_ksm_unregister() for the mmc block device driver, perhaps we should still do it to be consistent with blk_ksm_register()?
Then a final concern. It looks like the mmc core relies on checking "host->caps2 & MMC_CAP2_CRYPTO", when it calls blk_ksm_register() and blk_ksm_reprogram_all_keys(), for example. Normally, host->caps2 bits are considered as static configurations and set during the host driver probe path, which may not be a good match for this case. Instead, it seems like we should set a new separate flag, to indicate for the mmc core that blk_ksm_init has been enabled. Otherwise it looks like we could end up calling blk_ksm_reprogram_all_keys(), even if blk_ksm_init() hasn't been called.
Kind regards
Uffe
Eric Biggers
maintainerRe: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 23 lines · Ulf Hansson
Quoted 14 lines
Quoted 8 lines
Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct
blk_keyslot_managerksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.Quoted 5 lines
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
UffeQuoted 8 lines
The
blk_keyslot_manageris initialized early on when the other host structures (structmmc_host, structcqhci_host, structsdhci_host, structsdhci_msm_host) are initialized, prior tommc_add_host().It is destroyed when the struct
mmc_hostis freed bymmc_free_host().So it should just work; it's the same lifecycle as the existing host structures. Is there something you think I'm overlooking?
Quoted 8 lines
I think so, but let me elaborate a bit.
As I understand it, to initialize the data structures,
blk_ksm_init()is getting called and viacqhci_init().To hook up the block request queue,
blk_ksm_register()is called viammc_setup_queue(), which means this happens when the mmc block device driver is probed.
Well, the call to blk_ksm_register() happens in mmc_crypto_setup_queue(), when allocating the request_queue for a particular mmc_card. As far as I can tell, the mmc_host has already been initialized and added then, so we don't have to worry about cases where the mmc_host has only been partially initialized. And in particular, MMC_CAP2_CRYPTO will have its final value.
Quoted 7 lines
To free up the data structures,
blk_ksm_destroy()is called frommmc_free_host().To me, this can be made more consistent. For example, it looks like
blk_ksm_destroy()could be called, even ifblk_ksm_init()hasn't been called (depending on the probe error path of the mmc host).
blk_ksm_destroy() is a no-op on an all-zeroed struct, so it's fine to call it unnecessarily. We could call it unconditionally, if that would be clearer.
Quoted 4 lines
There are a couple of options to better deal with this.
1) Extend theblk_ksminterface with adevm_blk_ksm_init()function (thus let it deal with lifecycle problems for us) and simply drop the call toblk_ksm_destroy().
This would require adding APIs to devm to support zeroing buffers on free and to use kvmalloc() instead of kmalloc(). It looks like these new APIs wouldn't be useful for many drivers (since almost everyone else just wants regular kmalloc with no special behavior on free), so they don't seem worth adding yet.
Quoted 2 lines
2) Extend the cqhci interface with a cleanup function (perhaps "
cqhci_deinit") and let it callblk_ksm_destroy().
The blk_keyslot_manager is part of struct mmc_host, so it makes more sense for mmc_core to be responsible for freeing it.
We could move it to cqhci_host, but that would require adding multiple new function pointers to mmc_cqe_ops for use by mmc_crypto_set_initial_state(), mmc_crypto_free_host(), and mmc_crypto_setup_queue(), as these all currently need access to the blk_keyslot_manager.
I think that making mmc_core directly aware of the blk_keyslot_manager is the right call, as it avoids excessive callbacks, and it avoids tying the inline encryption support too closely to CQHCI. (Keep in mind that in the future, MMC hosts could support inline encryption using other interfaces besides CQHCI.)
Quoted 2 lines
3) Convert to let
blk_ksm_init()to be called frommmc_add_host()andblk_ksm_destroy()frommmc_remove_host().
That won't work because the driver has to fill in the crypto capabilities in the blk_keyslot_manager after calling blk_ksm_init(). mmc_add_host() is too late to do that. mmc_add_host() happens after the driver has already initialized the host structures and is finally registering them with the driver model.
Quoted 4 lines
Moreover, even if there seems to be no real need to call
blk_ksm_unregister()for the mmc block device driver, perhaps we should still do it to be consistent withblk_ksm_register()?
blk_ksm_unregister() isn't exported to modules. Its only purpose is for the block layer to disable inline encryption support on a disk if blk-integrity support is registered on the same disk. So it shouldn't (and can't) be called by drivers.
We probably should just remove blk_ksm_unregister() and make blk_integrity_register() set the ->ksm pointer to NULL directly. Also maybe blk_ksm_register() should be renamed to something like "queue_set_keyslot_manager()" to avoid implying that "unregister" is needed.
However those would be block layer changes, not related to this patchset.
Quoted 10 lines
Then a final concern. It looks like the mmc core relies on checking "
host->caps2&MMC_CAP2_CRYPTO", when it callsblk_ksm_register()andblk_ksm_reprogram_all_keys(), for example. Normally,host->caps2bits are considered as static configurations and set during the host driver probe path, which may not be a good match for this case. Instead, it seems like we should set a new separate flag, to indicate for the mmc core thatblk_ksm_inithas been enabled. Otherwise it looks like we could end up callingblk_ksm_reprogram_all_keys(), even ifblk_ksm_init()hasn't been called.
MMC_CAP2_CRYPTO *is* a static configuration that is set during the host driver probe path. So I don't understand your concern here.
It's true that during the host driver probe path, MMC_CAP2_CRYPTO initially means "the hardware might support crypto", and then cqhci_crypto_init() clears it if it decides that the hardware doesn't support crypto after all, after which the bit really does mean "the hardware supports crypto".
That seems fine because this all happens while the host structures are being initialized, before they are registered with the driver model and MMC cards are detected. So AFAICS there can't be any concurrent calls to mmc_crypto_set_initial_state() or mmc_crypto_setup_queue(). Do you think otherwise?
- Eric
Eric Biggers
maintainerRe: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 15 lines · Eric Biggers
Quoted 6 lines
To free up the data structures,
blk_ksm_destroy()is called frommmc_free_host().To me, this can be made more consistent. For example, it looks like
blk_ksm_destroy()could be called, even ifblk_ksm_init()hasn't been called (depending on the probe error path of the mmc host).
blk_ksm_destroy()is a no-op on an all-zeroed struct, so it's fine to call it unnecessarily. We could call it unconditionally, if that would be clearer.Quoted 4 lines
There are a couple of options to better deal with this.
1) Extend theblk_ksminterface with adevm_blk_ksm_init()function (thus let it deal with lifecycle problems for us) and simply drop the call toblk_ksm_destroy().
Quoted 4 lines
This would require adding APIs to devm to support zeroing buffers on free and to use
kvmalloc()instead ofkmalloc(). It looks like these new APIs wouldn't be useful for many drivers (since almost everyone else just wants regular kmalloc with no special behavior on free), so they don't seem worth adding yet.
Actually devres is more flexible than I thought; it's possible to register custom actions to be executed. I'll send out a patchset that adds devm_blk_ksm_init() and converts the UFS driver to use it.
- Eric
Eric Biggers
maintainerRe: [PATCH v4 1/9] mmc: add basic support for inline encryption
In reply to Eric BiggersQuoted 120 lines · Eric Biggers
Quoted 23 lines · Ulf Hansson
Quoted 14 lines
Quoted 8 lines
Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct
blk_keyslot_managerksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.Quoted 5 lines
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
UffeQuoted 8 lines
The
blk_keyslot_manageris initialized early on when the other host structures (structmmc_host, structcqhci_host, structsdhci_host, structsdhci_msm_host) are initialized, prior tommc_add_host().It is destroyed when the struct
mmc_hostis freed bymmc_free_host().So it should just work; it's the same lifecycle as the existing host structures. Is there something you think I'm overlooking?
Quoted 8 lines
I think so, but let me elaborate a bit.
As I understand it, to initialize the data structures,
blk_ksm_init()is getting called and viacqhci_init().To hook up the block request queue,
blk_ksm_register()is called viammc_setup_queue(), which means this happens when the mmc block device driver is probed.Well, the call to
blk_ksm_register()happens inmmc_crypto_setup_queue(), when allocating therequest_queuefor a particularmmc_card. As far as I can tell, themmc_hosthas already been initialized and added then, so we don't have to worry about cases where themmc_hosthas only been partially initialized. And in particular,MMC_CAP2_CRYPTOwill have its final value.Quoted 7 lines
To free up the data structures,
blk_ksm_destroy()is called frommmc_free_host().To me, this can be made more consistent. For example, it looks like
blk_ksm_destroy()could be called, even ifblk_ksm_init()hasn't been called (depending on the probe error path of the mmc host).
blk_ksm_destroy()is a no-op on an all-zeroed struct, so it's fine to call it unnecessarily. We could call it unconditionally, if that would be clearer.Quoted 4 lines
There are a couple of options to better deal with this.
1) Extend theblk_ksminterface with adevm_blk_ksm_init()function (thus let it deal with lifecycle problems for us) and simply drop the call toblk_ksm_destroy().This would require adding APIs to devm to support zeroing buffers on free and to use
kvmalloc()instead ofkmalloc(). It looks like these new APIs wouldn't be useful for many drivers (since almost everyone else just wants regular kmalloc with no special behavior on free), so they don't seem worth adding yet.Quoted 2 lines
2) Extend the cqhci interface with a cleanup function (perhaps "
cqhci_deinit") and let it callblk_ksm_destroy().The
blk_keyslot_manageris part of structmmc_host, so it makes more sense formmc_coreto be responsible for freeing it.We could move it to
cqhci_host, but that would require adding multiple new function pointers tommc_cqe_opsfor use bymmc_crypto_set_initial_state(),mmc_crypto_free_host(), andmmc_crypto_setup_queue(), as these all currently need access to theblk_keyslot_manager.I think that making
mmc_coredirectly aware of theblk_keyslot_manageris the right call, as it avoids excessive callbacks, and it avoids tying the inline encryption support too closely to CQHCI. (Keep in mind that in the future, MMC hosts could support inline encryption using other interfaces besides CQHCI.)Quoted 2 lines
3) Convert to let
blk_ksm_init()to be called frommmc_add_host()andblk_ksm_destroy()frommmc_remove_host().That won't work because the driver has to fill in the crypto capabilities in the
blk_keyslot_managerafter callingblk_ksm_init().mmc_add_host()is too late to do that.mmc_add_host()happens after the driver has already initialized the host structures and is finally registering them with the driver model.Quoted 4 lines
Moreover, even if there seems to be no real need to call
blk_ksm_unregister()for the mmc block device driver, perhaps we should still do it to be consistent withblk_ksm_register()?
blk_ksm_unregister()isn't exported to modules. Its only purpose is for the block layer to disable inline encryption support on a disk if blk-integrity support is registered on the same disk. So it shouldn't (and can't) be called by drivers.We probably should just remove
blk_ksm_unregister()and makeblk_integrity_register()set the ->ksm pointer to NULL directly. Also maybeblk_ksm_register()should be renamed to something like "queue_set_keyslot_manager()" to avoid implying that "unregister" is needed.However those would be block layer changes, not related to this patchset.
Quoted 10 lines
Then a final concern. It looks like the mmc core relies on checking "
host->caps2&MMC_CAP2_CRYPTO", when it callsblk_ksm_register()andblk_ksm_reprogram_all_keys(), for example. Normally,host->caps2bits are considered as static configurations and set during the host driver probe path, which may not be a good match for this case. Instead, it seems like we should set a new separate flag, to indicate for the mmc core thatblk_ksm_inithas been enabled. Otherwise it looks like we could end up callingblk_ksm_reprogram_all_keys(), even ifblk_ksm_init()hasn't been called.
MMC_CAP2_CRYPTO*is* a static configuration that is set during the host driver probe path. So I don't understand your concern here.It's true that during the host driver probe path,
MMC_CAP2_CRYPTOinitially means "the hardware might support crypto", and thencqhci_crypto_init()clears it if it decides that the hardware doesn't support crypto after all, after which the bit really does mean "the hardware supports crypto".
Quoted 5 lines
That seems fine because this all happens while the host structures are being initialized, before they are registered with the driver model and MMC cards are detected. So AFAICS there can't be any concurrent calls to
mmc_crypto_set_initial_state()ormmc_crypto_setup_queue(). Do you think otherwise?
I've sent out a new version of this patchset that uses the new function devm_blk_ksm_init() I've proposed, so that the blk_keyslot_manager no longer needs to be explicitly destroyed.
Please let me know if you still have any other concerns.
I think you may have been assuming that the blk_keyslot_manager doesn't get initialized until the CQE is enabled, and thus would have a separate lifetime from the other host structures? That's not what happens; it just gets initialized on the driver probe path. See e.g.:
sdhci_msm_probe() => sdhci_msm_cqe_add_host() => cqhci_init() => cqhci_crypto_init() => devm_blk_ksm_init()
And we don't leave MMC_CAP2_CRYPTO set but the blk_keyslot_manager uninitialized, as that combination doesn't make sense.
Thanks,
- Eric
Re: [PATCH v4 1/9] mmc: add basic support for inline encryption
Quoted 139 lines · Eric Biggers
Quoted 120 lines · Eric Biggers
Quoted 23 lines · Ulf Hansson
Quoted 14 lines
Quoted 8 lines
Eric, again, my apologies for the delay. Overall, I think this looks good.
My only hesitation to merge this as is, is that I want to make sure you have thought of the life cycle issues for the struct
blk_keyslot_managerksm. It's being used both from the mmc core/block device driver and the mmc host driver. I am looking at this right now and will get back to you very soon, if I find some issues with it.Quoted 5 lines
If you have some time, feel free to elaborate around how this is intended to work.
Kind regards
UffeQuoted 8 lines
The
blk_keyslot_manageris initialized early on when the other host structures (structmmc_host, structcqhci_host, structsdhci_host, structsdhci_msm_host) are initialized, prior tommc_add_host().It is destroyed when the struct
mmc_hostis freed bymmc_free_host().So it should just work; it's the same lifecycle as the existing host structures. Is there something you think I'm overlooking?
Quoted 8 lines
I think so, but let me elaborate a bit.
As I understand it, to initialize the data structures,
blk_ksm_init()is getting called and viacqhci_init().To hook up the block request queue,
blk_ksm_register()is called viammc_setup_queue(), which means this happens when the mmc block device driver is probed.Well, the call to
blk_ksm_register()happens inmmc_crypto_setup_queue(), when allocating therequest_queuefor a particularmmc_card. As far as I can tell, themmc_hosthas already been initialized and added then, so we don't have to worry about cases where themmc_hosthas only been partially initialized. And in particular,MMC_CAP2_CRYPTOwill have its final value.Quoted 7 lines
To free up the data structures,
blk_ksm_destroy()is called frommmc_free_host().To me, this can be made more consistent. For example, it looks like
blk_ksm_destroy()could be called, even ifblk_ksm_init()hasn't been called (depending on the probe error path of the mmc host).
blk_ksm_destroy()is a no-op on an all-zeroed struct, so it's fine to call it unnecessarily. We could call it unconditionally, if that would be clearer.Quoted 4 lines
There are a couple of options to better deal with this.
1) Extend theblk_ksminterface with adevm_blk_ksm_init()function (thus let it deal with lifecycle problems for us) and simply drop the call toblk_ksm_destroy().This would require adding APIs to devm to support zeroing buffers on free and to use
kvmalloc()instead ofkmalloc(). It looks like these new APIs wouldn't be useful for many drivers (since almost everyone else just wants regular kmalloc with no special behavior on free), so they don't seem worth adding yet.Quoted 2 lines
2) Extend the cqhci interface with a cleanup function (perhaps "
cqhci_deinit") and let it callblk_ksm_destroy().The
blk_keyslot_manageris part of structmmc_host, so it makes more sense formmc_coreto be responsible for freeing it.We could move it to
cqhci_host, but that would require adding multiple new function pointers tommc_cqe_opsfor use bymmc_crypto_set_initial_state(),mmc_crypto_free_host(), andmmc_crypto_setup_queue(), as these all currently need access to theblk_keyslot_manager.I think that making
mmc_coredirectly aware of theblk_keyslot_manageris the right call, as it avoids excessive callbacks, and it avoids tying the inline encryption support too closely to CQHCI. (Keep in mind that in the future, MMC hosts could support inline encryption using other interfaces besides CQHCI.)Quoted 2 lines
3) Convert to let
blk_ksm_init()to be called frommmc_add_host()andblk_ksm_destroy()frommmc_remove_host().That won't work because the driver has to fill in the crypto capabilities in the
blk_keyslot_managerafter callingblk_ksm_init().mmc_add_host()is too late to do that.mmc_add_host()happens after the driver has already initialized the host structures and is finally registering them with the driver model.Quoted 4 lines
Moreover, even if there seems to be no real need to call
blk_ksm_unregister()for the mmc block device driver, perhaps we should still do it to be consistent withblk_ksm_register()?
blk_ksm_unregister()isn't exported to modules. Its only purpose is for the block layer to disable inline encryption support on a disk if blk-integrity support is registered on the same disk. So it shouldn't (and can't) be called by drivers.We probably should just remove
blk_ksm_unregister()and makeblk_integrity_register()set the ->ksm pointer to NULL directly. Also maybeblk_ksm_register()should be renamed to something like "queue_set_keyslot_manager()" to avoid implying that "unregister" is needed.However those would be block layer changes, not related to this patchset.
Quoted 10 lines
Then a final concern. It looks like the mmc core relies on checking "
host->caps2&MMC_CAP2_CRYPTO", when it callsblk_ksm_register()andblk_ksm_reprogram_all_keys(), for example. Normally,host->caps2bits are considered as static configurations and set during the host driver probe path, which may not be a good match for this case. Instead, it seems like we should set a new separate flag, to indicate for the mmc core thatblk_ksm_inithas been enabled. Otherwise it looks like we could end up callingblk_ksm_reprogram_all_keys(), even ifblk_ksm_init()hasn't been called.
MMC_CAP2_CRYPTO*is* a static configuration that is set during the host driver probe path. So I don't understand your concern here.It's true that during the host driver probe path,
MMC_CAP2_CRYPTOinitially means "the hardware might support crypto", and thencqhci_crypto_init()clears it if it decides that the hardware doesn't support crypto after all, after which the bit really does mean "the hardware supports crypto".Quoted 5 lines
That seems fine because this all happens while the host structures are being initialized, before they are registered with the driver model and MMC cards are detected. So AFAICS there can't be any concurrent calls to
mmc_crypto_set_initial_state()ormmc_crypto_setup_queue(). Do you think otherwise?I've sent out a new version of this patchset that uses the new function
devm_blk_ksm_init()I've proposed, so that theblk_keyslot_managerno longer needs to be explicitly destroyed.Please let me know if you still have any other concerns.
I think you may have been assuming that the
blk_keyslot_managerdoesn't get initialized until the CQE is enabled, and thus would have a separate lifetime from the other host structures? That's not what happens; it just gets initialized on the driver probe path. See e.g.:
Quoted 8 lines
sdhci_msm_probe() => sdhci_msm_cqe_add_host() => cqhci_init() => cqhci_crypto_init() => devm_blk_ksm_init()And we don't leave
MMC_CAP2_CRYPTOset but theblk_keyslot_manageruninitialized, as that combination doesn't make sense.
I think we still can (but we shouldn't), but see my reply on the latest version.
Besides that minor thing, the latest version looks good to me. Thanks for doing the conversion to devm_blk_ksm_init() - it certainly simplifies the lifecycle issue for this case.
Kind regards
Uffe
Eric Biggers
maintainerPATCH v4 2/9 mmc: cqhci: rename cqhci.c to cqhci-core.c
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Rename cqhci.c to cqhci-core.c so that another source file can be added to the cqhci module without having to rename the module.
---
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/{cqhci.c => cqhci-core.c} | 0
2 files changed, 1 insertion(+)
rename drivers/mmc/host/{cqhci.c => cqhci-core.c} (100%)drivers/mmc/host/Makefile +1 -0
@@ -104,6 +104,7 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o +cqhci-y += cqhci-core.o obj-$(CONFIG_MMC_HSQ) += mmc_hsq.o ifeq ($(CONFIG_CB710_DEBUG),y)
drivers/mmc/host/cqhci-core.c renamed from drivers/mmc/host/cqhci.c +0 -0
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 3/9 mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Move the task descriptor initialization into cqhci_prep_task_desc(). In addition, make it explicitly initialize all 128 bits of the task descriptor if the host controller is using 128-bit task descriptors, rather than relying on the implicit zeroing from dmam_alloc_coherent().
This is needed to prepare for CQHCI inline encryption support, which requires 128-bit task descriptors and uses the upper 64 bits.
--- drivers/mmc/host/cqhci-core.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-)
drivers/mmc/host/cqhci-core.c +20 -10
@@ -408,13 +408,15 @@ static void cqhci_disable(struct mmc_host *mmc) }static void cqhci_prep_task_desc (struct mmc_request *mrq, -u64 *data,bool intr) +struct cqhci_host *cq_host,int tag) { +__le64 *task_desc = (__le64 __force *)get_desc (cq_host, tag);u32 req_flags = mrq->data->flags; +u64 desc0; - *data =CQHCI_VALID (1 ) | + desc0 =CQHCI_VALID (1 ) |CQHCI_END (1 ) | -CQHCI_INT (intr) | +CQHCI_INT (1 ) |CQHCI_ACT (0x5 ) |CQHCI_FORCED_PROG (!!(req_flags &MMC_DATA_FORCED_PRG )) | CQHCI_DATA_TAG(!!(req_flags & MMC_DATA_DAT_TAG)) |
@@ -425,8 +427,19 @@ static void cqhci_prep_task_desc(struct mmc_request *mrq,CQHCI_BLK_COUNT (mrq->data->blocks) |CQHCI_BLK_ADDR ((u64 )mrq->data->blk_addr); -pr_debug ("%s: cqhci: tag %d task descriptor 0x%016llx\n" , -mmc_hostname (mrq->host), mrq->tag, (unsigned long long )*data); + task_desc[0 ] =cpu_to_le64 (desc0); + +if (cq_host->caps &CQHCI_TASK_DESC_SZ_128 ) { +u64 desc1 =0 ; + + task_desc[1 ] =cpu_to_le64 (desc1); + +pr_debug ("%s: cqhci: tag %d task descriptor 0x%016llx%016llx\n" , +mmc_hostname (mrq->host), mrq->tag, desc1, desc0); + }else { +pr_debug ("%s: cqhci: tag %d task descriptor 0x%016llx\n" , +mmc_hostname (mrq->host), mrq->tag, desc0); + } }static int cqhci_dma_map (struct mmc_host *host,struct mmc_request *mrq)
@@ -567,8 +580,6 @@ static inline int cqhci_tag(struct mmc_request *mrq)static int cqhci_request (struct mmc_host *mmc,struct mmc_request *mrq) {int err =0 ; -u64 data =0 ; -u64 *task_desc =NULL ;int tag =cqhci_tag (mrq);struct cqhci_host *cq_host = mmc->cqe_private;unsigned long flags;
@@ -598,9 +609,8 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq) }if (mrq->data) { - task_desc = (__le64 __force *)get_desc (cq_host, tag); -cqhci_prep_task_desc (mrq, &data,1 ); - *task_desc =cpu_to_le64 (data); +cqhci_prep_task_desc (mrq, cq_host, tag); + err =cqhci_prep_tran_desc (mrq, cq_host, tag);if (err) { pr_err("%s: cqhci: failed to setup tx desc: %d\n",
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 4/9 mmc: cqhci: add support for inline encryption
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Add support for eMMC inline encryption using the blk-crypto framework (Documentation/block/inline-encryption.rst).
eMMC inline encryption support is specified by the upcoming JEDEC eMMC v5.2 specification. It is only specified for the CQ interface, not the non-CQ interface. Although the eMMC v5.2 specification hasn't been officially released yet, the crypto support was already agreed on several years ago, and it was already implemented by at least two major hardware vendors. Lots of hardware in the field already supports and uses it, e.g. Snapdragon 630 to give one example.
eMMC inline encryption support is very similar to the UFS inline encryption support which was standardized in the UFS v2.1 specification and was already upstreamed. The only major difference is that eMMC limits data unit numbers to 32 bits, unlike UFS's 64 bits.
Like we did with UFS, make the crypto support opt-in by individual drivers; don't enable it automatically whenever the hardware declares crypto support. This is necessary because in every case we've seen, some extra vendor-specific logic is needed to use the crypto support.
--- drivers/mmc/host/Makefile | 1 + drivers/mmc/host/cqhci-core.c | 41 +++++- drivers/mmc/host/cqhci-crypto.c | 241 ++++++++++++++++++++++++++++++++ drivers/mmc/host/cqhci-crypto.h | 47 +++++++ drivers/mmc/host/cqhci.h | 80 ++++++++++- 5 files changed, 407 insertions(+), 3 deletions(-) create mode 100644 drivers/mmc/host/cqhci-crypto.c create mode 100644 drivers/mmc/host/cqhci-crypto.h
drivers/mmc/host/Makefile +1 -0
@@ -105,6 +105,7 @@ obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o cqhci-y += cqhci-core.o +cqhci-$(CONFIG_MMC_CRYPTO) += cqhci-crypto.o obj-$(CONFIG_MMC_HSQ) += mmc_hsq.o ifeq ($(CONFIG_CB710_DEBUG),y)
drivers/mmc/host/cqhci-core.c +39 -2
83 lines not on this page · raw message
drivers/mmc/host/cqhci-crypto.c new file +241 -0
241 lines not on this page · raw message
drivers/mmc/host/cqhci-crypto.h new file +47 -0
47 lines not on this page · raw message
drivers/mmc/host/cqhci.h +79 -1
126 lines not on this page · raw message
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 5/9 mmc: cqhci: add cqhci_host_ops::program_key
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
On Snapdragon SoCs, the Linux kernel isn't permitted to directly access the standard CQHCI crypto configuration registers. Instead, programming and evicting keys must be done through vendor-specific SMC calls.
To support this hardware, add a ->program_key() method to 'struct cqhci_host_ops'. This allows overriding the standard CQHCI crypto key programming / eviction procedure.
This is inspired by the corresponding UFS crypto support, which uses these same SMC calls. See commit 1bc726e26ef3 ("scsi: ufs: Add program_key() variant op").
--- drivers/mmc/host/cqhci-crypto.c | 22 +++++++++++++--------- drivers/mmc/host/cqhci.h | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-)
drivers/mmc/host/cqhci-crypto.c +13 -9
@@ -30,13 +30,16 @@ cqhci_host_from_ksm(struct blk_keyslot_manager *ksm)return mmc->cqe_private; } -static void cqhci_crypto_program_key (struct cqhci_host *cq_host, -const union cqhci_crypto_cfg_entry *cfg, -int slot) +static int cqhci_crypto_program_key (struct cqhci_host *cq_host, +const union cqhci_crypto_cfg_entry *cfg, +int slot) {u32 slot_offset = cq_host->crypto_cfg_register + slot *sizeof (*cfg);int i; +if (cq_host->ops->program_key) +return cq_host->ops->program_key (cq_host, cfg, slot); +/* Clear CFGE */ cqhci_writel (cq_host,0 , slot_offset +16 *sizeof (cfg->reg_val[0 ]));
@@ -51,6 +54,7 @@ static void cqhci_crypto_program_key(struct cqhci_host *cq_host,/* Write dword 16, which includes the new value of CFGE */ cqhci_writel (cq_host,le32_to_cpu (cfg->reg_val[16 ]), slot_offset +16 *sizeof (cfg->reg_val[0 ])); +return 0 ; } static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
@@ -67,6 +71,7 @@ static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,int i;int cap_idx =-1 ;union cqhci_crypto_cfg_entry cfg = {}; +int err;BUILD_BUG_ON (CQHCI_CRYPTO_KEY_SIZE_INVALID !=0 );for (i =0 ; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
@@ -93,13 +98,13 @@ static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,memcpy (cfg.crypto_key, key->raw, key->size); } -cqhci_crypto_program_key (cq_host, &cfg, slot); + err =cqhci_crypto_program_key (cq_host, &cfg, slot);memzero_explicit (&cfg,sizeof (cfg)); -return 0 ; +return err; } -static void cqhci_crypto_clear_keyslot (struct cqhci_host *cq_host,int slot) +static int cqhci_crypto_clear_keyslot (struct cqhci_host *cq_host,int slot) {/* * Clear the crypto cfg on the device. Clearing CFGE
@@ -107,7 +112,7 @@ static void cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)*/ union cqhci_crypto_cfg_entry cfg = {}; -cqhci_crypto_program_key (cq_host, &cfg, slot); +return cqhci_crypto_program_key (cq_host, &cfg, slot); } static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
@@ -116,8 +121,7 @@ static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm, {struct cqhci_host *cq_host =cqhci_host_from_ksm (ksm); -cqhci_crypto_clear_keyslot (cq_host, slot); -return 0 ; +return cqhci_crypto_clear_keyslot (cq_host, slot); }/*
drivers/mmc/host/cqhci.h +4 -0
@@ -286,6 +286,10 @@ struct cqhci_host_ops { u64 *data);void (*pre_enable)(struct mmc_host *mmc);void (*post_disable)(struct mmc_host *mmc); +#ifdef CONFIG_MMC_CRYPTO +int (*program_key)(struct cqhci_host *cq_host, +const union cqhci_crypto_cfg_entry *cfg,int slot); +#endif };static inline void cqhci_writel (struct cqhci_host *host,u32 val,int reg)
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 6/9 firmware: qcom_scm: update comment for ICE-related functions
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
The SCM calls QCOM_SCM_ES_INVALIDATE_ICE_KEY and QCOM_SCM_ES_CONFIG_SET_ICE_KEY are also needed for eMMC inline encryption support, not just for UFS. Update the comments accordingly.
--- drivers/firmware/qcom_scm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
drivers/firmware/qcom_scm.c +11 -5
@@ -965,8 +965,11 @@ EXPORT_SYMBOL(qcom_scm_ice_available);* qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key * @index: the keyslot to invalidate * -* The UFSHCI standard defines a standard way to do this, but it doesn't work on -* these SoCs; only this SCM call does. +* The UFSHCI and eMMC standards define a standard way to do this, but it +* doesn't work on these SoCs; only this SCM call does. +* +* It is assumed that the SoC has only one ICE instance being used, as this SCM +* call doesn't specify which ICE instance the keyslot belongs to. * * Return: 0 on success; -errno on failure. */
@@ -995,10 +998,13 @@ EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);* units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc. * * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it -* can then be used to encrypt/decrypt UFS I/O requests inline. +* can then be used to encrypt/decrypt UFS or eMMC I/O requests inline. +* +* The UFSHCI and eMMC standards define a standard way to do this, but it +* doesn't work on these SoCs; only this SCM call does. * -* The UFSHCI standard defines a standard way to do this, but it doesn't work on -* these SoCs; only this SCM call does. +* It is assumed that the SoC has only one ICE instance being used, as this SCM +* call doesn't specify which ICE instance the keyslot belongs to. * * Return: 0 on success; -errno on failure. */
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 7/9 dt-bindings: mmc: sdhci-msm: add ICE registers and clock
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Document the bindings for the registers and clock for the MMC instance of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings are needed in order for sdhci-msm to support inline encryption.
--- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/mmc/sdhci-msm.txt +3 -0
@@ -30,10 +30,12 @@ Required properties: - SD Core register map (required for controllers earlier than msm-v5) - CQE register map (Optional, CQE support is present on SDHC instance meant for eMMC and version v4.2 and above) + - Inline Crypto Engine register map (optional) - reg-names: When CQE register map is supplied, below reg-names are required - "hc" for Host controller register map - "core" for SD core register map - "cqhci" for CQE register map + - "ice" for Inline Crypto Engine register map (optional) - interrupts: Should contain an interrupt-specifiers for the interrupts: - Host controller interrupt (required) - pinctrl-names: Should contain only one value - "default".
@@ -46,6 +48,7 @@ Required properties: "xo" - TCXO clock (optional) "cal" - reference clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional) + "ice" - clock for Inline Crypto Engine (optional) - qcom,ddr-config: Certain chipsets and platforms require particular settings for the DDR_CONFIG register. Use this field to specify the register
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 8/9 arm64: dts: qcom: sdm630: add ICE registers and clocks
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Add the registers and clock for the Inline Crypto Engine (ICE) to the device tree node for the sdhci-msm host controller on sdm630. This allows sdhci-msm to support inline encryption on sdm630.
--- arch/arm64/boot/dts/qcom/sdm630.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/qcom/sdm630.dtsi +6 -4
@@ -808,8 +808,9 @@ spmi_bus: spmi@800f000 { sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, - <0x0c0c5000 0x1000>; - reg-names = "hc", "cqhci"; + <0x0c0c5000 0x1000>, + <0x0c0c8000 0x8000>; + reg-names = "hc", "cqhci", "ice"; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
@@ -817,8 +818,9 @@ sdhc_1: sdhci@c0c4000 { clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "xo", "ice"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
Signature · 1 line
2.30.0
Eric Biggers
maintainerPATCH v4 9/9 mmc: sdhci-msm: add Inline Crypto Engine support
In reply to Eric BiggersFrom: Eric Biggers <[email protected]>
Add support for Qualcomm Inline Crypto Engine (ICE) to sdhci-msm.
The standard-compliant parts, such as querying the crypto capabilities and enabling crypto for individual MMC requests, are already handled by cqhci-crypto.c, which itself is wired into the blk-crypto framework. However, ICE requires vendor-specific init, enable, and resume logic, and it requires that keys be programmed and evicted by vendor-specific SMC calls. Make the sdhci-msm driver handle these details.
This is heavily inspired by the similar changes made for UFS, since the UFS and eMMC ICE instances are very similar. See commit df4ec2fa7a4d ("scsi: ufs-qcom: Add Inline Crypto Engine support").
I tested this on a Sony Xperia 10, which uses the Snapdragon 630 SoC, which has basic upstream support. Mainly, I used android-xfstests
(https://github.com/tytso/xfstests-bld/blob/master/Documentation/android-xfstests.md)
to run the ext4 and f2fs encryption tests in a Debian chroot:
android-xfstests -c ext4,f2fs -g encrypt -m inlinecrypt
These tests included tests which verify that the on-disk ciphertext is identical to that produced by a software implementation. I also verified that ICE was actually being used.
--- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-msm.c | 276 ++++++++++++++++++++++++++++++++++- 2 files changed, 273 insertions(+), 4 deletions(-)
drivers/mmc/host/Kconfig +1 -0
@@ -544,6 +544,7 @@ config MMC_SDHCI_MSM depends on MMC_SDHCI_PLTFM select MMC_SDHCI_IO_ACCESSORS select MMC_CQHCI + select QCOM_SCM if MMC_CRYPTO && ARCH_QCOM help This selects the Secure Digital Host Controller Interface (SDHCI) support present in Qualcomm SOCs. The controller supports
drivers/mmc/host/sdhci-msm.c +272 -4
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Signature · 1 line
2.30.0