SM8350 USB and dt-bindings updates
cover SM8350 USB and dt-bindings updates
This series adds support for the SM8350 USB PHY to the QMP PHY driver as well as adds the documentation for the QMP, SNPS PHY and DWC3 controller bindings. This also adds the bindings for SM8150 and SM8250 to the same docs which had not been added previously even though they are in use now.
Jack Pham (4):
phy: qcom-qmp: Add SM8350 USB QMP PHYs
dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY
bindings
dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350
bindings
dt-bindings: usb: qcom,dwc3: Add bindings for SM8150, SM8250, SM8350
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 67 ++++++ .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 2 + .../devicetree/bindings/usb/qcom,dwc3.yaml | 3 + drivers/phy/qualcomm/phy-qcom-qmp.c | 209 ++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 100 +++++++++ 5 files changed, 381 insertions(+)
Signature · 1 line
2.24.0
PATCH 1/4 phy: qcom-qmp: Add SM8350 USB QMP PHYs
Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused.
Signed-off-by Jack Pham <[email protected]>
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 209 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 100 +++++++++++++ 2 files changed, 309 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp.c +209 -0
@@ -216,6 +216,15 @@ static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, }; +static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE ] = { + [QPHY_SW_RESET ] =0x00 , + [QPHY_START_CTRL ] =0x44 , + [QPHY_PCS_STATUS ] =0x14 , + [QPHY_PCS_POWER_DOWN_CONTROL ] =0x40 , + [QPHY_PCS_AUTONOMOUS_MODE_CTRL ] =0x1008 , + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR ] =0x1014 , +}; +static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE ] = { [QPHY_START_CTRL ] =0x00 , [QPHY_PCS_READY_STATUS ] =0x160 ,
@@ -2025,6 +2034,144 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), }; +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_TX ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_RX ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX ,0x16 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_1 ,0x35 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_3 ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_4 ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_5 ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RCV_DETECT_LVL_2 ,0x12 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_PI_QEC_CTRL ,0x21 ), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FO_GAIN ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SO_GAIN ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN ,0x2f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_PI_CONTROLS ,0x99 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_THRESH1 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_THRESH2 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_GAIN1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_GAIN2 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_VGA_CAL_CNTRL1 ,0x54 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_VGA_CAL_CNTRL2 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 ,0x4a ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW ,0xc0 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x47 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_SIGDET_CNTRL ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_LOW ,0xbb ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH ,0x7b ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH2 ,0xbb ), +QMP_PHY_INIT_CFG_LANE (QSERDES_V5_RX_RX_MODE_00_HIGH3 ,0x3d ,1 ), +QMP_PHY_INIT_CFG_LANE (QSERDES_V5_RX_RX_MODE_00_HIGH3 ,0x3c ,2 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH4 ,0xdb ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_LOW ,0x64 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH2 ,0xd2 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH3 ,0x13 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH4 ,0xa9 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_DFE_EN_TIMER ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET ,0x38 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE ,0xa0 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_DCC_CTRL1 ,0x0c ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_GM_CAL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_VTH_CODE ,0x10 ), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L ,0x40 ), +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H ,0x00 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L ,0xe7 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H ,0x03 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG1 ,0xd0 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG2 ,0x07 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG3 ,0x20 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG6 ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_REFGEN_REQ_CONFIG1 ,0x21 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RX_SIGDET_LVL ,0xaa ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_CDR_RESET_TIME ,0x0a ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCS_TX_RX_CONFIG ,0x0c ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG1 ,0x4b ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG5 ,0x10 ), +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL ,0xf8 ), +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 ,0x07 ), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_1 ,0xa5 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_2 ,0x82 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_3 ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_LANE_MODE_4 ,0x3f ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_PI_QEC_CTRL ,0x21 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX ,0x10 ), +QMP_PHY_INIT_CFG (QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX ,0x0e ), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH4 ,0xdc ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH3 ,0xbd ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH2 ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_HIGH ,0x7f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_00_LOW ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH4 ,0xa9 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH3 ,0x7b ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH2 ,0xe4 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_HIGH ,0x24 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_MODE_01_LOW ,0x64 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_PI_CONTROLS ,0x99 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_THRESH1 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_THRESH2 ,0x08 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_GAIN1 ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SB2_GAIN2 ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN ,0x2f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW ,0xff ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_FO_GAIN ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_VGA_CAL_CNTRL1 ,0x54 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_VGA_CAL_CNTRL2 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 ,0x0f ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 ,0x0a ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 ,0x47 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 ,0x80 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_SIGDET_CNTRL ,0x04 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL ,0x0e ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET ,0x38 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_UCDR_SO_GAIN ,0x05 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_GM_CAL ,0x00 ), +QMP_PHY_INIT_CFG (QSERDES_V5_RX_SIGDET_ENABLES ,0x00 ), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG1 ,0xd0 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG2 ,0x07 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG3 ,0x20 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_LOCK_DETECT_CONFIG6 ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L ,0xe7 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H ,0x03 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_RX_SIGDET_LVL ,0xaa ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_PCS_TX_RX_CONFIG ,0x0c ), +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 ,0x07 ), +QMP_PHY_INIT_CFG (QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL ,0xf8 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_CDR_RESET_TIME ,0x0a ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 ,0x88 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 ,0x13 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG1 ,0x4b ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_EQ_CONFIG5 ,0x10 ), +QMP_PHY_INIT_CFG (QPHY_V4_PCS_REFGEN_REQ_CONFIG1 ,0x21 ), +}; +/* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg {/* phy-type - PCIE/UFS/USB */
@@ -2917,6 +3064,65 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { + .type =PHY_TYPE_USB3 , + .nlanes =1 , + + .serdes_tbl = sm8150_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (sm8150_usb3_serdes_tbl), + .tx_tbl = sm8350_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (sm8350_usb3_tx_tbl), + .rx_tbl = sm8350_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (sm8350_usb3_rx_tbl), + .pcs_tbl = sm8350_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (sm8350_usb3_pcs_tbl), + .clk_list = qmp_v4_sm8250_usbphy_clk_l, + .num_clks =ARRAY_SIZE (qmp_v4_sm8250_usbphy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .start_ctrl =SERDES_START |PCS_START , + .pwrdn_ctrl =SW_PWRDN , + + .has_pwrdn_delay = true, + .pwrdn_delay_min =POWER_DOWN_DELAY_US_MIN , + .pwrdn_delay_max =POWER_DOWN_DELAY_US_MAX , + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; + +static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { + .type =PHY_TYPE_USB3 , + .nlanes =1 , + + .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (sm8150_usb3_uniphy_serdes_tbl), + .tx_tbl = sm8350_usb3_uniphy_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (sm8350_usb3_uniphy_tx_tbl), + .rx_tbl = sm8350_usb3_uniphy_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (sm8350_usb3_uniphy_rx_tbl), + .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (sm8350_usb3_uniphy_pcs_tbl), + .clk_list = qmp_v4_phy_clk_l, + .num_clks =ARRAY_SIZE (qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = sm8350_usb3_uniphy_regs_layout, + + .start_ctrl =SERDES_START |PCS_START , + .pwrdn_ctrl =SW_PWRDN , + + .has_pwrdn_delay = true, + .pwrdn_delay_min =POWER_DOWN_DELAY_US_MIN , + .pwrdn_delay_max =POWER_DOWN_DELAY_US_MAX , +}; + static void qcom_qmp_phy_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[],
@@ -4267,6 +4473,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sdx55-qmp-usb3-uni-phy", .data = &sdx55_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-usb3-phy", + .data = &sm8350_usb3phy_cfg, }, { }, };
drivers/phy/qualcomm/phy-qcom-qmp.h +100 -0
104 lines not on this page · raw message
Signature · 1 line
2.24.0
Re: [PATCH 1/4] phy: qcom-qmp: Add SM8350 USB QMP PHYs
Hi,
I might be wrong but it looks as if you forgot to add a compatible for the "sm8350_usb3_uniphy_cfg" configuration.
Konrad
Vinod Koul
maintainerRe: [PATCH 1/4] phy: qcom-qmp: Add SM8350 USB QMP PHYs
Quoted 4 lines · Konrad Dybcio
Hi,
I might be wrong but it looks as if you forgot to add a compatible for the "
sm8350_usb3_uniphy_cfg" configuration.
It seems to be documented in patch 2, ideally we should have the bindings patches first and this as patch 3...
Quoted 3 lines
Konrad
Signature · 1 line
~Vinod
Re: [PATCH 1/4] phy: qcom-qmp: Add SM8350 USB QMP PHYs
Hi Vinod,
Quoted 3 lines · Vinod Koul
Quoted 2 lines · Konrad Dybcio
I might be wrong but it looks as if you forgot to add a compatible for the "
sm8350_usb3_uniphy_cfg" configuration.
I believe Konrad was referring to the driver in which I had neglected to add the compatible to the qcom_qmp_phy_of_match_table. My mistake.
Quoted 2 lines
It seems to be documented in patch 2, ideally we should have the bindings patches first and this as patch 3...
Ok. I think driver change would be patch 2 rather, with the bindings in patch 1? Patch 3 and 4 are dt-bindings updates to the SNPS Femto PHY and DWC3 QCOM docs respectively.
Will send v2, thanks.
Jack
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 1/4] phy: qcom-qmp: Add SM8350 USB QMP PHYs
In reply to Konrad DybcioQuoted 2 lines · Konrad Dybcio
I might be wrong but it looks as if you forgot to add a compatible for the "
sm8350_usb3_uniphy_cfg" configuration.
Not wrong at all! My mistake, will add it in v2.
Thanks,
Jack
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 2/4 dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY bindings
In reply to Jack PhamAdd the compatible strings for the USB3 PHYs found on SM8150, SM8250 and SM8350 SoCs.
Note the SM8150 and SM8250 compatibles have already been in place in the dts as well as the driver implementation but were missing from the documentation.
Signed-off-by Jack Pham <[email protected]>
--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+)
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +67 -0
@@ -30,15 +30,24 @@ properties: - qcom,sdm845-qmp-ufs-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy + - qcom,sm8150-qmp-usb3-phy + - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-ufs-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8250-qmp-usb3-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-phy + - qcom,sm8350-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy reg: + minItems: 1 + maxItems: 2 items: - description: Address and length of PHY's common serdes block. + - description: Address and length of PHY's DP_COM control block. "#clock-cells": enum: [ 1, 2 ]
@@ -287,6 +296,64 @@ allOf: reset-names: items: - const: phy + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8150-qmp-usb3-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-uni-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: 19.2 MHz ref clk source. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: ref + - const: com_aux + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8250-qmp-usb3-phy + - qcom,sm8350-qmp-usb3-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: com_aux + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common examples: - |
Signature · 1 line
2.24.0
PATCH 3/4 dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350 bindings
In reply to Jack PhamAdd the compatible strings for the USB2 PHYs found on QCOM SM8250 & SM8350 SoCs.
Note that the SM8250 compatible is already in use in the dts and driver implementation but was missing from the documentation.
Signed-off-by Jack Pham <[email protected]>
--- .../devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +2 -0
@@ -17,6 +17,8 @@ properties: enum: - qcom,usb-snps-hs-7nm-phy - qcom,sm8150-usb-hs-phy + - qcom,sm8250-usb-hs-phy + - qcom,sm8350-usb-hs-phy - qcom,usb-snps-femto-v2-phy reg:
Signature · 1 line
2.24.0
PATCH 4/4 dt-bindings: usb: qcom,dwc3: Add bindings for SM8150, SM8250, SM8350
In reply to Jack PhamAdd compatible strings for the USB DWC3 controller on QCOM SM8150, SM8250 and SM8350 SoCs.
Note the SM8150 & SM8250 compatibles are already being used in the dts and driver implementation but was missing from the documentation.
Signed-off-by Jack Pham <[email protected]>
--- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +3 -0
@@ -17,6 +17,9 @@ properties: - qcom,msm8998-dwc3 - qcom,sc7180-dwc3 - qcom,sdm845-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 - const: qcom,dwc3 reg:
Signature · 1 line
2.24.0