Intel Vision Processing base enabling

index 83aec191555c..5a08e6f216f2 100644
@@ -495,7 +495,7 @@ static int intel_tsens_config_dt(struct intel_tsens_priv *priv)
 
 		ts = devm_kzalloc(&pdev->dev, sizeof(struct intel_tsens),
 				  GFP_KERNEL);
-		if (!ts){
+		if (!ts) {
 			of_node_put(s_node);
 			return -ENOMEM;
 		}

index 7a61c09de261..e9b927a31e22 100644
@@ -61,7 +61,7 @@ enum keembay_thermal_sensor_en {
 
 #define KEEMBAY_SENSOR_BASE_TEMP 27
 
-static int const raw_kmb[] = {
+static const int raw_kmb[] = {
 39956,  -39637, -39319, -39001, -38684,
 
 38367,  -38050, -37734, -37418, -37103,

index 03311dbd579a..44b9408d478e 100644
@@ -361,8 +361,7 @@ int vcm_wait(struct vpumgr_ctx *v, s32 submit_id,
 	rc = wait_for_completion_interruptible_timeout(&vcmd->complete, timeout);
 	if (rc < 0) {
 		goto exit;
-	}
-	else if (rc == 0) {
+	} else if (rc == 0) {
 		rc = -ETIMEDOUT;
 		goto exit;
 	} else {

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index c04b8f44f684..e98a5a4b66a2 100644
@@ -426,7 +426,7 @@ int xlink_ipc_connect(u32 sw_device_id)
 
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_connect);
+EXPORT_SYMBOL_GPL(xlink_ipc_connect);
 
 /*
  * xlink_ipc_write() - platform write interface.

@@ -471,7 +471,7 @@ int xlink_ipc_write(u32 sw_device_id, void *data, size_t * const size,
 
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_write);
+EXPORT_SYMBOL_GPL(xlink_ipc_write);
 
 /*
  * xlink_ipc_read() - platform read interface.

@@ -513,7 +513,7 @@ int xlink_ipc_read(u32 sw_device_id, void *data, size_t * const size,
 	}
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_read);
+EXPORT_SYMBOL_GPL(xlink_ipc_read);
 
 /*
  * xlink_ipc_get_device_list() - platform get device list interface.

@@ -538,7 +538,7 @@ int xlink_ipc_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
 	*num_devices = i;
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_get_device_list);
+EXPORT_SYMBOL_GPL(xlink_ipc_get_device_list);
 
 /*
  * xlink_ipc_get_device_name() - platform get device name interface.

@@ -566,7 +566,7 @@ int xlink_ipc_get_device_name(u32 sw_device_id, char *device_name,
 	strncpy(device_name, xlink_dev->device_name, size);
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_get_device_name);
+EXPORT_SYMBOL_GPL(xlink_ipc_get_device_name);
 
 /*
  * xlink_ipc_get_device_status() - platform get device status interface.

@@ -587,7 +587,7 @@ int xlink_ipc_get_device_status(u32 sw_device_id, u32 *device_status)
 	*device_status = intel_keembay_vpu_status(xlink_dev->vpu_dev);
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_get_device_status);
+EXPORT_SYMBOL_GPL(xlink_ipc_get_device_status);
 
 static void kernel_callback(struct device *dev, enum intel_keembay_vpu_event event)
 {

@@ -619,7 +619,7 @@ int xlink_ipc_register_for_events(u32 sw_device_id,
 	rc = intel_keembay_vpu_register_for_events(xlink_dev->vpu_dev, kernel_callback);
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_register_for_events);
+EXPORT_SYMBOL_GPL(xlink_ipc_register_for_events);
 /*
  * xlink_ipc_unregister_for_events() - platform register for events
  *

@@ -636,7 +636,7 @@ int xlink_ipc_unregister_for_events(u32 sw_device_id)
 	rc = intel_keembay_vpu_unregister_for_events(xlink_dev->vpu_dev);
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_unregister_for_events);
+EXPORT_SYMBOL_GPL(xlink_ipc_unregister_for_events);
 
 /*
  * xlink_ipc_boot_device() - platform boot device interface.

@@ -683,7 +683,7 @@ int xlink_ipc_boot_device(u32 sw_device_id, const char *binary_name)
 	pr_info("VPU was ready.\n");
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_boot_device);
+EXPORT_SYMBOL_GPL(xlink_ipc_boot_device);
 
 /*
  * xlink_ipc_reset_device() - platform reset device interface.

@@ -717,7 +717,7 @@ int xlink_ipc_reset_device(u32 sw_device_id)
 	}
 	return 0;
 }
-EXPORT_SYMBOL(xlink_ipc_reset_device);
+EXPORT_SYMBOL_GPL(xlink_ipc_reset_device);
 
 /*
  * xlink_ipc_open_channel() - platform open channel interface.

@@ -738,7 +738,7 @@ int xlink_ipc_open_channel(u32 sw_device_id, u32 channel)
 						KMB_VPU_IPC_NODE_LEON_MSS, channel);
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_open_channel);
+EXPORT_SYMBOL_GPL(xlink_ipc_open_channel);
 
 /*
  * xlink_ipc_close_channel() - platform close channel interface.

@@ -759,7 +759,7 @@ int xlink_ipc_close_channel(u32 sw_device_id, u32 channel)
 						 KMB_VPU_IPC_NODE_LEON_MSS, channel);
 	return rc;
 }
-EXPORT_SYMBOL(xlink_ipc_close_channel);
+EXPORT_SYMBOL_GPL(xlink_ipc_close_channel);
 
 /*
  * xlink ipc driver functions

index 34b6c268aac5..87b302f87cfd 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_CORE_HEADER_
 #define XPCIE_CORE_HEADER_

index 4ad291ff97c8..5d30c27dd18d 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include <linux/xlink_drv_inf.h>
 

@@ -22,7 +20,7 @@ int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
 
 	return 0;
 }
-EXPORT_SYMBOL(xlink_pcie_get_device_list);
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
 
 int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
 			       size_t name_size)

@@ -33,7 +31,7 @@ int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
 	return intel_xpcie_get_device_name_by_id(sw_device_id,
 						 device_name, name_size);
 }
-EXPORT_SYMBOL(xlink_pcie_get_device_name);
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
 
 int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
 {

@@ -68,19 +66,19 @@ int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
 
 	return 0;
 }
-EXPORT_SYMBOL(xlink_pcie_get_device_status);
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
 
 int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
 {
 	return 0;
 }
-EXPORT_SYMBOL(xlink_pcie_boot_device);
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
 
 int xlink_pcie_connect(u32 sw_device_id)
 {
 	return intel_xpcie_pci_connect_device(sw_device_id);
 }
-EXPORT_SYMBOL(xlink_pcie_connect);
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
 
 int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
 		    u32 timeout)

@@ -90,7 +88,7 @@ int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
 
 	return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
 }
-EXPORT_SYMBOL(xlink_pcie_read);
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
 
 int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
 		     u32 timeout)

@@ -100,13 +98,13 @@ int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
 
 	return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
 }
-EXPORT_SYMBOL(xlink_pcie_write);
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
 
 int xlink_pcie_reset_device(u32 sw_device_id)
 {
 	return intel_xpcie_pci_reset_device(sw_device_id);
 }
-EXPORT_SYMBOL(xlink_pcie_reset_device);
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
 
 int xlink_pcie_register_device_event(u32 sw_device_id,
 				     xlink_device_event event_notif_fn)

@@ -117,10 +115,10 @@ int xlink_pcie_register_device_event(u32 sw_device_id,
 	return intel_xpcie_pci_register_device_event(sw_device_id,
 						     event_notif_fn);
 }
-EXPORT_SYMBOL(xlink_pcie_register_device_event);
+EXPORT_SYMBOL_GPL(xlink_pcie_register_device_event);
 
 int xlink_pcie_unregister_device_event(u32 sw_device_id)
 {
 	return intel_xpcie_pci_unregister_device_event(sw_device_id);
 }
-EXPORT_SYMBOL(xlink_pcie_unregister_device_event);
+EXPORT_SYMBOL_GPL(xlink_pcie_unregister_device_event);

index ec808b0cd72b..d99125f61ba0 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include "util.h"
 

index 908be897a61d..5295783b0437 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_UTIL_HEADER_
 #define XPCIE_UTIL_HEADER_

index d6e06f91ad91..b5cf9242a59a 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_HEADER_
 #define XPCIE_HEADER_

index a343e30d8b45..bfb14c18c24c 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include <linux/of_reserved_mem.h>
 

index 811e5eebb7ab..42978fb0db49 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/wait.h>

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index ad79416476d5..40bf4ff36580 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_EPF_HEADER_
 #define XPCIE_EPF_HEADER_

index 2e20e1490076..3be0492aa57c 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include "pci.h"
 

index fd31ee3c153b..efc9143a2fac 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include "pci.h"
 #include "../common/core.h"

index 0046bff5f604..6a79782b983e 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include <linux/mutex.h>
 #include <linux/pci.h>

index a05dedf36a12..b082bfb73e4f 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_PCI_HEADER_
 #define XPCIE_PCI_HEADER_

index 70a8d8b1f9a8..f097e92b1a99 100644
@@ -1161,7 +1161,7 @@ int intel_keembay_ipc_open_channel(struct device *dev, u8 node_id, u16 chan_id)
 
 	return 0;
 }
-EXPORT_SYMBOL(intel_keembay_ipc_open_channel);
+EXPORT_SYMBOL_GPL(intel_keembay_ipc_open_channel);
 
 /**
  * intel_keembay_ipc_close_channel() - Close an IPC channel.

@@ -1192,7 +1192,7 @@ int intel_keembay_ipc_close_channel(struct device *dev, u8 node_id, u16 chan_id)
 
 	return 0;
 }
-EXPORT_SYMBOL(intel_keembay_ipc_close_channel);
+EXPORT_SYMBOL_GPL(intel_keembay_ipc_close_channel);
 
 /**
  * intel_keembay_ipc_send() - Send data via IPC.

@@ -1242,7 +1242,7 @@ int intel_keembay_ipc_send(struct device *dev, u8 node_id, u16 chan_id,
 	srcu_read_unlock(&link->srcu_sp[chan_id], idx);
 	return rc;
 }
-EXPORT_SYMBOL(intel_keembay_ipc_send);
+EXPORT_SYMBOL_GPL(intel_keembay_ipc_send);
 
 /**
  * intel_keembay_ipc_recv() - Read data via IPC

@@ -1356,7 +1356,7 @@ int intel_keembay_ipc_recv(struct device *dev, u8 node_id, u16 chan_id,
 	srcu_read_unlock(&link->srcu_sp[chan_id], idx);
 	return rc;
 }
-EXPORT_SYMBOL(intel_keembay_ipc_recv);
+EXPORT_SYMBOL_GPL(intel_keembay_ipc_recv);
 
 MODULE_DESCRIPTION("Keem Bay IPC Driver");
 MODULE_AUTHOR("Daniele Alessandrelli <[email protected]>");

index bcf9bb4a225a..31b880195cac 100644
@@ -1463,7 +1463,7 @@ int intel_keembay_vpu_ipc_open_channel(struct device *dev, u8 node_id,
 	return intel_keembay_ipc_open_channel(vpu_dev->ipc_dev, node_id,
 					      chan_id);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_ipc_open_channel);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_ipc_open_channel);
 
 /**
  * intel_keembay_vpu_ipc_close_channel() - Close an IPC channel.

@@ -1487,7 +1487,7 @@ int intel_keembay_vpu_ipc_close_channel(struct device *dev, u8 node_id,
 	return intel_keembay_ipc_close_channel(vpu_dev->ipc_dev,
 					       node_id, chan_id);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_ipc_close_channel);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_ipc_close_channel);
 
 /**
  * intel_keembay_vpu_ipc_send() - Send data via IPC.

@@ -1512,7 +1512,7 @@ int intel_keembay_vpu_ipc_send(struct device *dev, u8 node_id, u16 chan_id,
 	return intel_keembay_ipc_send(vpu_dev->ipc_dev, node_id, chan_id,
 				      vpu_addr, size);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_ipc_send);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_ipc_send);
 
 /**
  * intel_keembay_vpu_ipc_recv() - Read data via IPC

@@ -1540,7 +1540,7 @@ int intel_keembay_vpu_ipc_recv(struct device *dev, u8 node_id, u16 chan_id,
 	return intel_keembay_ipc_recv(vpu_dev->ipc_dev, node_id, chan_id,
 				      vpu_addr, size, timeout);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_ipc_recv);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_ipc_recv);
 
 /**
  * intel_keembay_vpu_startup() - Boot the VPU

@@ -1582,7 +1582,7 @@ int intel_keembay_vpu_startup(struct device *dev, const char *firmware_name)
 
 	return do_boot_sequence(vpu_dev);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_startup);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_startup);
 
 /**
  * intel_keembay_vpu_reset() - Reset the VPU

@@ -1610,7 +1610,7 @@ int intel_keembay_vpu_reset(struct device *dev)
 
 	return do_boot_sequence(vpu_dev);
 }
-EXPORT_SYMBOL(intel_keembay_vpu_reset);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_reset);
 
 /**
  * intel_keembay_vpu_stop() - Stop the VPU

@@ -1659,7 +1659,7 @@ int intel_keembay_vpu_stop(struct device *dev)
 
 	return rc;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_stop);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_stop);
 
 /**
  * intel_keembay_vpu_status() - Get the VPU state.

@@ -1678,7 +1678,7 @@ enum intel_keembay_vpu_state intel_keembay_vpu_status(struct device *dev)
 
 	return vpu_dev->state;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_status);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_status);
 
 /**
  * intel_keembay_vpu_get_wdt_count() - Get the WDT count

@@ -1709,7 +1709,7 @@ int intel_keembay_vpu_get_wdt_count(struct device *dev,
 	}
 	return rc;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_get_wdt_count);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_get_wdt_count);
 
 /**
  * intel_keembay_vpu_wait_for_ready() - Sleep until VPU is READY

@@ -1754,7 +1754,7 @@ int intel_keembay_vpu_wait_for_ready(struct device *dev, u32 timeout)
 
 	return rc;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_wait_for_ready);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_wait_for_ready);
 
 /**
  * intel_keembay_vpu_register_for_events() - Register callback for event notification

@@ -1784,7 +1784,7 @@ int intel_keembay_vpu_register_for_events(struct device *dev,
 
 	return 0;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_register_for_events);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_register_for_events);
 
 /**
  * intel_keembay_vpu_unregister_for_events() - Unregister callback for event notification

@@ -1803,7 +1803,7 @@ int intel_keembay_vpu_unregister_for_events(struct device *dev)
 
 	return 0;
 }
-EXPORT_SYMBOL(intel_keembay_vpu_unregister_for_events);
+EXPORT_SYMBOL_GPL(intel_keembay_vpu_unregister_for_events);
 
 /* Probe() function for the VPU IPC platform driver. */
 static int keembay_vpu_ipc_probe(struct platform_device *pdev)

index 5ca0ae1ae2e3..f20f69bd879a 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef _XLINK_DRV_INF_H_
 #define _XLINK_DRV_INF_H_

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new file mode 100644
index 000000000000..ac7748d1595f
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Keem Bay IPC Linux Kernel API
+ *
+ * Copyright (C) 2018-2020 Intel Corporation
+ */
+
+#ifndef __KEEMBAY_IPC_H
+#define __KEEMBAY_IPC_H
+
+#include <linux/types.h>
+
+/* The possible node IDs. */
+enum {
+	KMB_IPC_NODE_CPU = 0,
+	KMB_IPC_NODE_LEON_MSS,
+};
+
+int intel_keembay_ipc_open_channel(struct device *dev, u8 node_id, u16 chan_id);
+
+int intel_keembay_ipc_close_channel(struct device *dev, u8 node_id,
+				    u16 chan_id);
+
+int intel_keembay_ipc_send(struct device *dev, u8 node_id, u16 chan_id,
+			   u32 vpu_addr, size_t size);
+
+int intel_keembay_ipc_recv(struct device *dev, u8 node_id, u16 chan_id,
+			   u32 *vpu_addr, size_t *size, u32 timeout);
+
+#endif /* __KEEMBAY_IPC_H */

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new file mode 100644
index 000000000000..ac7748d1595f
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Keem Bay IPC Linux Kernel API
+ *
+ * Copyright (C) 2018-2020 Intel Corporation
+ */
+
+#ifndef __KEEMBAY_IPC_H
+#define __KEEMBAY_IPC_H
+
+#include <linux/types.h>
+
+/* The possible node IDs. */
+enum {
+	KMB_IPC_NODE_CPU = 0,
+	KMB_IPC_NODE_LEON_MSS,
+};
+
+int intel_keembay_ipc_open_channel(struct device *dev, u8 node_id, u16 chan_id);
+
+int intel_keembay_ipc_close_channel(struct device *dev, u8 node_id,
+				    u16 chan_id);
+
+int intel_keembay_ipc_send(struct device *dev, u8 node_id, u16 chan_id,
+			   u32 vpu_addr, size_t size);
+
+int intel_keembay_ipc_recv(struct device *dev, u8 node_id, u16 chan_id,
+			   u32 *vpu_addr, size_t *size, u32 timeout);
+
+#endif /* __KEEMBAY_IPC_H */

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new file mode 100644
index 000000000000..a60cd43fe555
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#ifndef XPCIE_EPF_HEADER_
+#define XPCIE_EPF_HEADER_
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+#include "xpcie.h"
+
+#define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
+#define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"
+
+#define KEEMBAY_XPCIE_STEPPING_MAXLEN 8
+
+struct xpcie_epf {
+	struct pci_epf *epf;
+	void *vaddr[BAR_5 + 1];
+	enum pci_barno comm_bar;
+	enum pci_barno bar4;
+	const struct pci_epc_features *epc_features;
+	struct xpcie xpcie;
+	int irq;
+	int irq_dma;
+	int irq_err;
+	void __iomem *apb_base;
+	void __iomem *dma_base;
+	void __iomem *dbi_base;
+	char stepping[KEEMBAY_XPCIE_STEPPING_MAXLEN];
+};
+
+#endif /* XPCIE_EPF_HEADER_ */

new file mode 100644
index 000000000000..0745e6dfee10
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*****************************************************************************
+ *
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ ****************************************************************************/
+
+#ifndef XPCIE_HEADER_
+#define XPCIE_HEADER_
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci_ids.h>
+
+#ifndef PCI_DEVICE_ID_INTEL_KEEMBAY
+#define PCI_DEVICE_ID_INTEL_KEEMBAY 0x6240
+#endif
+
+#define XPCIE_IO_COMM_SIZE SZ_16K
+#define XPCIE_MMIO_OFFSET SZ_4K
+
+/* MMIO layout and offsets shared between device and host */
+struct xpcie_mmio {
+	u8 legacy_a0;
+} __packed;
+
+#define XPCIE_MMIO_LEGACY_A0	(offsetof(struct xpcie_mmio, legacy_a0))
+
+struct xpcie {
+	u32 status;
+	bool legacy_a0;
+	void *mmio;
+	void *bar4;
+};
+
+#endif /* XPCIE_HEADER_ */

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new file mode 100644
index 000000000000..a60cd43fe555
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#ifndef XPCIE_EPF_HEADER_
+#define XPCIE_EPF_HEADER_
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+#include "xpcie.h"
+
+#define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
+#define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"
+
+#define KEEMBAY_XPCIE_STEPPING_MAXLEN 8
+
+struct xpcie_epf {
+	struct pci_epf *epf;
+	void *vaddr[BAR_5 + 1];
+	enum pci_barno comm_bar;
+	enum pci_barno bar4;
+	const struct pci_epc_features *epc_features;
+	struct xpcie xpcie;
+	int irq;
+	int irq_dma;
+	int irq_err;
+	void __iomem *apb_base;
+	void __iomem *dma_base;
+	void __iomem *dbi_base;
+	char stepping[KEEMBAY_XPCIE_STEPPING_MAXLEN];
+};
+
+#endif /* XPCIE_EPF_HEADER_ */

new file mode 100644
index 000000000000..0745e6dfee10
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*****************************************************************************
+ *
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ ****************************************************************************/
+
+#ifndef XPCIE_HEADER_
+#define XPCIE_HEADER_
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci_ids.h>
+
+#ifndef PCI_DEVICE_ID_INTEL_KEEMBAY
+#define PCI_DEVICE_ID_INTEL_KEEMBAY 0x6240
+#endif
+
+#define XPCIE_IO_COMM_SIZE SZ_16K
+#define XPCIE_MMIO_OFFSET SZ_4K
+
+/* MMIO layout and offsets shared between device and host */
+struct xpcie_mmio {
+	u8 legacy_a0;
+} __packed;
+
+#define XPCIE_MMIO_LEGACY_A0	(offsetof(struct xpcie_mmio, legacy_a0))
+
+struct xpcie {
+	u32 status;
+	bool legacy_a0;
+	void *mmio;
+	void *bar4;
+};
+
+#endif /* XPCIE_HEADER_ */

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index 0234756e89ae..7019aecd6a81 100644
@@ -43,6 +43,8 @@ static irqreturn_t intel_xpcie_err_interrupt(int irq, void *args)
 
 	xpcie_epf = container_of(xpcie, struct xpcie_epf, xpcie);
 	val = ioread32(xpcie_epf->apb_base + PCIE_REGS_PCIE_ERR_INTR_FLAGS);
+	if (val & LINK_REQ_RST_FLG)
+		intel_xpcie_ep_dma_reset(xpcie_epf->epf);
 
 	iowrite32(val, xpcie_epf->apb_base + PCIE_REGS_PCIE_ERR_INTR_FLAGS);
 

@@ -285,8 +287,17 @@ static int intel_xpcie_epf_bind(struct pci_epf *epf)
 		goto err_cleanup_bars;
 	}
 
+	ret = intel_xpcie_ep_dma_init(epf);
+	if (ret) {
+		dev_err(&epf->dev, "DMA initialization failed\n");
+		goto err_free_err_irq;
+	}
+
 	return 0;
 
+err_free_err_irq:
+	free_irq(xpcie_epf->irq_err, &xpcie_epf->xpcie);
+
 err_cleanup_bars:
 	intel_xpcie_cleanup_bars(epf);
 

@@ -295,11 +306,9 @@ static int intel_xpcie_epf_bind(struct pci_epf *epf)
 
 static void intel_xpcie_epf_unbind(struct pci_epf *epf)
 {
-	struct xpcie_epf *xpcie_epf = epf_get_drvdata(epf);
 	struct pci_epc *epc = epf->epc;
 
-	free_irq(xpcie_epf->irq, &xpcie_epf->xpcie);
-	free_irq(xpcie_epf->irq_err, &xpcie_epf->xpcie);
+	intel_xpcie_ep_dma_uninit(epf);
 
 	pci_epc_stop(epc);
 

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index 0234756e89ae..7019aecd6a81 100644
@@ -43,6 +43,8 @@ static irqreturn_t intel_xpcie_err_interrupt(int irq, void *args)
 
 	xpcie_epf = container_of(xpcie, struct xpcie_epf, xpcie);
 	val = ioread32(xpcie_epf->apb_base + PCIE_REGS_PCIE_ERR_INTR_FLAGS);
+	if (val & LINK_REQ_RST_FLG)
+		intel_xpcie_ep_dma_reset(xpcie_epf->epf);
 
 	iowrite32(val, xpcie_epf->apb_base + PCIE_REGS_PCIE_ERR_INTR_FLAGS);
 

@@ -285,8 +287,17 @@ static int intel_xpcie_epf_bind(struct pci_epf *epf)
 		goto err_cleanup_bars;
 	}
 
+	ret = intel_xpcie_ep_dma_init(epf);
+	if (ret) {
+		dev_err(&epf->dev, "DMA initialization failed\n");
+		goto err_free_err_irq;
+	}
+
 	return 0;
 
+err_free_err_irq:
+	free_irq(xpcie_epf->irq_err, &xpcie_epf->xpcie);
+
 err_cleanup_bars:
 	intel_xpcie_cleanup_bars(epf);
 

@@ -295,11 +306,9 @@ static int intel_xpcie_epf_bind(struct pci_epf *epf)
 
 static void intel_xpcie_epf_unbind(struct pci_epf *epf)
 {
-	struct xpcie_epf *xpcie_epf = epf_get_drvdata(epf);
 	struct pci_epc *epc = epf->epc;
 
-	free_irq(xpcie_epf->irq, &xpcie_epf->xpcie);
-	free_irq(xpcie_epf->irq_err, &xpcie_epf->xpcie);
+	intel_xpcie_ep_dma_uninit(epf);
 
 	pci_epc_stop(epc);
 

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index 82410404d54e..7220cead0973 100644
@@ -12,6 +12,7 @@
 #include <linux/pci-epf.h>
 
 #include "xpcie.h"
+#include "util.h"
 
 #define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
 #define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"

@@ -24,6 +25,7 @@
 #define XPCIE_NUM_RX_DESCS	(64)
 
 extern bool dma_ll_mode;
+extern u32 xlink_sw_id;
 
 struct xpcie_dma_ll_desc {
 	u32 dma_ch_control1;

@@ -65,14 +67,35 @@ struct xpcie_epf {
 	void __iomem *dbi_base;
 	char stepping[KEEMBAY_XPCIE_STEPPING_MAXLEN];
 
+	irq_handler_t			core_irq_callback;
+	dma_addr_t			tx_phys;
+	void				*tx_virt;
+	size_t				tx_size;
+
 	struct xpcie_dma_ll_desc_buf	tx_desc_buf[DMA_CHAN_NUM];
 	struct xpcie_dma_ll_desc_buf	rx_desc_buf[DMA_CHAN_NUM];
 };
 
+static inline struct device *xpcie_to_dev(struct xpcie *xpcie)
+{
+	struct xpcie_epf *xpcie_epf = container_of(xpcie,
+						   struct xpcie_epf, xpcie);
+
+	return &xpcie_epf->epf->dev;
+}
+
 int intel_xpcie_ep_dma_init(struct pci_epf *epf);
 int intel_xpcie_ep_dma_uninit(struct pci_epf *epf);
 int intel_xpcie_ep_dma_reset(struct pci_epf *epf);
 int intel_xpcie_ep_dma_read_ll(struct pci_epf *epf, int chan, int descs_num);
 int intel_xpcie_ep_dma_write_ll(struct pci_epf *epf, int chan, int descs_num);
 
+void intel_xpcie_register_host_irq(struct xpcie *xpcie,
+				   irq_handler_t func);
+int intel_xpcie_raise_irq(struct xpcie *xpcie,
+			  enum xpcie_doorbell_type type);
+int intel_xpcie_copy_from_host_ll(struct xpcie *xpcie,
+				  int chan, int descs_num);
+int intel_xpcie_copy_to_host_ll(struct xpcie *xpcie,
+				int chan, int descs_num);
 #endif /* XPCIE_EPF_HEADER_ */

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index 82410404d54e..7220cead0973 100644
@@ -12,6 +12,7 @@
 #include <linux/pci-epf.h>
 
 #include "xpcie.h"
+#include "util.h"
 
 #define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
 #define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"

@@ -24,6 +25,7 @@
 #define XPCIE_NUM_RX_DESCS	(64)
 
 extern bool dma_ll_mode;
+extern u32 xlink_sw_id;
 
 struct xpcie_dma_ll_desc {
 	u32 dma_ch_control1;

@@ -65,14 +67,35 @@ struct xpcie_epf {
 	void __iomem *dbi_base;
 	char stepping[KEEMBAY_XPCIE_STEPPING_MAXLEN];
 
+	irq_handler_t			core_irq_callback;
+	dma_addr_t			tx_phys;
+	void				*tx_virt;
+	size_t				tx_size;
+
 	struct xpcie_dma_ll_desc_buf	tx_desc_buf[DMA_CHAN_NUM];
 	struct xpcie_dma_ll_desc_buf	rx_desc_buf[DMA_CHAN_NUM];
 };
 
+static inline struct device *xpcie_to_dev(struct xpcie *xpcie)
+{
+	struct xpcie_epf *xpcie_epf = container_of(xpcie,
+						   struct xpcie_epf, xpcie);
+
+	return &xpcie_epf->epf->dev;
+}
+
 int intel_xpcie_ep_dma_init(struct pci_epf *epf);
 int intel_xpcie_ep_dma_uninit(struct pci_epf *epf);
 int intel_xpcie_ep_dma_reset(struct pci_epf *epf);
 int intel_xpcie_ep_dma_read_ll(struct pci_epf *epf, int chan, int descs_num);
 int intel_xpcie_ep_dma_write_ll(struct pci_epf *epf, int chan, int descs_num);
 
+void intel_xpcie_register_host_irq(struct xpcie *xpcie,
+				   irq_handler_t func);
+int intel_xpcie_raise_irq(struct xpcie *xpcie,
+			  enum xpcie_doorbell_type type);
+int intel_xpcie_copy_from_host_ll(struct xpcie *xpcie,
+				  int chan, int descs_num);
+int intel_xpcie_copy_to_host_ll(struct xpcie *xpcie,
+				int chan, int descs_num);
 #endif /* XPCIE_EPF_HEADER_ */

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similarity index 96%
rename from drivers/misc/xlink-pcie/local_host/core.h
rename to drivers/misc/xlink-pcie/common/core.h
index 84985ef41a64..656b5e2dbfae 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_CORE_HEADER_
 #define XPCIE_CORE_HEADER_

similarity index 97%
rename from drivers/misc/xlink-pcie/local_host/util.c
rename to drivers/misc/xlink-pcie/common/util.c
index ec808b0cd72b..d99125f61ba0 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include "util.h"
 

similarity index 91%
rename from drivers/misc/xlink-pcie/local_host/util.h
rename to drivers/misc/xlink-pcie/common/util.h
index 908be897a61d..5295783b0437 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_UTIL_HEADER_
 #define XPCIE_UTIL_HEADER_

similarity index 92%
rename from drivers/misc/xlink-pcie/local_host/xpcie.h
rename to drivers/misc/xlink-pcie/common/xpcie.h
index 8a559617daba..48529eb49be0 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_HEADER_
 #define XPCIE_HEADER_

index c67ce2c3067d..2c4e29bce7f7 100644
@@ -8,8 +8,8 @@
 #include <linux/of_reserved_mem.h>
 
 #include "epf.h"
-#include "core.h"
-#include "util.h"
+#include "../common/core.h"
+#include "../common/util.h"
 
 static struct xpcie *global_xpcie;
 

index 7220cead0973..40bf4ff36580 100644
@@ -11,8 +11,8 @@
 #include <linux/pci-epc.h>
 #include <linux/pci-epf.h>
 
-#include "xpcie.h"
-#include "util.h"
+#include "../common/xpcie.h"
+#include "../common/util.h"
 
 #define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
 #define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"

similarity index 96%
rename from drivers/misc/xlink-pcie/local_host/core.h
rename to drivers/misc/xlink-pcie/common/core.h
index 84985ef41a64..656b5e2dbfae 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_CORE_HEADER_
 #define XPCIE_CORE_HEADER_

similarity index 97%
rename from drivers/misc/xlink-pcie/local_host/util.c
rename to drivers/misc/xlink-pcie/common/util.c
index ec808b0cd72b..d99125f61ba0 100644
@@ -1,11 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #include "util.h"
 

similarity index 91%
rename from drivers/misc/xlink-pcie/local_host/util.h
rename to drivers/misc/xlink-pcie/common/util.h
index 908be897a61d..5295783b0437 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_UTIL_HEADER_
 #define XPCIE_UTIL_HEADER_

similarity index 92%
rename from drivers/misc/xlink-pcie/local_host/xpcie.h
rename to drivers/misc/xlink-pcie/common/xpcie.h
index 8a559617daba..48529eb49be0 100644
@@ -1,11 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*****************************************************************************
- *
+/*
  * Intel Keem Bay XLink PCIe Driver
  *
- * Copyright (C) 2020 Intel Corporation
- *
- ****************************************************************************/
+ * Copyright (C) 2021 Intel Corporation
+ */
 
 #ifndef XPCIE_HEADER_
 #define XPCIE_HEADER_

index c67ce2c3067d..2c4e29bce7f7 100644
@@ -8,8 +8,8 @@
 #include <linux/of_reserved_mem.h>
 
 #include "epf.h"
-#include "core.h"
-#include "util.h"
+#include "../common/core.h"
+#include "../common/util.h"
 
 static struct xpcie *global_xpcie;
 

index 7220cead0973..40bf4ff36580 100644
@@ -11,8 +11,8 @@
 #include <linux/pci-epc.h>
 #include <linux/pci-epf.h>
 
-#include "xpcie.h"
-#include "util.h"
+#include "../common/xpcie.h"
+#include "../common/util.h"
 
 #define XPCIE_DRIVER_NAME "mxlk_pcie_epf"
 #define XPCIE_DRIVER_DESC "Intel(R) xLink PCIe endpoint function driver"

index 48529eb49be0..b5cf9242a59a 100644
@@ -69,6 +69,7 @@ struct xpcie_mmio {
 struct xpcie {
 	u32 status;
 	bool legacy_a0;
+	void *bar0;
 	void *mmio;
 	void *bar4;
 

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index 48529eb49be0..b5cf9242a59a 100644
@@ -69,6 +69,7 @@ struct xpcie_mmio {
 struct xpcie {
 	u32 status;
 	bool legacy_a0;
+	void *bar0;
 	void *mmio;
 	void *bar4;
 

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index 656b5e2dbfae..f43c175b7a48 100644
@@ -8,15 +8,11 @@
 #ifndef XPCIE_CORE_HEADER_
 #define XPCIE_CORE_HEADER_
 
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-#include <linux/mempool.h>
 #include <linux/dma-mapping.h>
-#include <linux/cache.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
 #include <linux/wait.h>
+#include <linux/workqueue.h>
 
 #include <linux/xlink_drv_inf.h>
 

@@ -62,6 +58,7 @@ struct xpcie_buf_desc {
 struct xpcie_stream {
 	size_t frag;
 	struct xpcie_pipe pipe;
+	struct xpcie_buf_desc **ddr;
 };
 
 struct xpcie_list {

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index 656b5e2dbfae..f43c175b7a48 100644
@@ -8,15 +8,11 @@
 #ifndef XPCIE_CORE_HEADER_
 #define XPCIE_CORE_HEADER_
 
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/workqueue.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-#include <linux/mempool.h>
 #include <linux/dma-mapping.h>
-#include <linux/cache.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
 #include <linux/wait.h>
+#include <linux/workqueue.h>
 
 #include <linux/xlink_drv_inf.h>
 

@@ -62,6 +58,7 @@ struct xpcie_buf_desc {
 struct xpcie_stream {
 	size_t frag;
 	struct xpcie_pipe pipe;
+	struct xpcie_buf_desc **ddr;
 };
 
 struct xpcie_list {

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new file mode 100644
index 000000000000..fcc69a940a4c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include <linux/xlink_drv_inf.h>
+
+#include "core.h"
+#include "xpcie.h"
+
+/* Define xpcie driver interface API */
+int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
+{
+	if (!sw_device_id_list || !num_devices)
+		return -EINVAL;
+
+	*num_devices = intel_xpcie_get_device_num(sw_device_id_list);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
+
+int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
+			       size_t name_size)
+{
+	if (!device_name)
+		return -EINVAL;
+
+	return intel_xpcie_get_device_name_by_id(sw_device_id,
+						 device_name, name_size);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
+
+int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
+{
+	u32 status;
+	int rc;
+
+	if (!device_status)
+		return -EINVAL;
+
+	rc = intel_xpcie_get_device_status_by_id(sw_device_id, &status);
+	if (rc)
+		return rc;
+
+	switch (status) {
+	case XPCIE_STATUS_READY:
+	case XPCIE_STATUS_RUN:
+		*device_status = _XLINK_DEV_READY;
+		break;
+	case XPCIE_STATUS_ERROR:
+		*device_status = _XLINK_DEV_ERROR;
+		break;
+	case XPCIE_STATUS_RECOVERY:
+		*device_status = _XLINK_DEV_RECOVERY;
+		break;
+	case XPCIE_STATUS_OFF:
+		*device_status = _XLINK_DEV_OFF;
+		break;
+	default:
+		*device_status = _XLINK_DEV_BUSY;
+		break;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
+
+int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
+
+int xlink_pcie_connect(u32 sw_device_id)
+{
+	return intel_xpcie_pci_connect_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
+
+int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
+		    u32 timeout)
+{
+	if (!data || !size)
+		return -EINVAL;
+
+	return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
+
+int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
+		     u32 timeout)
+{
+	if (!data || !size)
+		return -EINVAL;
+
+	return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
+
+int xlink_pcie_reset_device(u32 sw_device_id)
+{
+	return intel_xpcie_pci_reset_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);

index f43c175b7a48..87b302f87cfd 100644
@@ -239,4 +239,7 @@ int intel_xpcie_pci_connect_device(u32 id);
 int intel_xpcie_pci_read(u32 id, void *data, size_t *size, u32 timeout);
 int intel_xpcie_pci_write(u32 id, void *data, size_t *size, u32 timeout);
 int intel_xpcie_pci_reset_device(u32 id);
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+					  xlink_device_event event_notif_fn);
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id);
 #endif /* XPCIE_CORE_HEADER_ */

index fcc69a940a4c..5d30c27dd18d 100644
@@ -105,3 +105,20 @@ int xlink_pcie_reset_device(u32 sw_device_id)
 	return intel_xpcie_pci_reset_device(sw_device_id);
 }
 EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
+
+int xlink_pcie_register_device_event(u32 sw_device_id,
+				     xlink_device_event event_notif_fn)
+{
+	if (!event_notif_fn)
+		return -EINVAL;
+
+	return intel_xpcie_pci_register_device_event(sw_device_id,
+						     event_notif_fn);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_register_device_event);
+
+int xlink_pcie_unregister_device_event(u32 sw_device_id)
+{
+	return intel_xpcie_pci_unregister_device_event(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_unregister_device_event);

index 2c4e29bce7f7..bfb14c18c24c 100644
@@ -804,3 +804,14 @@ int intel_xpcie_pci_reset_device(u32 id)
 {
 	return 0;
 }
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+					  xlink_device_event event_notif_fn)
+{
+	return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+	return 0;
+}

index ed1a431ed5d4..efc9143a2fac 100644
@@ -53,6 +53,8 @@ static int intel_xpcie_probe(struct pci_dev *pdev,
 	if (new_device)
 		intel_xpcie_list_add_device(xdev);
 
+	intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_CONNECTED);
+
 	return ret;
 }
 

@@ -62,6 +64,7 @@ static void intel_xpcie_remove(struct pci_dev *pdev)
 
 	if (xdev) {
 		intel_xpcie_pci_cleanup(xdev);
+		intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_DISCONNECTED);
 		intel_xpcie_remove_device(xdev);
 	}
 }

index 71cbe779d1bc..6a79782b983e 100644
@@ -6,6 +6,7 @@
  */
 
 #include <linux/mutex.h>
+#include <linux/pci.h>
 #include <linux/sched.h>
 #include <linux/wait.h>
 #include <linux/workqueue.h>

@@ -485,3 +486,38 @@ int intel_xpcie_pci_reset_device(u32 id)
 
 	return intel_xpcie_pci_prepare_dev_reset(xdev, true);
 }
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+					  xlink_device_event event_notif_fn)
+{
+	struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+	if (!xdev)
+		return -ENOMEM;
+
+	xdev->event_fn = event_notif_fn;
+
+	return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+	struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+	if (!xdev)
+		return -ENOMEM;
+
+	xdev->event_fn = NULL;
+
+	return 0;
+}
+
+void intel_xpcie_pci_notify_event(struct xpcie_dev *xdev,
+				  enum xlink_device_event_type event_type)
+{
+	if (event_type >= NUM_EVENT_TYPE)
+		return;
+
+	if (xdev->event_fn)
+		xdev->event_fn(xdev->devid, event_type);
+}

index bd6b01cc58b8..b082bfb73e4f 100644
@@ -36,6 +36,7 @@ struct xpcie_dev {
 	irq_handler_t core_irq_callback;
 
 	struct xpcie xpcie;
+	xlink_device_event event_fn;
 };
 
 static inline struct device *xpcie_to_dev(struct xpcie *xpcie)

@@ -58,5 +59,7 @@ struct xpcie_dev *intel_xpcie_create_device(u32 sw_device_id,
 void intel_xpcie_remove_device(struct xpcie_dev *xdev);
 void intel_xpcie_list_add_device(struct xpcie_dev *xdev);
 void intel_xpcie_list_del_device(struct xpcie_dev *xdev);
+void intel_xpcie_pci_notify_event(struct xpcie_dev *xdev,
+				  enum xlink_device_event_type event_type);
 
 #endif /* XPCIE_PCI_HEADER_ */

index 8ffbaafecc88..f20f69bd879a 100644
@@ -42,6 +42,15 @@ enum _xlink_device_status {
 	_XLINK_DEV_READY
 };
 
+enum xlink_device_event_type {
+	NOTIFY_DEVICE_DISCONNECTED,
+	NOTIFY_DEVICE_CONNECTED,
+	NUM_EVENT_TYPE
+};
+
+typedef int (*xlink_device_event)(u32 sw_device_id,
+				  enum xlink_device_event_type event_type);
+
 int xlink_pcie_get_device_list(u32 *sw_device_id_list,
 			       u32 *num_devices);
 int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,

@@ -55,4 +64,7 @@ int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
 int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
 		     u32 timeout);
 int xlink_pcie_reset_device(u32 sw_device_id);
+int xlink_pcie_register_device_event(u32 sw_device_id,
+				     xlink_device_event event_notif_fn);
+int xlink_pcie_unregister_device_event(u32 sw_device_id);
 #endif

new file mode 100644
index 000000000000..fcc69a940a4c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include <linux/xlink_drv_inf.h>
+
+#include "core.h"
+#include "xpcie.h"
+
+/* Define xpcie driver interface API */
+int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
+{
+	if (!sw_device_id_list || !num_devices)
+		return -EINVAL;
+
+	*num_devices = intel_xpcie_get_device_num(sw_device_id_list);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
+
+int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
+			       size_t name_size)
+{
+	if (!device_name)
+		return -EINVAL;
+
+	return intel_xpcie_get_device_name_by_id(sw_device_id,
+						 device_name, name_size);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
+
+int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
+{
+	u32 status;
+	int rc;
+
+	if (!device_status)
+		return -EINVAL;
+
+	rc = intel_xpcie_get_device_status_by_id(sw_device_id, &status);
+	if (rc)
+		return rc;
+
+	switch (status) {
+	case XPCIE_STATUS_READY:
+	case XPCIE_STATUS_RUN:
+		*device_status = _XLINK_DEV_READY;
+		break;
+	case XPCIE_STATUS_ERROR:
+		*device_status = _XLINK_DEV_ERROR;
+		break;
+	case XPCIE_STATUS_RECOVERY:
+		*device_status = _XLINK_DEV_RECOVERY;
+		break;
+	case XPCIE_STATUS_OFF:
+		*device_status = _XLINK_DEV_OFF;
+		break;
+	default:
+		*device_status = _XLINK_DEV_BUSY;
+		break;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
+
+int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
+
+int xlink_pcie_connect(u32 sw_device_id)
+{
+	return intel_xpcie_pci_connect_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
+
+int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
+		    u32 timeout)
+{
+	if (!data || !size)
+		return -EINVAL;
+
+	return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
+
+int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
+		     u32 timeout)
+{
+	if (!data || !size)
+		return -EINVAL;
+
+	return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
+
+int xlink_pcie_reset_device(u32 sw_device_id)
+{
+	return intel_xpcie_pci_reset_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);