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ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL

PATCH RESEND Applied Alexandre Belloni 3 participants 3 messages Feb 3, 2021

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Device tree bindings Arm/LPC32XX SoC support
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Alexandre Belloni

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PATCH RESEND v2 1/1 ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL

This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.

The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL.

Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI).

Signed-off-by Alexandre Belloni <[email protected]>
Tested-by Gregory CLEMENT <[email protected]>

---
Arnd,

This is a very important fix that was sent back in may and october 2019 without any reply from the maintainers, please consider applying it so it can be backported on v5.10.

 arch/arm/boot/dts/lpc32xx.dtsi | 3 ---
 1 file changed, 3 deletions(-)
arch/arm/boot/dts/lpc32xx.dtsi +0 -3
index 3a5cfb0ddb20..c87066d6c995 100644
@@ -326,9 +326,6 @@ clk: clock-controller@0 {
 
 					clocks = <&xtal_32k>, <&xtal>;
 					clock-names = "xtal_32k", "xtal";
-
-					assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
-					assigned-clock-rates = <208000000>;
 				};
 			};
Signature · 1 line
2.29.2
CI Applied
#1 lore raw
This patch was applied to soc/soc.git (refs/heads/arm/fixes):

Hello:

This patch was applied to soc/soc.git (refs/heads/arm/fixes):

Quoted 9 lines · On Wed, 3 Feb 2021 10:03:20 +0100 you wrote:

This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.

The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL.

[...]

Here is the summary with links:
- [RESEND,v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL

    https://git.kernel.org/soc/soc/c/5638159f6d93

You are awesome, thank you!
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Applied
#2 lore raw
In reply to Alexandre Belloni

From: Arnd Bergmann <[email protected]>

Quoted 9 lines · Alexandre Belloni

This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7.

The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL.

[...]

Applied to arm/fixes, thanks!

[1/1] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL

      commit: 5638159f6d93b99ec9743ac7f65563fca3cf413d

       Arnd