dt-bindings: usb: convert rockchip,dwc3.txt to yaml

In the past Rockchip dwc3 usb nodes were manually checked. With the conversion of snps,dwc3.yaml as common document we now can convert rockchip,dwc3.txt to yaml as well. Remove node wrapper.

Added properties for rk3399 are:
power-domains
resets
reset-names

Signed-off-by Johan Jonker <[email protected]>

---
 .../devicetree/bindings/usb/rockchip,dwc3.txt      |  56 -----------
 .../devicetree/bindings/usb/rockchip,dwc3.yaml     | 103 +++++++++++++++++++++
 2 files changed, 103 insertions(+), 56 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml

Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted +0 -56

deleted file mode 100644
index 945204932..000000000
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks:	A list of phandle + clock-specifier pairs for the
-		clocks listed in clock-names
-- clock-names:	Should contain the following:
-  "ref_clk"	Controller reference clk, have to be 24 MHz
-  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
-  "bus_clk"	Master/Core clock, have to be >= 62.5 MHz for SS
-		operation and >= 30MHz for HS operation
-  "grf_clk"	Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
-Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt     - Type-C PHY
-
-Example device nodes:
-
-	usbdrd3_0: usb@fe800000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
-			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_0: dwc3@fe800000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe800000 0x0 0x100000>;
-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};
-
-	usbdrd3_1: usb@fe900000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
-			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_1: dwc3@fe900000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe900000 0x0 0x100000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +12 -0

new file mode 100644
index 000000000..fdf9497bc
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Heiko Stuebner <[email protected]>
+
+description:

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +69 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - rockchip,rk3399-dwc3
+      - const: snps,dwc3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description:
+          Controller reference clock, must to be 24 MHz
+      - description:
+          Controller suspend clock, must to be 24 MHz or 32 KHz
+      - description:
+          Master/Core clock, must to be >= 62.5 MHz for SS
+          operation and >= 30MHz for HS operation
+      - description:
+          Controller aclk_usb3_rksoc_axi_perf clock
+      - description:
+          Controller aclk_usb3 clock
+      - description:
+          Controller grf clock
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: suspend_clk
+      - const: bus_clk
+      - const: aclk_usb3_rksoc_axi_perf
+      - const: aclk_usb3
+      - const: grf_clk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: usb3-otg
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3399-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      usbdrd3_0: usb@fe800000 {
+        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+        reg = <0x0 0xfe800000 0x0 0x100000>;

In the past Rockchip dwc3 usb nodes were manually checked. With the conversion of snps,dwc3.yaml as common document we now can convert rockchip,dwc3.txt to yaml as well. Remove node wrapper.

Added properties for rk3399 are:
power-domains
resets
reset-names

Signed-off-by Johan Jonker <[email protected]>

---
  .../devicetree/bindings/usb/rockchip,dwc3.txt      |  56 -----------
  .../devicetree/bindings/usb/rockchip,dwc3.yaml     | 103 +++++++++++++++++++++
  2 files changed, 103 insertions(+), 56 deletions(-)

delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml

Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted +0 -56

deleted file mode 100644
index 945204932..000000000
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks:	A list of phandle + clock-specifier pairs for the
-		clocks listed in clock-names
-- clock-names:	Should contain the following:
-  "ref_clk"	Controller reference clk, have to be 24 MHz
-  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
-  "bus_clk"	Master/Core clock, have to be >= 62.5 MHz for SS
-		operation and >= 30MHz for HS operation
-  "grf_clk"	Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
-Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt     - Type-C PHY
-
-Example device nodes:
-
-	usbdrd3_0: usb@fe800000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
-			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_0: dwc3@fe800000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe800000 0x0 0x100000>;
-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};
-
-	usbdrd3_1: usb@fe900000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
-			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_1: dwc3@fe900000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe900000 0x0 0x100000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +39 -0

new file mode 100644
index 000000000..fdf9497bc
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Heiko Stuebner <[email protected]>
+
+description:
+      The common content of the node is defined in snps,dwc3.yaml.
+
+      Phy documentation is provided in the following places.
+
+      USB2.0 PHY
+      Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+
+      Type-C PHY
+      Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+
+allOf:
+  - $ref: snps,dwc3.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - rockchip,rk3399-dwc3
+      - const: snps,dwc3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +42 -0

+      - description:
+          Controller grf clock
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: suspend_clk
+      - const: bus_clk
+      - const: aclk_usb3_rksoc_axi_perf
+      - const: aclk_usb3
+      - const: grf_clk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: usb3-otg
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3399-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      usbdrd3_0: usb@fe800000 {
+        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+        reg = <0x0 0xfe800000 0x0 0x100000>;

Quoted 117 lines · Johan Jonker

In the past Rockchip dwc3 usb nodes were manually checked. With the conversion of snps,dwc3.yaml as common document we now can convert rockchip,dwc3.txt to yaml as well. Remove node wrapper.

Added properties for rk3399 are:
   power-domains
   resets
   reset-names

Signed-off-by Johan Jonker <[email protected]>

---
  .../devicetree/bindings/usb/rockchip,dwc3.txt      |  56 ----------- .../devicetree/bindings/usb/rockchip,dwc3.yaml     | 103
+++++++++++++++++++++

  2 files changed, 103 insertions(+), 56 deletions(-)

  delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml

Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted +0 -16

deleted file mode 100644
index 945204932..000000000
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible:    should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks:    A list of phandle + clock-specifier pairs for the
-        clocks listed in clock-names
-- clock-names:    Should contain the following:
-  "ref_clk"    Controller reference clk, have to be 24 MHz
-  "suspend_clk"    Controller suspend clk, have to be 24 MHz or 32 KHz
-  "bus_clk"    Master/Core clock, have to be >= 62.5 MHz for SS
-        operation and >= 30MHz for HS operation
-  "grf_clk"    Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in

dwc3.txt.

Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted +0 -3

-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml -

USB2.0 PHY -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt     - Type-C PHY

Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted +0 -36

-
-Example device nodes:
-
-    usbdrd3_0: usb@fe800000 {
-        compatible = "rockchip,rk3399-dwc3";
-        clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
-             <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
-        clock-names = "ref_clk", "suspend_clk",
-                  "bus_clk", "grf_clk";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-        usbdrd_dwc3_0: dwc3@fe800000 {
-            compatible = "snps,dwc3";
-            reg = <0x0 0xfe800000 0x0 0x100000>;
-            interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-            dr_mode = "otg";
-        };
-    };
-
-    usbdrd3_1: usb@fe900000 {
-        compatible = "rockchip,rk3399-dwc3";
-        clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
-             <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
-        clock-names = "ref_clk", "suspend_clk",
-                  "bus_clk", "grf_clk";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-        usbdrd_dwc3_1: dwc3@fe900000 {
-            compatible = "snps,dwc3";
-            reg = <0x0 0xfe900000 0x0 0x100000>;
-            interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-            dr_mode = "otg";
-        };
-    };

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +23 -0

new file mode 100644
index 000000000..fdf9497bc
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Heiko Stuebner <[email protected]>
+
+description:
+      The common content of the node is defined in snps,dwc3.yaml.
+
+      Phy documentation is provided in the following places.
+
+      USB2.0 PHY
+      Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+
+      Type-C PHY
+      Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+
+allOf:

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml line 24

Quoted 1 line

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +1 -0

+  - $ref: snps,dwc3.yaml#

Quoted 21 lines

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +21 -0

+
+properties:
+  compatible:
+    items:
+      - enum:
+          - rockchip,rk3399-dwc3
+      - const: snps,dwc3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description:
+          Controller reference clock, must to be 24 MHz
+      - description:
+          Controller suspend clock, must to be 24 MHz or 32 KHz
+      - description:

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml line 49

Quoted 4 lines

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +4 -0

+          Master/Core clock, must to be >= 62.5 MHz for SS
+          operation and >= 30MHz for HS operation
+      - description:
+          Controller aclk_usb3_rksoc_axi_perf clock

I'm pretty sure these last 3 don't belong to the controller itself, hence why they were in the glue layer node to being with.

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml line 51

Quoted 3 lines

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +2 -0

+      - description:
+          Controller aclk_usb3 clock

Does anything in the USB3 block actually consume this clock directly? If not, then I don't think it needs to be specified since it's already the parent of the controller's required bus_clk.

I'm similarly suspicious of ACLK_USB3_NOC which is currently marked as CLK_IGNORE_UNUSED - if that's necessary for USB3 to function then it probably *should* be specified as part of the glue layer binding here.

Robin.

Quoted 11 lines

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +10 -0

+      - description:
+          Controller grf clock
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: suspend_clk
+      - const: bus_clk
 
+      - const: aclk_usb3_rksoc_axi_perf
+      - const: aclk_usb3

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml line 71

Quoted 11 lines

+      - const: grf_clk

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +9 -0

+
+  power-domains:
+    maxItems: 1
+
 
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: usb3-otg

Quoted 25 lines

Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml new file +25 -0

+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3399-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      usbdrd3_0: usb@fe800000 {
+        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+        reg = <0x0 0xfe800000 0x0 0x100000>;
+        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+                 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,

Quoted 8 lines

+                 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; +        clock-names = "ref_clk", "suspend_clk",
+                      "bus_clk", "aclk_usb3_rksoc_axi_perf", +                      "aclk_usb3", "grf_clk";
+        dr_mode = "otg";
+      };
+    };

In the past Rockchip dwc3 usb nodes were manually checked. With the conversion of snps,dwc3.yaml as common document we now can convert rockchip,dwc3.txt to yaml as well. Remove node wrapper.

Added properties for rk3399 are:
power-domains
resets
reset-names

Signed-off-by Johan Jonker <[email protected]>

---
 .../devicetree/bindings/usb/rockchip,dwc3.txt      |  56 -----------
 .../devicetree/bindings/usb/rockchip,dwc3.yaml     | 103 +++++++++++++++++++++
 2 files changed, 103 insertions(+), 56 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml