Add Unisoc's drm kms module

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for drivers to explicitly call drm_mode_config_cleanup, so delete it.

---
 drivers/gpu/drm/Kconfig         |   2 +
 drivers/gpu/drm/Makefile        |   1 +
 drivers/gpu/drm/sprd/Kconfig    |  12 ++
 drivers/gpu/drm/sprd/Makefile   |   5 +
 drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
 6 files changed, 253 insertions(+)
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
 source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
 obj-$(CONFIG_DRM_MCDE) += mcde/
 obj-$(CONFIG_DRM_TIDSS) += tidss/
 obj-y                  += xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +12 -0

new file mode 100644
index 000000000..6e80cc9f3
@@ -0,0 +1,12 @@
+config DRM_SPRD
+       tristate "DRM Support for Unisoc SoCs Platform"
+       depends on ARCH_SPRD || COMPILE_TEST
+       depends on DRM && OF
+       select DRM_KMS_HELPER
+       select DRM_GEM_CMA_HELPER
+       select DRM_KMS_CMA_HELPER
+       select DRM_MIPI_DSI
+       help
+         Choose this option if you have a Unisoc chipset.
+         If M is selected the module will be called sprd_drm.
+

drivers/gpu/drm/sprd/Makefile new file +5 -0

new file mode 100644
index 000000000..86d95d93a
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)
+
+obj-y := sprd_drm.o

drivers/gpu/drm/sprd/sprd_drm.c new file +15 -0

new file mode 100644
index 000000000..a1d3ed655
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>

drivers/gpu/drm/sprd/sprd_drm.c new file +192 -0

+#define DRIVER_DATE    "20200201"
+#define DRIVER_MAJOR   1
+#define DRIVER_MINOR   0
+
+static const struct drm_mode_config_helper_funcs sprd_drm_mode_config_helper = {
+       .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+       .fb_create = drm_gem_fb_create,
+       .atomic_check = drm_atomic_helper_check,
+       .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+       drm->mode_config.min_width = 0;
+       drm->mode_config.min_height = 0;
+       drm->mode_config.max_width = 8192;
+       drm->mode_config.max_height = 8192;
+       drm->mode_config.allow_fb_modifiers = true;
+
+       drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+       drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+       .driver_features        = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+       .fops                   = &sprd_drm_fops,
+
+       /* GEM Operations */
+       DRM_GEM_CMA_DRIVER_OPS,
+
+       .name                   = DRIVER_NAME,
+       .desc                   = DRIVER_DESC,
+       .date                   = DRIVER_DATE,
+       .major                  = DRIVER_MAJOR,
+       .minor                  = DRIVER_MINOR,
+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct drm_device *drm;
+       struct sprd_drm *sprd;
+       int ret;
+
+       sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm, drm);
+       if (IS_ERR(sprd))
+               return PTR_ERR(sprd);
+
+       drm = &sprd->drm;
+       platform_set_drvdata(pdev, drm);
+
+       ret = drmm_mode_config_init(drm);
+       if (ret)
+               return ret;
+
+       sprd_drm_mode_config_init(drm);
+
+       /* bind and init sub drivers */
+       ret = component_bind_all(drm->dev, drm);
+       if (ret) {
+               drm_err(drm, "failed to bind all component.\n");
+               return ret;
+       }
+
+       /* vblank init */
+       ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+       if (ret) {
+               drm_err(drm, "failed to initialize vblank.\n");
+               goto err_unbind_all;
+       }
+       /* with irq_enabled = true, we can use the vblank feature. */
+       drm->irq_enabled = true;
+
+       /* reset all the states of crtc/plane/encoder/connector */
+       drm_mode_config_reset(drm);
+
+       /* init kms poll for handling hpd */
+       drm_kms_helper_poll_init(drm);
+
+       ret = drm_dev_register(drm, 0);
+       if (ret < 0)
+               goto err_kms_helper_poll_fini;
+
+       return 0;
+
+err_kms_helper_poll_fini:
+       drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+       component_unbind_all(drm->dev, drm);
+       return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+       struct drm_device *drm = dev_get_drvdata(dev);
+
+       drm_dev_unregister(drm);
+
+       drm_kms_helper_poll_fini(drm);
+
+       component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+       .bind = sprd_drm_bind,
+       .unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+       return dev->of_node == data;
+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       int ret;
+
+       ret = dma_set_mask_and_coherent(dev, ~0UL);
+       if (ret) {
+               dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
+               return ret;
+       }
+
+       return drm_of_component_probe(dev, compare_of, &drm_component_ops);
+}
+
+static int sprd_drm_remove(struct platform_device *pdev)
+{
+       component_master_del(&pdev->dev, &drm_component_ops);
+       return 0;
+}
+
+static void sprd_drm_shutdown(struct platform_device *pdev)
+{
+       struct drm_device *drm = platform_get_drvdata(pdev);
+
+       if (!drm) {
+               drm_warn(drm, "drm device is not available, no shutdown\n");
+               return;
+       }
+
+       drm_atomic_helper_shutdown(drm);
+}
+
+static const struct of_device_id drm_match_table[] = {
+       { .compatible = "sprd,display-subsystem", },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, drm_match_table);
+
+static struct platform_driver sprd_drm_driver = {
+       .probe = sprd_drm_probe,
+       .remove = sprd_drm_remove,
+       .shutdown = sprd_drm_shutdown,
+       .driver = {
+               .name = "sprd-drm-drv",
+               .of_match_table = drm_match_table,
+       },
+};
+
+static struct platform_driver *sprd_drm_drivers[]  = {
+       &sprd_drm_driver,
+};
+
+static int __init sprd_drm_init(void)
+{
+       int ret;
+
+       ret = platform_register_drivers(sprd_drm_drivers,
+                                       ARRAY_SIZE(sprd_drm_drivers));
+       return ret;
+}
+
+static void __exit sprd_drm_exit(void)
+{
+       platform_unregister_drivers(sprd_drm_drivers,
+                                   ARRAY_SIZE(sprd_drm_drivers));
+}
+
+module_init(sprd_drm_init);
+module_exit(sprd_drm_exit);
+
+MODULE_AUTHOR("Leon He <[email protected]>");
+MODULE_AUTHOR("Kevin Tang <[email protected]>");
+MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
+MODULE_LICENSE("GPL v2");

drivers/gpu/drm/sprd/sprd_drm.h new file +16 -1

new file mode 100644
index 000000000..9781fd591
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _SPRD_DRM_H_
+#define _SPRD_DRM_H_
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+
+struct sprd_drm {
+       struct drm_device drm;
+};
+
+#endif /* _SPRD_DRM_H_ */
--

2.29.0

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for
drivers to explicitly call drm_mode_config_cleanup, so delete it.

---
 drivers/gpu/drm/Kconfig         |   2 +
 drivers/gpu/drm/Makefile        |   1 +
 drivers/gpu/drm/sprd/Kconfig    |  12 ++
 drivers/gpu/drm/sprd/Makefile   |   5 +
 drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
 6 files changed, 253 insertions(+)
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
 source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
 obj-$(CONFIG_DRM_MCDE) += mcde/
 obj-$(CONFIG_DRM_TIDSS) += tidss/
 obj-y                  += xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +12 -0

new file mode 100644
index 000000000..6e80cc9f3
@@ -0,0 +1,12 @@
+config DRM_SPRD
+       tristate "DRM Support for Unisoc SoCs Platform"
+       depends on ARCH_SPRD || COMPILE_TEST
+       depends on DRM && OF
+       select DRM_KMS_HELPER
+       select DRM_GEM_CMA_HELPER
+       select DRM_KMS_CMA_HELPER
+       select DRM_MIPI_DSI
+       help
+         Choose this option if you have a Unisoc chipset.
+         If M is selected the module will be called sprd_drm.
+

drivers/gpu/drm/sprd/Makefile new file +5 -0

new file mode 100644
index 000000000..86d95d93a
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)
+
+obj-y := sprd_drm.o

drivers/gpu/drm/sprd/sprd_drm.c new file +30 -0

new file mode 100644
index 000000000..a1d3ed655
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME    "sprd"
+#define DRIVER_DESC    "Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE    "20200201"
+#define DRIVER_MAJOR   1
+#define DRIVER_MINOR   0
+
+static const struct drm_mode_config_helper_funcs

sprd_drm_mode_config_helper = {

drivers/gpu/drm/sprd/sprd_drm.c new file +25 -0

+       .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+       .fb_create = drm_gem_fb_create,
+       .atomic_check = drm_atomic_helper_check,
+       .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+       drm->mode_config.min_width = 0;
+       drm->mode_config.min_height = 0;
+       drm->mode_config.max_width = 8192;
+       drm->mode_config.max_height = 8192;
+       drm->mode_config.allow_fb_modifiers = true;
+
+       drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+       drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+       .driver_features        = DRIVER_GEM | DRIVER_MODESET |

DRIVER_ATOMIC,

drivers/gpu/drm/sprd/sprd_drm.c new file +20 -0

+       .fops                   = &sprd_drm_fops,
+
+       /* GEM Operations */
+       DRM_GEM_CMA_DRIVER_OPS,
+
+       .name                   = DRIVER_NAME,
+       .desc                   = DRIVER_DESC,
+       .date                   = DRIVER_DATE,
+       .major                  = DRIVER_MAJOR,
+       .minor                  = DRIVER_MINOR,
+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct drm_device *drm;
+       struct sprd_drm *sprd;
+       int ret;
+
+       sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm,

drm);

drivers/gpu/drm/sprd/sprd_drm.c new file +76 -0

+       if (IS_ERR(sprd))
+               return PTR_ERR(sprd);
+
+       drm = &sprd->drm;
+       platform_set_drvdata(pdev, drm);
+
+       ret = drmm_mode_config_init(drm);
+       if (ret)
+               return ret;
+
+       sprd_drm_mode_config_init(drm);
+
+       /* bind and init sub drivers */
+       ret = component_bind_all(drm->dev, drm);
+       if (ret) {
+               drm_err(drm, "failed to bind all component.\n");
+               return ret;
+       }
+
+       /* vblank init */
+       ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+       if (ret) {
+               drm_err(drm, "failed to initialize vblank.\n");
+               goto err_unbind_all;
+       }
+       /* with irq_enabled = true, we can use the vblank feature. */
+       drm->irq_enabled = true;
+
+       /* reset all the states of crtc/plane/encoder/connector */
+       drm_mode_config_reset(drm);
+
+       /* init kms poll for handling hpd */
+       drm_kms_helper_poll_init(drm);
+
+       ret = drm_dev_register(drm, 0);
+       if (ret < 0)
+               goto err_kms_helper_poll_fini;
+
+       return 0;
+
+err_kms_helper_poll_fini:
+       drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+       component_unbind_all(drm->dev, drm);
+       return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+       struct drm_device *drm = dev_get_drvdata(dev);
+
+       drm_dev_unregister(drm);
+
+       drm_kms_helper_poll_fini(drm);
+
+       component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+       .bind = sprd_drm_bind,
+       .unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+       return dev->of_node == data;
+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       int ret;
+
+       ret = dma_set_mask_and_coherent(dev, ~0UL);
+       if (ret) {
+               dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",

ret);

drivers/gpu/drm/sprd/sprd_drm.c new file +18 -0

+               return ret;
+       }
+
+       return drm_of_component_probe(dev, compare_of, &drm_component_ops);
+}
+
+static int sprd_drm_remove(struct platform_device *pdev)
+{
+       component_master_del(&pdev->dev, &drm_component_ops);
+       return 0;
+}
+
+static void sprd_drm_shutdown(struct platform_device *pdev)
+{
+       struct drm_device *drm = platform_get_drvdata(pdev);
+
+       if (!drm) {
+               drm_warn(drm, "drm device is not available, no

shutdown\n");

drivers/gpu/drm/sprd/sprd_drm.c new file +48 -0

+               return;
+       }
+
+       drm_atomic_helper_shutdown(drm);
+}
+
+static const struct of_device_id drm_match_table[] = {
+       { .compatible = "sprd,display-subsystem", },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, drm_match_table);
+
+static struct platform_driver sprd_drm_driver = {
+       .probe = sprd_drm_probe,
+       .remove = sprd_drm_remove,
+       .shutdown = sprd_drm_shutdown,
+       .driver = {
+               .name = "sprd-drm-drv",
+               .of_match_table = drm_match_table,
+       },
+};
+
+static struct platform_driver *sprd_drm_drivers[]  = {
+       &sprd_drm_driver,
+};
+
+static int __init sprd_drm_init(void)
+{
+       int ret;
+
+       ret = platform_register_drivers(sprd_drm_drivers,
+                                       ARRAY_SIZE(sprd_drm_drivers));
+       return ret;
+}
+
+static void __exit sprd_drm_exit(void)
+{
+       platform_unregister_drivers(sprd_drm_drivers,
+                                   ARRAY_SIZE(sprd_drm_drivers));
+}
+
+module_init(sprd_drm_init);
+module_exit(sprd_drm_exit);
+
+MODULE_AUTHOR("Leon He <[email protected]>");
+MODULE_AUTHOR("Kevin Tang <[email protected]>");
+MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
+MODULE_LICENSE("GPL v2");

drivers/gpu/drm/sprd/sprd_drm.h new file +16 -1

new file mode 100644
index 000000000..9781fd591
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _SPRD_DRM_H_
+#define _SPRD_DRM_H_
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+
+struct sprd_drm {
+       struct drm_device drm;
+};
+
+#endif /* _SPRD_DRM_H_ */
--

2.29.0

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel

peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for drivers to explicitly call drm_mode_config_cleanup, so delete it.

---
 drivers/gpu/drm/Kconfig         |   2 +
 drivers/gpu/drm/Makefile        |   1 +
 drivers/gpu/drm/sprd/Kconfig    |  12 ++
 drivers/gpu/drm/sprd/Makefile   |   5 +
 drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
 6 files changed, 253 insertions(+)
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
 source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
 obj-$(CONFIG_DRM_MCDE) += mcde/
 obj-$(CONFIG_DRM_TIDSS) += tidss/
 obj-y			+= xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +0 -0

new file mode 100644
index 000000000..6e80cc9f3

drivers/gpu/drm/sprd/Makefile new file +1 -0

+obj-y := sprd_drm.o

drivers/gpu/drm/sprd/sprd_drm.c new file +143 -0

new file mode 100644
index 000000000..a1d3ed655
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME	"sprd"
+#define DRIVER_DESC	"Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE	"20200201"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+static const struct drm_mode_config_helper_funcs sprd_drm_mode_config_helper = {
+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+	.fb_create = drm_gem_fb_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+	drm->mode_config.min_width = 0;
+	drm->mode_config.min_height = 0;
+	drm->mode_config.max_width = 8192;
+	drm->mode_config.max_height = 8192;
+	drm->mode_config.allow_fb_modifiers = true;
+
+	drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+	drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	.fops			= &sprd_drm_fops,
+
+	/* GEM Operations */
+	DRM_GEM_CMA_DRIVER_OPS,
+
+	.name			= DRIVER_NAME,
+	.desc			= DRIVER_DESC,
+	.date			= DRIVER_DATE,
+	.major			= DRIVER_MAJOR,
+	.minor			= DRIVER_MINOR,
+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct drm_device *drm;
+	struct sprd_drm *sprd;
+	int ret;
+
+	sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm, drm);
+	if (IS_ERR(sprd))
+		return PTR_ERR(sprd);
+
+	drm = &sprd->drm;
+	platform_set_drvdata(pdev, drm);
+
+	ret = drmm_mode_config_init(drm);
+	if (ret)
+		return ret;
+
+	sprd_drm_mode_config_init(drm);
+
+	/* bind and init sub drivers */
+	ret = component_bind_all(drm->dev, drm);
+	if (ret) {
+		drm_err(drm, "failed to bind all component.\n");
+		return ret;
+	}
+
+	/* vblank init */
+	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+	if (ret) {
+		drm_err(drm, "failed to initialize vblank.\n");
+		goto err_unbind_all;
+	}
+	/* with irq_enabled = true, we can use the vblank feature. */
+	drm->irq_enabled = true;
+
+	/* reset all the states of crtc/plane/encoder/connector */
+	drm_mode_config_reset(drm);
+
+	/* init kms poll for handling hpd */
+	drm_kms_helper_poll_init(drm);
+
+	ret = drm_dev_register(drm, 0);
+	if (ret < 0)
+		goto err_kms_helper_poll_fini;
+
+	return 0;
+
+err_kms_helper_poll_fini:
+	drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+	component_unbind_all(drm->dev, drm);
+	return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm);
+
+	drm_kms_helper_poll_fini(drm);
+
+	component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+	.bind = sprd_drm_bind,
+	.unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+

Hi

Quoted 6 lines · Kevin Tang

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel

^ internal

Quoted 10 lines

peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for

drivers to explicitly call drm_mode_config_cleanup, so delete it.

Quoted 43 lines

---
 drivers/gpu/drm/Kconfig         |   2 +
 drivers/gpu/drm/Makefile        |   1 +
 drivers/gpu/drm/sprd/Kconfig    |  12 ++
 drivers/gpu/drm/sprd/Makefile   |   5 +
 drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
 6 files changed, 253 insertions(+)
 create mode 100644 drivers/gpu/drm/sprd/Kconfig
 create mode 100644 drivers/gpu/drm/sprd/Makefile
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
 source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
 # Keep legacy drivers last
 
 menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
 obj-$(CONFIG_DRM_MCDE) += mcde/
 obj-$(CONFIG_DRM_TIDSS) += tidss/
 obj-y                        += xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +2 -0

new file mode 100644
index 000000000..6e80cc9f3
@@ -0,0 +1,12 @@
+config DRM_SPRD
+     tristate "DRM Support for Unisoc SoCs Platform"

drivers/gpu/drm/sprd/Kconfig line 8

Quoted 6 lines

drivers/gpu/drm/sprd/Kconfig new file +6 -0

+     depends on ARCH_SPRD || COMPILE_TEST
+     depends on DRM && OF
+     select DRM_KMS_HELPER
+     select DRM_GEM_CMA_HELPER
+     select DRM_KMS_CMA_HELPER
+     select DRM_MIPI_DSI

I guess this should rather be moved to your DSI introduction patch?

Review

Quoted 6 lines

drivers/gpu/drm/sprd/Kconfig new file +4 -0

+     help
+       Choose this option if you have a Unisoc chipset.
+       If M is selected the module will be called sprd_drm.
+

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/Makefile

drivers/gpu/drm/sprd/Makefile line 3

Quoted 8 lines

new file mode 100644
index 000000000..86d95d93a

drivers/gpu/drm/sprd/Makefile new file +3 -0

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)

Is it really needed? I'm not seeing any header that aren't in the include path already.

Review

Quoted 3 lines

drivers/gpu/drm/sprd/Makefile new file +1 -0

+obj-y := sprd_drm.o

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/sprd_drm.c

Quoted 25 lines

new file mode 100644
index 000000000..a1d3ed655

drivers/gpu/drm/sprd/sprd_drm.c new file +20 -0

@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>

drivers/gpu/drm/sprd/sprd_drm.c line 30

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME  "sprd"
+#define DRIVER_DESC  "Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE  "20200201"
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 0
+
+static const struct drm_mode_config_helper_funcs

sprd_drm_mode_config_helper = {

Quoted 15 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +15 -0

+     .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+     .fb_create = drm_gem_fb_create,
+     .atomic_check = drm_atomic_helper_check,
+     .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+     drm->mode_config.min_width = 0;
+     drm->mode_config.min_height = 0;
+     drm->mode_config.max_width = 8192;
+     drm->mode_config.max_height = 8192;

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+     drm->mode_config.allow_fb_modifiers = true;
+
+     drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+     drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+     .driver_features        = DRIVER_GEM | DRIVER_MODESET |

DRIVER_ATOMIC,

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+     .fops                   = &sprd_drm_fops,
+
+     /* GEM Operations */
+     DRM_GEM_CMA_DRIVER_OPS,
+
+     .name                   = DRIVER_NAME,
+     .desc                   = DRIVER_DESC,
+     .date                   = DRIVER_DATE,
+     .major                  = DRIVER_MAJOR,
+     .minor                  = DRIVER_MINOR,

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+     struct platform_device *pdev = to_platform_device(dev);
+     struct drm_device *drm;
+     struct sprd_drm *sprd;
+     int ret;
+
+     sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm,

drm);

Quoted 66 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +66 -0

+     if (IS_ERR(sprd))
+             return PTR_ERR(sprd);
+
+     drm = &sprd->drm;
+     platform_set_drvdata(pdev, drm);
+
+     ret = drmm_mode_config_init(drm);
+     if (ret)
+             return ret;
+
+     sprd_drm_mode_config_init(drm);
+
+     /* bind and init sub drivers */
+     ret = component_bind_all(drm->dev, drm);
+     if (ret) {
+             drm_err(drm, "failed to bind all component.\n");
+             return ret;
+     }
+
+     /* vblank init */
+     ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+     if (ret) {
+             drm_err(drm, "failed to initialize vblank.\n");
+             goto err_unbind_all;
+     }
+     /* with irq_enabled = true, we can use the vblank feature. */
+     drm->irq_enabled = true;
+
+     /* reset all the states of crtc/plane/encoder/connector */
+     drm_mode_config_reset(drm);
+
+     /* init kms poll for handling hpd */
+     drm_kms_helper_poll_init(drm);
+
+     ret = drm_dev_register(drm, 0);
+     if (ret < 0)
+             goto err_kms_helper_poll_fini;
+
+     return 0;
+
+err_kms_helper_poll_fini:
+     drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+     component_unbind_all(drm->dev, drm);
+     return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+     struct drm_device *drm = dev_get_drvdata(dev);
+
+     drm_dev_unregister(drm);
+
+     drm_kms_helper_poll_fini(drm);
+
+     component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+     .bind = sprd_drm_bind,
+     .unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+     return dev->of_node == data;

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+     struct device *dev = &pdev->dev;
+     int ret;
+
+     ret = dma_set_mask_and_coherent(dev, ~0UL);
+     if (ret) {
+             dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",

ret);

drivers/gpu/drm/sprd/sprd_drm.c line 153

Quoted 2 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +2 -0

+             return ret;
+     }

It's not really clear to me what it's here for. Could you explain with a comment here?

Thanks
Maxime

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for drivers to explicitly call drm_mode_config_cleanup, so delete it.

---
  drivers/gpu/drm/Kconfig         |   2 +
  drivers/gpu/drm/Makefile        |   1 +
  drivers/gpu/drm/sprd/Kconfig    |  12 ++
  drivers/gpu/drm/sprd/Makefile   |   5 +
  drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
  drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
  6 files changed, 253 insertions(+)

create mode 100644 drivers/gpu/drm/sprd/Kconfig create mode 100644 drivers/gpu/drm/sprd/Makefile create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
  source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
  # Keep legacy drivers last
 
  menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
  obj-$(CONFIG_DRM_MCDE) += mcde/
  obj-$(CONFIG_DRM_TIDSS) += tidss/
  obj-y			+= xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +0 -0

new file mode 100644
index 000000000..6e80cc9f3

drivers/gpu/drm/sprd/Kconfig new file +4 -0

+	help
+	  Choose this option if you have a Unisoc chipset.
+	  If M is selected the module will be called sprd_drm.
+

drivers/gpu/drm/sprd/Makefile new file +5 -0

new file mode 100644
index 000000000..86d95d93a
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)
+
+obj-y := sprd_drm.o

drivers/gpu/drm/sprd/sprd_drm.c new file +188 -0

new file mode 100644
index 000000000..a1d3ed655
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME	"sprd"
+#define DRIVER_DESC	"Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE	"20200201"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+static const struct drm_mode_config_helper_funcs sprd_drm_mode_config_helper = {
+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+	.fb_create = drm_gem_fb_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+	drm->mode_config.min_width = 0;
+	drm->mode_config.min_height = 0;
+	drm->mode_config.max_width = 8192;
+	drm->mode_config.max_height = 8192;
+	drm->mode_config.allow_fb_modifiers = true;
+
+	drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+	drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	.fops			= &sprd_drm_fops,
+
+	/* GEM Operations */
+	DRM_GEM_CMA_DRIVER_OPS,
+
+	.name			= DRIVER_NAME,
+	.desc			= DRIVER_DESC,
+	.date			= DRIVER_DATE,
+	.major			= DRIVER_MAJOR,
+	.minor			= DRIVER_MINOR,
+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct drm_device *drm;
+	struct sprd_drm *sprd;
+	int ret;
+
+	sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm, drm);
+	if (IS_ERR(sprd))
+		return PTR_ERR(sprd);
+
+	drm = &sprd->drm;
+	platform_set_drvdata(pdev, drm);
+
+	ret = drmm_mode_config_init(drm);
+	if (ret)
+		return ret;
+
+	sprd_drm_mode_config_init(drm);
+
+	/* bind and init sub drivers */
+	ret = component_bind_all(drm->dev, drm);
+	if (ret) {
+		drm_err(drm, "failed to bind all component.\n");
+		return ret;
+	}
+
+	/* vblank init */
+	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+	if (ret) {
+		drm_err(drm, "failed to initialize vblank.\n");
+		goto err_unbind_all;
+	}
+	/* with irq_enabled = true, we can use the vblank feature. */
+	drm->irq_enabled = true;
+
+	/* reset all the states of crtc/plane/encoder/connector */
+	drm_mode_config_reset(drm);
+
+	/* init kms poll for handling hpd */
+	drm_kms_helper_poll_init(drm);
+
+	ret = drm_dev_register(drm, 0);
+	if (ret < 0)
+		goto err_kms_helper_poll_fini;
+
+	return 0;
+
+err_kms_helper_poll_fini:
+	drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+	component_unbind_all(drm->dev, drm);
+	return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm);
+
+	drm_kms_helper_poll_fini(drm);
+
+	component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+	.bind = sprd_drm_bind,
+	.unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	ret = dma_set_mask_and_coherent(dev, ~0UL);
+	if (ret) {
+		dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
+		return ret;
+	}
+
+	return drm_of_component_probe(dev, compare_of, &drm_component_ops);
+}
+
+static int sprd_drm_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &drm_component_ops);
+	return 0;
+}
+
+static void sprd_drm_shutdown(struct platform_device *pdev)
+{
+	struct drm_device *drm = platform_get_drvdata(pdev);
+
+	if (!drm) {
+		drm_warn(drm, "drm device is not available, no shutdown\n");
+		return;
+	}
+
+	drm_atomic_helper_shutdown(drm);
+}
+
+static const struct of_device_id drm_match_table[] = {
+	{ .compatible = "sprd,display-subsystem", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, drm_match_table);
+
+static struct platform_driver sprd_drm_driver = {
+	.probe = sprd_drm_probe,
+	.remove = sprd_drm_remove,
+	.shutdown = sprd_drm_shutdown,
+	.driver = {
+		.name = "sprd-drm-drv",
+		.of_match_table = drm_match_table,

drivers/gpu/drm/sprd/sprd_drm.c new file +19 -0

+
+	ret = platform_register_drivers(sprd_drm_drivers,
+					ARRAY_SIZE(sprd_drm_drivers));
+	return ret;
+}
+
+static void __exit sprd_drm_exit(void)
+{
+	platform_unregister_drivers(sprd_drm_drivers,
+				    ARRAY_SIZE(sprd_drm_drivers));
+}
+
+module_init(sprd_drm_init);
+module_exit(sprd_drm_exit);
+
+MODULE_AUTHOR("Leon He <[email protected]>");
+MODULE_AUTHOR("Kevin Tang <[email protected]>");
+MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
+MODULE_LICENSE("GPL v2");

drivers/gpu/drm/sprd/sprd_drm.h new file +16 -0

new file mode 100644
index 000000000..9781fd591
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _SPRD_DRM_H_
+#define _SPRD_DRM_H_
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+
+struct sprd_drm {
+	struct drm_device drm;
+};
+
+#endif /* _SPRD_DRM_H_ */

Hi,

I have just a few nits below plus the points that others made.

Am 22.02.21 um 14:28 schrieb Kevin Tang:

Quoted 9 lines

Adds drm support for the Unisoc's display subsystem.

This is drm kms driver, this driver provides support for the application framework in Android, Yocto and more.

Application framework can access Unisoc's display internel peripherals through libdrm or libkms, it's test ok by modetest (DRM/KMS test tool) and Android HWComposer.

Quoted 7 lines

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v4:
- Move the devm_drm_dev_alloc to master_ops->bind function.
- The managed drmm_mode_config_init() it is no longer necessary for

drivers to explicitly call drm_mode_config_cleanup, so delete it.

Quoted 43 lines

---
  drivers/gpu/drm/Kconfig         |   2 +
  drivers/gpu/drm/Makefile        |   1 +
  drivers/gpu/drm/sprd/Kconfig    |  12 ++
  drivers/gpu/drm/sprd/Makefile   |   5 +
  drivers/gpu/drm/sprd/sprd_drm.c | 217 ++++++++++++++++++++++++++++++++
  drivers/gpu/drm/sprd/sprd_drm.h |  16 +++
  6 files changed, 253 insertions(+)

create mode 100644 drivers/gpu/drm/sprd/Kconfig create mode 100644 drivers/gpu/drm/sprd/Makefile create mode 100644 drivers/gpu/drm/sprd/sprd_drm.c create mode 100644 drivers/gpu/drm/sprd/sprd_drm.h

drivers/gpu/drm/Kconfig +2 -0

index 8bf103de1..9d6ce2867 100644
@@ -382,6 +382,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
 
  source "drivers/gpu/drm/xlnx/Kconfig"
 
+source "drivers/gpu/drm/sprd/Kconfig"
+
  # Keep legacy drivers last
 
  menuconfig DRM_LEGACY

drivers/gpu/drm/Makefile +1 -0

index 02c229392..42d211d9c 100644
@@ -126,3 +126,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
  obj-$(CONFIG_DRM_MCDE) += mcde/
  obj-$(CONFIG_DRM_TIDSS) += tidss/
  obj-y                       += xlnx/
+obj-$(CONFIG_DRM_SPRD) += sprd/

drivers/gpu/drm/sprd/Kconfig new file +2 -0

new file mode 100644
index 000000000..6e80cc9f3
@@ -0,0 +1,12 @@
+config DRM_SPRD
+     tristate "DRM Support for Unisoc SoCs Platform"

drivers/gpu/drm/sprd/Kconfig line 8

Quoted 6 lines

drivers/gpu/drm/sprd/Kconfig new file +6 -0

+     depends on ARCH_SPRD || COMPILE_TEST
+     depends on DRM && OF
+     select DRM_KMS_HELPER
+     select DRM_GEM_CMA_HELPER
+     select DRM_KMS_CMA_HELPER
+     select DRM_MIPI_DSI

Maybe keep the selects sorted by alphabet to make it more readable.

Review

Quoted 6 lines

drivers/gpu/drm/sprd/Kconfig new file +4 -0

+     help
+       Choose this option if you have a Unisoc chipset.
+       If M is selected the module will be called sprd_drm.
+

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/Makefile

Review

Quoted 11 lines

new file mode 100644
index 000000000..86d95d93a

drivers/gpu/drm/sprd/Makefile new file +5 -0

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/$(src)
+
+obj-y := sprd_drm.o

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/sprd_drm.c

Quoted 25 lines

new file mode 100644
index 000000000..a1d3ed655

drivers/gpu/drm/sprd/sprd_drm.c new file +20 -0

@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>

drivers/gpu/drm/sprd/sprd_drm.c line 30

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+
+#include "sprd_drm.h"
+
+#define DRIVER_NAME  "sprd"
+#define DRIVER_DESC  "Spreadtrum SoCs' DRM Driver"
+#define DRIVER_DATE  "20200201"
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 0
+
+static const struct drm_mode_config_helper_funcs

sprd_drm_mode_config_helper = {

Quoted 15 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +15 -0

+     .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct drm_mode_config_funcs sprd_drm_mode_config_funcs = {
+     .fb_create = drm_gem_fb_create,
+     .atomic_check = drm_atomic_helper_check,
+     .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void sprd_drm_mode_config_init(struct drm_device *drm)
+{
+     drm->mode_config.min_width = 0;
+     drm->mode_config.min_height = 0;
+     drm->mode_config.max_width = 8192;
+     drm->mode_config.max_height = 8192;

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+     drm->mode_config.allow_fb_modifiers = true;
+
+     drm->mode_config.funcs = &sprd_drm_mode_config_funcs;
+     drm->mode_config.helper_private = &sprd_drm_mode_config_helper;
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(sprd_drm_fops);
+
+static struct drm_driver sprd_drm_drv = {
+     .driver_features        = DRIVER_GEM | DRIVER_MODESET |

DRIVER_ATOMIC,

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+     .fops                   = &sprd_drm_fops,
+
+     /* GEM Operations */
+     DRM_GEM_CMA_DRIVER_OPS,
+
+     .name                   = DRIVER_NAME,
+     .desc                   = DRIVER_DESC,
+     .date                   = DRIVER_DATE,
+     .major                  = DRIVER_MAJOR,
+     .minor                  = DRIVER_MINOR,

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+};
+
+static int sprd_drm_bind(struct device *dev)
+{
+     struct platform_device *pdev = to_platform_device(dev);
+     struct drm_device *drm;
+     struct sprd_drm *sprd;
+     int ret;
+
+     sprd = devm_drm_dev_alloc(dev, &sprd_drm_drv, struct sprd_drm,

drm);

Quoted 66 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +66 -0

+     if (IS_ERR(sprd))
+             return PTR_ERR(sprd);
+
+     drm = &sprd->drm;
+     platform_set_drvdata(pdev, drm);
+
+     ret = drmm_mode_config_init(drm);
+     if (ret)
+             return ret;
+
+     sprd_drm_mode_config_init(drm);
+
+     /* bind and init sub drivers */
+     ret = component_bind_all(drm->dev, drm);
+     if (ret) {
+             drm_err(drm, "failed to bind all component.\n");
+             return ret;
+     }
+
+     /* vblank init */
+     ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+     if (ret) {
+             drm_err(drm, "failed to initialize vblank.\n");
+             goto err_unbind_all;
+     }
+     /* with irq_enabled = true, we can use the vblank feature. */
+     drm->irq_enabled = true;
+
+     /* reset all the states of crtc/plane/encoder/connector */
+     drm_mode_config_reset(drm);
+
+     /* init kms poll for handling hpd */
+     drm_kms_helper_poll_init(drm);
+
+     ret = drm_dev_register(drm, 0);
+     if (ret < 0)
+             goto err_kms_helper_poll_fini;
+
+     return 0;
+
+err_kms_helper_poll_fini:
+     drm_kms_helper_poll_fini(drm);
+err_unbind_all:
+     component_unbind_all(drm->dev, drm);
+     return ret;
+}
+
+static void sprd_drm_unbind(struct device *dev)
+{
+     struct drm_device *drm = dev_get_drvdata(dev);
+
+     drm_dev_unregister(drm);
+
+     drm_kms_helper_poll_fini(drm);
+
+     component_unbind_all(drm->dev, drm);
+}
+
+static const struct component_master_ops drm_component_ops = {
+     .bind = sprd_drm_bind,
+     .unbind = sprd_drm_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+     return dev->of_node == data;

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+}
+
+static int sprd_drm_probe(struct platform_device *pdev)
+{
+     struct device *dev = &pdev->dev;
+     int ret;
+
+     ret = dma_set_mask_and_coherent(dev, ~0UL);
+     if (ret) {
+             dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",

ret);

Quoted 8 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +8 -0

+             return ret;
+     }
+
+     return drm_of_component_probe(dev, compare_of, &drm_component_ops);
+}
+
+static int sprd_drm_remove(struct platform_device *pdev)
+{

drivers/gpu/drm/sprd/sprd_drm.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +10 -0

+     component_master_del(&pdev->dev, &drm_component_ops);
+     return 0;
+}
+
+static void sprd_drm_shutdown(struct platform_device *pdev)
+{
+     struct drm_device *drm = platform_get_drvdata(pdev);
+
+     if (!drm) {
+             drm_warn(drm, "drm device is not available, no

shutdown\n");

Quoted 23 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +23 -0

+             return;
+     }
+
+     drm_atomic_helper_shutdown(drm);
+}
+
+static const struct of_device_id drm_match_table[] = {
+     { .compatible = "sprd,display-subsystem", },
+     { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, drm_match_table);
+
+static struct platform_driver sprd_drm_driver = {
+     .probe = sprd_drm_probe,
+     .remove = sprd_drm_remove,
+     .shutdown = sprd_drm_shutdown,
+     .driver = {
+             .name = "sprd-drm-drv",
+             .of_match_table = drm_match_table,
+     },
+};
+
+static struct platform_driver *sprd_drm_drivers[]  = {

drivers/gpu/drm/sprd/sprd_drm.c line 198

Quoted 6 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +6 -0

+     &sprd_drm_driver,
+};
+
+static int __init sprd_drm_init(void)
+{
+     int ret;

I think ret should just go away.

Acked-by Thomas Zimmermann <[email protected]>

Review

Quoted 20 lines

drivers/gpu/drm/sprd/sprd_drm.c new file +19 -0

+
+     ret = platform_register_drivers(sprd_drm_drivers,
+                                     ARRAY_SIZE(sprd_drm_drivers));
+     return ret;
+}
+
+static void __exit sprd_drm_exit(void)
+{
+     platform_unregister_drivers(sprd_drm_drivers,
+                                 ARRAY_SIZE(sprd_drm_drivers));
+}
+
+module_init(sprd_drm_init);
+module_exit(sprd_drm_exit);
+
+MODULE_AUTHOR("Leon He <[email protected]>");
+MODULE_AUTHOR("Kevin Tang <[email protected]>");
+MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
+MODULE_LICENSE("GPL v2");

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/sprd_drm.h

Quoted 12 lines

new file mode 100644
index 000000000..9781fd591

drivers/gpu/drm/sprd/sprd_drm.h new file +6 -0

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#ifndef _SPRD_DRM_H_

drivers/gpu/drm/sprd/sprd_drm.h line 16

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_drm.h new file +10 -0

+#define _SPRD_DRM_H_
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_print.h>
+
+struct sprd_drm {
+     struct drm_device drm;
+};
+
+#endif /* _SPRD_DRM_H_ */

--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer

> +static int __init sprd_drm_init(void)
> +{
> +     int ret;

I think ret should just go away.

Like this?
"return platform_register_drivers(sprd_drm_drivers, ARRAY_SIZE(sprd_drm_drivers));"

if so, i will fix it, thks.

    Acked-by: Thomas Zimmermann <[email protected]
    <mailto:[email protected]>>

     > +
     > +     ret = platform_register_drivers(sprd_drm_drivers,
     > +                                     ARRAY_SIZE(sprd_drm_drivers));
     > +     return ret;
     > +}
     > +
     > +static void __exit sprd_drm_exit(void)
     > +{
     > +     platform_unregister_drivers(sprd_drm_drivers,
     > +                                 ARRAY_SIZE(sprd_drm_drivers));
     > +}
     > +
     > +module_init(sprd_drm_init);
     > +module_exit(sprd_drm_exit);
     > +
     > +MODULE_AUTHOR("Leon He <[email protected]
    <mailto:[email protected]>>");
     > +MODULE_AUTHOR("Kevin Tang <[email protected]
    <mailto:[email protected]>>");
     > +MODULE_DESCRIPTION("Unisoc DRM KMS Master Driver");
     > +MODULE_LICENSE("GPL v2");
     > diff --git a/drivers/gpu/drm/sprd/sprd_drm.h
    b/drivers/gpu/drm/sprd/sprd_drm.h
     > new file mode 100644
     > index 000000000..9781fd591
     > --- /dev/null
     > +++ b/drivers/gpu/drm/sprd/sprd_drm.h
     > @@ -0,0 +1,16 @@
     > +/* SPDX-License-Identifier: GPL-2.0 */
     > +/*
     > + * Copyright (C) 2020 Unisoc Inc.
     > + */
     > +
     > +#ifndef _SPRD_DRM_H_
     > +#define _SPRD_DRM_H_
     > +
     > +#include <drm/drm_atomic.h>
     > +#include <drm/drm_print.h>
     > +
     > +struct sprd_drm {
     > +     struct drm_device drm;
     > +};
     > +
     > +#endif /* _SPRD_DRM_H_ */
     >

    -- 
    Thomas Zimmermann
    Graphics Driver Developer
    SUSE Software Solutions Germany GmbH
    Maxfeldstr. 5, 90409 Nürnberg, Germany
    (HRB 36809, AG Nürnberg)
    Geschäftsführer: Felix Imendörffer

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Adds DPU(Display Processor Unit) support for the Unisoc's display subsystem. It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v2:
- Use drm_xxx to replace all DRM_XXX.
- Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.

v3:
- Remove dpu_layer stuff layer and commit layers by aotmic_update

v4:
- Use drmm_helpers to allocate crtc and planes.
- Move rotation enum definitions to crtc layer reg bitfields.
- Move allocate crtc and planes to bind funtion.

---
 drivers/gpu/drm/sprd/Kconfig    |   1 +
 drivers/gpu/drm/sprd/Makefile   |   4 +-
 drivers/gpu/drm/sprd/sprd_dpu.c | 964 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
 drivers/gpu/drm/sprd/sprd_drm.c |   1 +
 drivers/gpu/drm/sprd/sprd_drm.h |   2 +
 6 files changed, 1079 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h

drivers/gpu/drm/sprd/Kconfig +1 -0

index 6e80cc9f3..9b4ef9aea 100644
@@ -3,6 +3,7 @@ config DRM_SPRD
 	depends on ARCH_SPRD || COMPILE_TEST
 	depends on DRM && OF
 	select DRM_KMS_HELPER
+	select VIDEOMODE_HELPERS
 	select DRM_GEM_CMA_HELPER
 	select DRM_KMS_CMA_HELPER
 	select DRM_MIPI_DSI

drivers/gpu/drm/sprd/Makefile +2 -2

index 86d95d93a..6c25bfa99 100644
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
-subdir-ccflags-y += -I$(srctree)/$(src)
+obj-y := sprd_drm.o \
+	sprd_dpu.o
 
-obj-y := sprd_drm.o

drivers/gpu/drm/sprd/sprd_dpu.c new file +156 -0

new file mode 100644
index 000000000..75b7e40d9
@@ -0,0 +1,964 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/dma-buf.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "sprd_drm.h"
+#include "sprd_dpu.h"
+
+/* Global control registers */
+#define REG_DPU_CTRL	0x04
+#define REG_DPU_CFG0	0x08
+#define REG_PANEL_SIZE	0x20
+#define REG_BLEND_SIZE	0x24
+#define REG_BG_COLOR	0x2C
+
+/* Layer0 control registers */
+#define REG_LAY_BASE_ADDR0	0x30
+#define REG_LAY_BASE_ADDR1	0x34
+#define REG_LAY_BASE_ADDR2	0x38
+#define REG_LAY_CTRL		0x40
+#define REG_LAY_SIZE		0x44
+#define REG_LAY_PITCH		0x48
+#define REG_LAY_POS		0x4C
+#define REG_LAY_ALPHA		0x50
+#define REG_LAY_CROP_START	0x5C
+
+/* Interrupt control registers */
+#define REG_DPU_INT_EN		0x1E0
+#define REG_DPU_INT_CLR		0x1E4
+#define REG_DPU_INT_STS		0x1E8
+
+/* DPI control registers */
+#define REG_DPI_CTRL		0x1F0
+#define REG_DPI_H_TIMING	0x1F4
+#define REG_DPI_V_TIMING	0x1F8
+
+/* MMU control registers */
+#define REG_MMU_EN			0x800
+#define REG_MMU_VPN_RANGE		0x80C
+#define REG_MMU_VAOR_ADDR_RD		0x818
+#define REG_MMU_VAOR_ADDR_WR		0x81C
+#define REG_MMU_INV_ADDR_RD		0x820
+#define REG_MMU_INV_ADDR_WR		0x824
+#define REG_MMU_PPN1			0x83C
+#define REG_MMU_RANGE1			0x840
+#define REG_MMU_PPN2			0x844
+#define REG_MMU_RANGE2			0x848
+
+/* Global control bits */
+#define BIT_DPU_RUN			BIT(0)
+#define BIT_DPU_STOP			BIT(1)
+#define BIT_DPU_REG_UPDATE		BIT(2)
+#define BIT_DPU_IF_EDPI			BIT(0)
+
+/* Layer control bits */
+#define BIT_DPU_LAY_EN				BIT(0)
+#define BIT_DPU_LAY_LAYER_ALPHA			(0x01 << 2)
+#define BIT_DPU_LAY_COMBO_ALPHA			(0x02 << 2)
+#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE		(0x00 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE		(0x01 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE		(0x02 << 4)
+#define BIT_DPU_LAY_FORMAT_ARGB8888			(0x03 << 4)
+#define BIT_DPU_LAY_FORMAT_RGB565			(0x04 << 4)
+#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3		(0x00 << 8)
+#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0		(0x01 << 8)
+#define BIT_DPU_LAY_NO_SWITCH			(0x00 << 10)
+#define BIT_DPU_LAY_RB_OR_UV_SWITCH		(0x01 << 10)
+#define BIT_DPU_LAY_MODE_BLEND_NORMAL		(0x00 << 16)
+#define BIT_DPU_LAY_MODE_BLEND_PREMULT		(0x01 << 16)
+#define BIT_DPU_LAY_ROTATION_0		(0x00 << 20)
+#define BIT_DPU_LAY_ROTATION_90		(0x01 << 20)
+#define BIT_DPU_LAY_ROTATION_180	(0x02 << 20)
+#define BIT_DPU_LAY_ROTATION_270	(0x03 << 20)
+#define BIT_DPU_LAY_ROTATION_0_M	(0x04 << 20)
+#define BIT_DPU_LAY_ROTATION_90_M	(0x05 << 20)
+#define BIT_DPU_LAY_ROTATION_180_M	(0x06 << 20)
+#define BIT_DPU_LAY_ROTATION_270_M	(0x07 << 20)
+
+/* Interrupt control & status bits */
+#define BIT_DPU_INT_DONE		BIT(0)
+#define BIT_DPU_INT_TE			BIT(1)
+#define BIT_DPU_INT_ERR			BIT(2)
+#define BIT_DPU_INT_UPDATE_DONE		BIT(4)
+#define BIT_DPU_INT_VSYNC		BIT(5)
+#define BIT_DPU_INT_MMU_VAOR_RD		BIT(16)
+#define BIT_DPU_INT_MMU_VAOR_WR		BIT(17)
+#define BIT_DPU_INT_MMU_INV_RD		BIT(18)
+#define BIT_DPU_INT_MMU_INV_WR		BIT(19)
+
+/* DPI control bits */
+#define BIT_DPU_EDPI_TE_EN		BIT(8)
+#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD	BIT(10)
+#define BIT_DPU_DPI_HALT_EN		BIT(16)
+
+static const u32 primary_fmts[] = {
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV61,
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_YVU420,
+};
+
+struct sprd_plane {
+	struct drm_plane base;
+	u32 index;
+};
+
+static inline struct sprd_plane *to_sprd_plane(struct drm_plane *plane)
+{
+	return container_of(plane, struct sprd_plane, base);
+}
+
+static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
+			BIT_DPU_INT_MMU_VAOR_WR |
+			BIT_DPU_INT_MMU_INV_RD |
+			BIT_DPU_INT_MMU_INV_WR;
+	u32 val = reg_val & mmu_mask;
+	int i;
+
+	if (val) {
+		drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n", val);
+
+		if (val & BIT_DPU_INT_MMU_INV_RD)
+			drm_err(dpu->drm, "iommu invalid read error, addr: 0x%08x\n",

drivers/gpu/drm/sprd/sprd_dpu.c new file +348 -0

+		for (i = 0; i < 8; i++) {
+			reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);
+			if (reg_val & 0x1)
+				drm_info(dpu->drm, "layer%d: 0x%08x 0x%08x 0x%08x ctrl: 0x%08x\n", i,
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR0, i),
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR1, i),
+					layer_reg_rd(ctx, REG_LAY_BASE_ADDR2, i),
+					layer_reg_rd(ctx, REG_LAY_CTRL, i));
+		}
+	}
+
+	return val;
+}
+
+static int dpu_wait_stop_done(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	int rc;
+
+	if (ctx->stopped)
+		return 0;
+
+	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
+					       msecs_to_jiffies(500));
+	ctx->evt_stop = false;
+
+	ctx->stopped = true;
+
+	if (!rc) {
+		drm_err(dpu->drm, "dpu wait for stop done time out!\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int dpu_wait_update_done(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	int rc;
+
+	ctx->evt_update = false;
+
+	rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
+					       msecs_to_jiffies(500));
+
+	if (!rc) {
+		drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
+{
+	u32 format = 0;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_BGRA8888:
+		/* BGRA8888 -> ARGB8888 */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_RGBX8888:
+	case DRM_FORMAT_RGBA8888:
+		/* RGBA8888 -> ABGR8888 */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		/* fallthrough */
+	case DRM_FORMAT_ABGR8888:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		/* fallthrough */
+	case DRM_FORMAT_ARGB8888:
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_XBGR8888:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		/* fallthrough */
+	case DRM_FORMAT_XRGB8888:
+		format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+		break;
+	case DRM_FORMAT_BGR565:
+		/* RB switch */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		/* fallthrough */
+	case DRM_FORMAT_RGB565:
+		format |= BIT_DPU_LAY_FORMAT_RGB565;
+		break;
+	case DRM_FORMAT_NV12:
+		/* 2-Lane: Yuv420 */
+		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_NV21:
+		/* 2-Lane: Yuv420 */
+		format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	case DRM_FORMAT_NV16:
+		/* 2-Lane: Yuv422 */
+		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	case DRM_FORMAT_NV61:
+		/* 2-Lane: Yuv422 */
+		format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_YUV420:
+		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_NO_SWITCH;
+		break;
+	case DRM_FORMAT_YVU420:
+		format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+		/* Y endian */
+		format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+		/* UV endian */
+		format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+		break;
+	default:
+		break;
+	}
+
+	return format;
+}
+
+static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
+{
+	u32 rotation = 0;
+
+	switch (state->rotation) {
+	default:
+	case DRM_MODE_ROTATE_0:
+		rotation = BIT_DPU_LAY_ROTATION_0;
+		break;
+	case DRM_MODE_ROTATE_90:
+		rotation = BIT_DPU_LAY_ROTATION_90;
+		break;
+	case DRM_MODE_ROTATE_180:
+		rotation = BIT_DPU_LAY_ROTATION_180;
+		break;
+	case DRM_MODE_ROTATE_270:
+		rotation = BIT_DPU_LAY_ROTATION_270;
+		break;
+	case DRM_MODE_REFLECT_Y:
+		rotation = BIT_DPU_LAY_ROTATION_180_M;
+		break;
+	case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
+		rotation = BIT_DPU_LAY_ROTATION_90_M;
+		break;
+	case DRM_MODE_REFLECT_X:
+		rotation = BIT_DPU_LAY_ROTATION_0_M;
+		break;
+	case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
+		rotation = BIT_DPU_LAY_ROTATION_270_M;
+		break;
+	}
+
+	return rotation;
+}
+
+static u32 drm_blend_to_dpu(struct drm_plane_state *state)
+{
+	u32 blend = 0;
+
+	switch (state->pixel_blend_mode) {
+	case DRM_MODE_BLEND_COVERAGE:
+		/* alpha mode select - combo alpha */
+		blend |= BIT_DPU_LAY_COMBO_ALPHA;
+		/* Normal mode */
+		blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
+		break;
+	case DRM_MODE_BLEND_PREMULTI:
+		/* alpha mode select - combo alpha */
+		blend |= BIT_DPU_LAY_COMBO_ALPHA;
+		/* Pre-mult mode */
+		blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
+		break;
+	case DRM_MODE_BLEND_PIXEL_NONE:
+	default:
+		/* don't do blending, maybe RGBX */
+		/* alpha mode select - layer alpha */
+		blend |= BIT_DPU_LAY_LAYER_ALPHA;
+		break;
+	}
+
+	return blend;
+}
+
+static void sprd_dpu_layer(struct sprd_dpu *dpu, struct sprd_plane *plane,
+			struct drm_plane_state *state)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	struct drm_gem_cma_object *cma_obj;
+	const struct drm_format_info *info;
+	struct drm_framebuffer *fb = state->fb;
+	u32 addr, size, offset, pitch, blend, format, rotation;
+	u32 src_x = state->src_x >> 16;
+	u32 src_y = state->src_y >> 16;
+	u32 src_w = state->src_w >> 16;
+	u32 src_h = state->src_h >> 16;
+	u32 dst_x = state->crtc_x;
+	u32 dst_y = state->crtc_y;
+	u32 alpha = state->alpha;
+	int i;
+
+	offset = (dst_x & 0xffff) | (dst_y << 16);
+	size = (src_w & 0xffff) | (src_h << 16);
+
+	for (i = 0; i < fb->format->num_planes; i++) {
+		cma_obj = drm_fb_cma_get_gem_obj(fb, i);
+		addr = cma_obj->paddr + fb->offsets[i];
+
+		if (i == 0)
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, plane->index);
+		else if (i == 1)
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, plane->index);
+		else
+			layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, plane->index);
+	}
+
+	info = drm_format_info(fb->format->format);
+	if (fb->format->num_planes == 3) {
+		/* UV pitch is 1/2 of Y pitch */
+		pitch = (fb->pitches[0] / info->cpp[0]) |
+				(fb->pitches[0] / info->cpp[0] << 15);
+	} else {
+		pitch = fb->pitches[0] / info->cpp[0];
+	}
+
+	layer_reg_wr(ctx, REG_LAY_POS, offset, plane->index);
+	layer_reg_wr(ctx, REG_LAY_SIZE, size, plane->index);
+	layer_reg_wr(ctx, REG_LAY_CROP_START,
+			src_y << 16 | src_x, plane->index);
+	layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, plane->index);
+	layer_reg_wr(ctx, REG_LAY_PITCH, pitch, plane->index);
+
+	format = drm_format_to_dpu(fb);
+	blend = drm_blend_to_dpu(state);
+	rotation = drm_rotation_to_dpu(state);
+
+	layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
+				format |
+				blend |
+				rotation,
+				plane->index);
+}
+
+static void sprd_dpu_flip(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 reg_val;
+
+	/*
+	 * Make sure the dpu is in stop status. DPU has no shadow
+	 * registers in EDPI mode. So the config registers can only be
+	 * updated in the rising edge of DPU_RUN bit.
+	 */
+	if (ctx->if_type == SPRD_DPU_IF_EDPI)
+		dpu_wait_stop_done(dpu);
+
+	/* update trigger and wait */
+	if (ctx->if_type == SPRD_DPU_IF_DPI) {
+		if (!ctx->stopped) {
+			dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
+			dpu_wait_update_done(dpu);
+		}
+
+		dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
+	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
+		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
+
+		ctx->stopped = false;
+	}
+
+	/*
+	 * If the following interrupt was disabled in isr,
+	 * re-enable it.
+	 */
+	reg_val = BIT_DPU_INT_MMU_VAOR_RD |
+		  BIT_DPU_INT_MMU_VAOR_WR |
+		  BIT_DPU_INT_MMU_INV_RD |
+		  BIT_DPU_INT_MMU_INV_WR;
+	dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
+}
+
+static void sprd_dpu_init(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 size;
+
+	writel(0x00, ctx->base + REG_BG_COLOR);
+
+	size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
+	writel(size, ctx->base + REG_PANEL_SIZE);
+	writel(size, ctx->base + REG_BLEND_SIZE);
+
+	writel(0x00, ctx->base + REG_MMU_EN);
+	writel(0x00, ctx->base + REG_MMU_PPN1);
+	writel(0xffff, ctx->base + REG_MMU_RANGE1);
+	writel(0x00, ctx->base + REG_MMU_PPN2);
+	writel(0xffff, ctx->base + REG_MMU_RANGE2);
+	writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
+}
+
+static void sprd_dpu_fini(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	writel(0x00, ctx->base + REG_DPU_INT_EN);
+	writel(0xff, ctx->base + REG_DPU_INT_CLR);
+}
+
+static void sprd_dpi_init(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+	u32 int_mask = 0;
+	u32 reg_val;
+
+	if (ctx->if_type == SPRD_DPU_IF_DPI) {
+		/* use dpi as interface */
+		dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
+		/* disable Halt function for SPRD DSI */
+		dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
+		/* select te from external pad */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+
+		/* set dpi timing */
+		reg_val = ctx->vm.hsync_len << 0 |
+			  ctx->vm.hback_porch << 8 |
+			  ctx->vm.hfront_porch << 20;

drivers/gpu/drm/sprd/sprd_dpu.c new file +162 -0

+		/* enable dpu update done INT */
+		int_mask |= BIT_DPU_INT_UPDATE_DONE;
+		/* enable dpu done INT */
+		int_mask |= BIT_DPU_INT_DONE;
+		/* enable dpu dpi vsync */
+		int_mask |= BIT_DPU_INT_VSYNC;
+		/* enable dpu TE INT */
+		int_mask |= BIT_DPU_INT_TE;
+		/* enable underflow err INT */
+		int_mask |= BIT_DPU_INT_ERR;
+	} else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
+		/* use edpi as interface */
+		dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
+		/* use external te */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
+		/* enable te */
+		dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
+
+		/* enable stop done INT */
+		int_mask |= BIT_DPU_INT_DONE;
+		/* enable TE INT */
+		int_mask |= BIT_DPU_INT_TE;
+	}
+
+	/* enable iommu va out of range read error INT */
+	int_mask |= BIT_DPU_INT_MMU_VAOR_RD;
+	/* enable iommu va out of range write error INT */
+	int_mask |= BIT_DPU_INT_MMU_VAOR_WR;
+	/* enable iommu invalid read error INT */
+	int_mask |= BIT_DPU_INT_MMU_INV_RD;
+	/* enable iommu invalid write error INT */
+	int_mask |= BIT_DPU_INT_MMU_INV_WR;
+
+	writel(int_mask, ctx->base + REG_DPU_INT_EN);
+}
+
+void sprd_dpu_run(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
+
+	ctx->stopped = false;
+}
+
+void sprd_dpu_stop(struct sprd_dpu *dpu)
+{
+	struct dpu_context *ctx = &dpu->ctx;
+
+	if (ctx->if_type == SPRD_DPU_IF_DPI)
+		dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
+
+	dpu_wait_stop_done(dpu);
+}
+
+static int sprd_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_plane_state *state)
+{
+	struct drm_framebuffer *fb = state->fb;
+	struct drm_crtc_state *crtc_state;
+	u32 fmt;
+
+	if (!fb || !state->crtc)
+		return 0;
+
+	fmt = drm_format_to_dpu(fb);
+	if (!fmt)
+		return -EINVAL;
+
+	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	return drm_atomic_helper_check_plane_state(state, crtc_state,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  true, true);
+}
+
+static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
+				    struct drm_plane_state *old_state)
+{
+	struct drm_plane_state *state = drm_plane->state;
+	struct sprd_plane *plane = to_sprd_plane(drm_plane);
+	struct sprd_dpu *dpu = to_sprd_crtc(state->crtc);
+
+	/* start configure dpu layers */
+	sprd_dpu_layer(dpu, plane, state);
+}
+
+static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
+				     struct drm_plane_state *old_state)
+{
+	struct sprd_plane *plane = to_sprd_plane(drm_plane);
+	struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
+
+	layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, plane->index);
+}
+
+static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
+{
+	unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+				       BIT(DRM_MODE_BLEND_PREMULTI) |
+				       BIT(DRM_MODE_BLEND_COVERAGE);
+
+	/* create rotation property */
+	drm_plane_create_rotation_property(&plane->base,
+					   DRM_MODE_ROTATE_0,
+					   DRM_MODE_ROTATE_MASK |
+					   DRM_MODE_REFLECT_MASK);
+
+	/* create alpha property */
+	drm_plane_create_alpha_property(&plane->base);
+
+	/* create blend mode property */
+	drm_plane_create_blend_mode_property(&plane->base, supported_modes);
+
+	/* create zpos property */
+	drm_plane_create_zpos_immutable_property(&plane->base, index);
+}
+
+static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
+	.atomic_check = sprd_plane_atomic_check,
+	.atomic_update = sprd_plane_atomic_update,
+	.atomic_disable = sprd_plane_atomic_disable,
+};
+
+static const struct drm_plane_funcs sprd_plane_funcs = {
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane	= drm_atomic_helper_disable_plane,
+	.destroy = drm_plane_cleanup,
+	.reset = drm_atomic_helper_plane_reset,
+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static struct sprd_plane *sprd_plane_init(struct drm_device *drm)
+{
+	struct sprd_plane *plane, *primary;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
+					       1, &sprd_plane_funcs,
+					       primary_fmts, ARRAY_SIZE(primary_fmts),
+					       NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
+		if (IS_ERR(plane)) {
+			drm_err(drm, "fail to init primary plane\n");
+			return plane;
+		}
+
+		drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
+
+		sprd_plane_create_properties(plane, i);
+
+		plane->index = i;
+		if (i == 0)
+			primary = plane;
+	}
+
+	return primary;
+}

drivers/gpu/drm/sprd/sprd_dpu.c new file +5 -0

+	}
+
+	return MODE_OK;
+}
+

drivers/gpu/drm/sprd/sprd_dpu.c new file +89 -0

+	drm_crtc_vblank_on(&dpu->base);
+}
+
+static void sprd_crtc_atomic_disable(struct drm_crtc *crtc,
+				    struct drm_atomic_state *state)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+	struct drm_device *drm = dpu->base.dev;
+
+	drm_crtc_vblank_off(&dpu->base);
+
+	disable_irq(dpu->ctx.irq);
+
+	sprd_dpu_fini(dpu);
+
+	spin_lock_irq(&drm->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&drm->event_lock);
+}
+
+static int sprd_crtc_atomic_check(struct drm_crtc *crtc,
+				 struct drm_atomic_state *state)
+{
+	drm_dbg(crtc->dev, "%s()\n", __func__);
+
+	return 0;
+}
+
+static void sprd_crtc_atomic_flush(struct drm_crtc *crtc,
+				  struct drm_atomic_state *state)
+
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+	struct drm_device *drm = dpu->base.dev;
+
+	sprd_dpu_flip(dpu);
+
+	spin_lock_irq(&drm->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&drm->event_lock);
+}
+
+static int sprd_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+
+	dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
+
+	return 0;
+}
+
+static void sprd_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	struct sprd_dpu *dpu = to_sprd_crtc(crtc);
+
+	dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
+}
+
+static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = {
+	.mode_valid	= sprd_crtc_mode_valid,
+	.atomic_check	= sprd_crtc_atomic_check,
+	.atomic_flush	= sprd_crtc_atomic_flush,
+	.atomic_enable	= sprd_crtc_atomic_enable,
+	.atomic_disable	= sprd_crtc_atomic_disable,
+};
+
+static const struct drm_crtc_funcs sprd_crtc_funcs = {
+	.destroy	= drm_crtc_cleanup,
+	.set_config	= drm_atomic_helper_set_config,
+	.page_flip	= drm_atomic_helper_page_flip,
+	.reset		= drm_atomic_helper_crtc_reset,
+	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
+	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
+	.enable_vblank	= sprd_crtc_enable_vblank,
+	.disable_vblank	= sprd_crtc_disable_vblank,
+};
+
+static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
+			 struct drm_plane *primary)
+{
+	struct device_node *port;
+	struct sprd_dpu *dpu;
+

Hi,

Quoted 1 line · Kevin Tang

Adds DPU(Display Processor Unit) support for the Unisoc's display

subsystem.

Quoted 1 line

It's support multi planes, scaler, rotation, PQ(Picture Quality) and

more.

Quoted 12 lines

Cc Orson Zhai <[email protected]>

Cc Chunyan Zhang <[email protected]>

Signed-off-by Kevin Tang <[email protected]>

v2:
- Use drm_xxx to replace all DRM_XXX.
- Use kzalloc to replace devm_kzalloc for sprd_dpu structure init.

v3:
- Remove dpu_layer stuff layer and commit layers by aotmic_update

Quoted 4 lines

v4:
- Use drmm_helpers to allocate crtc and planes.
- Move rotation enum definitions to crtc layer reg bitfields.
- Move allocate crtc and planes to bind funtion.

There's a number of checkpatch warnings, make sure to fix them

Review

Quoted 25 lines

---
 drivers/gpu/drm/sprd/Kconfig    |   1 +
 drivers/gpu/drm/sprd/Makefile   |   4 +-
 drivers/gpu/drm/sprd/sprd_dpu.c | 964 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sprd/sprd_dpu.h | 109 ++++
 drivers/gpu/drm/sprd/sprd_drm.c |   1 +
 drivers/gpu/drm/sprd/sprd_drm.h |   2 +
 6 files changed, 1079 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c
 create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h

drivers/gpu/drm/sprd/Kconfig +1 -0

index 6e80cc9f3..9b4ef9aea 100644
@@ -3,6 +3,7 @@ config DRM_SPRD
      depends on ARCH_SPRD || COMPILE_TEST
      depends on DRM && OF
      select DRM_KMS_HELPER
+     select VIDEOMODE_HELPERS
      select DRM_GEM_CMA_HELPER
      select DRM_KMS_CMA_HELPER
      select DRM_MIPI_DSI

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/Makefile

Review

Quoted 12 lines

index 86d95d93a..6c25bfa99 100644

drivers/gpu/drm/sprd/Makefile +2 -2

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
-subdir-ccflags-y += -I$(srctree)/$(src)
+obj-y := sprd_drm.o \
+     sprd_dpu.o
 
-obj-y := sprd_drm.o

(quoted diff) +0 -0

b/drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 148 lines

new file mode 100644
index 000000000..75b7e40d9

drivers/gpu/drm/sprd/sprd_dpu.c new file +143 -0

@@ -0,0 +1,964 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Unisoc Inc.
+ */
+
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/dma-buf.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "sprd_drm.h"
+#include "sprd_dpu.h"
+
+/* Global control registers */
+#define REG_DPU_CTRL 0x04
+#define REG_DPU_CFG0 0x08
+#define REG_PANEL_SIZE       0x20
+#define REG_BLEND_SIZE       0x24
+#define REG_BG_COLOR 0x2C
+
+/* Layer0 control registers */
+#define REG_LAY_BASE_ADDR0   0x30
+#define REG_LAY_BASE_ADDR1   0x34
+#define REG_LAY_BASE_ADDR2   0x38
+#define REG_LAY_CTRL         0x40
+#define REG_LAY_SIZE         0x44
+#define REG_LAY_PITCH                0x48
+#define REG_LAY_POS          0x4C
+#define REG_LAY_ALPHA                0x50
+#define REG_LAY_CROP_START   0x5C
+
+/* Interrupt control registers */
+#define REG_DPU_INT_EN               0x1E0
+#define REG_DPU_INT_CLR              0x1E4
+#define REG_DPU_INT_STS              0x1E8
+
+/* DPI control registers */
+#define REG_DPI_CTRL         0x1F0
+#define REG_DPI_H_TIMING     0x1F4
+#define REG_DPI_V_TIMING     0x1F8
+
+/* MMU control registers */
+#define REG_MMU_EN                   0x800
+#define REG_MMU_VPN_RANGE            0x80C
+#define REG_MMU_VAOR_ADDR_RD         0x818
+#define REG_MMU_VAOR_ADDR_WR         0x81C
+#define REG_MMU_INV_ADDR_RD          0x820
+#define REG_MMU_INV_ADDR_WR          0x824
+#define REG_MMU_PPN1                 0x83C
+#define REG_MMU_RANGE1                       0x840
+#define REG_MMU_PPN2                 0x844
+#define REG_MMU_RANGE2                       0x848
+
+/* Global control bits */
+#define BIT_DPU_RUN                  BIT(0)
+#define BIT_DPU_STOP                 BIT(1)
+#define BIT_DPU_REG_UPDATE           BIT(2)
+#define BIT_DPU_IF_EDPI                      BIT(0)
+
+/* Layer control bits */
+#define BIT_DPU_LAY_EN                               BIT(0)
+#define BIT_DPU_LAY_LAYER_ALPHA                      (0x01 << 2)
+#define BIT_DPU_LAY_COMBO_ALPHA                      (0x02 << 2)
+#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE             (0x00 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE             (0x01 << 4)
+#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE             (0x02 << 4)
+#define BIT_DPU_LAY_FORMAT_ARGB8888                  (0x03 << 4)
+#define BIT_DPU_LAY_FORMAT_RGB565                    (0x04 << 4)
+#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3             (0x00 << 8)
+#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0             (0x01 << 8)
+#define BIT_DPU_LAY_NO_SWITCH                        (0x00 << 10)
+#define BIT_DPU_LAY_RB_OR_UV_SWITCH          (0x01 << 10)
+#define BIT_DPU_LAY_MODE_BLEND_NORMAL                (0x00 << 16)
+#define BIT_DPU_LAY_MODE_BLEND_PREMULT               (0x01 << 16)
+#define BIT_DPU_LAY_ROTATION_0               (0x00 << 20)
+#define BIT_DPU_LAY_ROTATION_90              (0x01 << 20)
+#define BIT_DPU_LAY_ROTATION_180     (0x02 << 20)
+#define BIT_DPU_LAY_ROTATION_270     (0x03 << 20)
+#define BIT_DPU_LAY_ROTATION_0_M     (0x04 << 20)
+#define BIT_DPU_LAY_ROTATION_90_M    (0x05 << 20)
+#define BIT_DPU_LAY_ROTATION_180_M   (0x06 << 20)
+#define BIT_DPU_LAY_ROTATION_270_M   (0x07 << 20)
+
+/* Interrupt control & status bits */
+#define BIT_DPU_INT_DONE             BIT(0)
+#define BIT_DPU_INT_TE                       BIT(1)
+#define BIT_DPU_INT_ERR                      BIT(2)
+#define BIT_DPU_INT_UPDATE_DONE              BIT(4)
+#define BIT_DPU_INT_VSYNC            BIT(5)
+#define BIT_DPU_INT_MMU_VAOR_RD              BIT(16)
+#define BIT_DPU_INT_MMU_VAOR_WR              BIT(17)
+#define BIT_DPU_INT_MMU_INV_RD               BIT(18)
+#define BIT_DPU_INT_MMU_INV_WR               BIT(19)
+
+/* DPI control bits */
+#define BIT_DPU_EDPI_TE_EN           BIT(8)
+#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD       BIT(10)
+#define BIT_DPU_DPI_HALT_EN          BIT(16)
+
+static const u32 primary_fmts[] = {
+     DRM_FORMAT_XRGB8888,
+     DRM_FORMAT_XBGR8888,
+     DRM_FORMAT_ARGB8888,
+     DRM_FORMAT_ABGR8888,
+     DRM_FORMAT_RGBA8888,
+     DRM_FORMAT_BGRA8888,
+     DRM_FORMAT_RGBX8888,
+     DRM_FORMAT_RGB565,
+     DRM_FORMAT_BGR565,
+     DRM_FORMAT_NV12,
+     DRM_FORMAT_NV21,
+     DRM_FORMAT_NV16,
+     DRM_FORMAT_NV61,
+     DRM_FORMAT_YUV420,
+     DRM_FORMAT_YVU420,
+};
+
+struct sprd_plane {
+     struct drm_plane base;
+     u32 index;
+};
+
+static inline struct sprd_plane *to_sprd_plane(struct drm_plane *plane)
+{
+     return container_of(plane, struct sprd_plane, base);
+}
+
+static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val)
+{

drivers/gpu/drm/sprd/sprd_dpu.c line 153

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+     struct dpu_context *ctx = &dpu->ctx;
+     u32 mmu_mask = BIT_DPU_INT_MMU_VAOR_RD |
+                     BIT_DPU_INT_MMU_VAOR_WR |
+                     BIT_DPU_INT_MMU_INV_RD |
+                     BIT_DPU_INT_MMU_INV_WR;
+     u32 val = reg_val & mmu_mask;
+     int i;
+
+     if (val) {
+             drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n",

val);

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 3 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +3 -0

+
+             if (val & BIT_DPU_INT_MMU_INV_RD)
+                     drm_err(dpu->drm, "iommu invalid read error, addr:

0x%08x\n",

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 3 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +3 -0

+                             readl(ctx->base + REG_MMU_INV_ADDR_RD));
+             if (val & BIT_DPU_INT_MMU_INV_WR)
+                     drm_err(dpu->drm, "iommu invalid write error,

addr: 0x%08x\n",

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 3 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +3 -0

+                             readl(ctx->base + REG_MMU_INV_ADDR_WR));
+             if (val & BIT_DPU_INT_MMU_VAOR_RD)
+                     drm_err(dpu->drm, "iommu va out of range read

error, addr: 0x%08x\n",

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 3 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +3 -0

+                             readl(ctx->base + REG_MMU_VAOR_ADDR_RD));
+             if (val & BIT_DPU_INT_MMU_VAOR_WR)
+                     drm_err(dpu->drm, "iommu va out of range write

error, addr: 0x%08x\n",

drivers/gpu/drm/sprd/sprd_dpu.c line 166

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+                             readl(ctx->base + REG_MMU_VAOR_ADDR_WR));

Is that the IOMMU page fault interrupt? I would expect it to be in the iommu driver.

drivers/gpu/drm/sprd/sprd_dpu.c line 168

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+             for (i = 0; i < 8; i++) {

+ reg_val = layer_reg_rd(ctx, REG_LAY_CTRL, i);

drivers/gpu/drm/sprd/sprd_dpu.c line 169

Quoted 2 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +2 -0

+                     if (reg_val & 0x1)
+                             drm_info(dpu->drm, "layer%d: 0x%08x 0x%08x

0x%08x ctrl: 0x%08x\n", i,

drivers/gpu/drm/sprd/sprd_dpu.c line 170

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+                                     layer_reg_rd(ctx,

REG_LAY_BASE_ADDR0, i),

drivers/gpu/drm/sprd/sprd_dpu.c line 171

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+                                     layer_reg_rd(ctx,

REG_LAY_BASE_ADDR1, i),

drivers/gpu/drm/sprd/sprd_dpu.c line 172

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+                                     layer_reg_rd(ctx,

REG_LAY_BASE_ADDR2, i),

drivers/gpu/drm/sprd/sprd_dpu.c line 173

Quoted 1 line

drivers/gpu/drm/sprd/sprd_dpu.c new file +1 -0

+                                     layer_reg_rd(ctx, REG_LAY_CTRL,

i));

Quoted 5 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +5 -0

+             }
+     }
+
+     return val;
+}

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+
+static int dpu_wait_stop_done(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+     int rc;
+
+     if (ctx->stopped)
+             return 0;
+
+     rc = wait_event_interruptible_timeout(ctx->wait_queue,

ctx->evt_stop,

Quoted 11 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +11 -0

+                                            msecs_to_jiffies(500));
+     ctx->evt_stop = false;
+
+     ctx->stopped = true;
+
+     if (!rc) {
+             drm_err(dpu->drm, "dpu wait for stop done time out!\n");
+             return -ETIMEDOUT;
+     }
+
+     return 0;

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+}
+
+static int dpu_wait_update_done(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+     int rc;
+
+     ctx->evt_update = false;
+
+     rc = wait_event_interruptible_timeout(ctx->wait_queue,

ctx->evt_update,

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 4 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +4 -0

+                                            msecs_to_jiffies(500));
+
+     if (!rc) {
+             drm_err(dpu->drm, "dpu wait for reg update done time

out!\n");

Quoted 149 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +149 -0

+             return -ETIMEDOUT;
+     }
+
+     return 0;
+}
+
+static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
+{
+     u32 format = 0;
+
+     switch (fb->format->format) {
+     case DRM_FORMAT_BGRA8888:
+             /* BGRA8888 -> ARGB8888 */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+             break;
+     case DRM_FORMAT_RGBX8888:
+     case DRM_FORMAT_RGBA8888:
+             /* RGBA8888 -> ABGR8888 */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+             /* fallthrough */
+     case DRM_FORMAT_ABGR8888:
+             /* RB switch */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             /* fallthrough */
+     case DRM_FORMAT_ARGB8888:
+             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+             break;
+     case DRM_FORMAT_XBGR8888:
+             /* RB switch */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             /* fallthrough */
+     case DRM_FORMAT_XRGB8888:
+             format |= BIT_DPU_LAY_FORMAT_ARGB8888;
+             break;
+     case DRM_FORMAT_BGR565:
+             /* RB switch */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             /* fallthrough */
+     case DRM_FORMAT_RGB565:
+             format |= BIT_DPU_LAY_FORMAT_RGB565;
+             break;
+     case DRM_FORMAT_NV12:
+             /* 2-Lane: Yuv420 */
+             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+             /* UV endian */
+             format |= BIT_DPU_LAY_NO_SWITCH;
+             break;
+     case DRM_FORMAT_NV21:
+             /* 2-Lane: Yuv420 */
+             format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+             /* UV endian */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             break;
+     case DRM_FORMAT_NV16:
+             /* 2-Lane: Yuv422 */
+             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
+             /* UV endian */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             break;
+     case DRM_FORMAT_NV61:
+             /* 2-Lane: Yuv422 */
+             format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+             /* UV endian */
+             format |= BIT_DPU_LAY_NO_SWITCH;
+             break;
+     case DRM_FORMAT_YUV420:
+             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+             /* UV endian */
+             format |= BIT_DPU_LAY_NO_SWITCH;
+             break;
+     case DRM_FORMAT_YVU420:
+             format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
+             /* Y endian */
+             format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
+             /* UV endian */
+             format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
+             break;
+     default:
+             break;
+     }
+
+     return format;
+}
+
+static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
+{
+     u32 rotation = 0;
+
+     switch (state->rotation) {
+     default:
+     case DRM_MODE_ROTATE_0:
+             rotation = BIT_DPU_LAY_ROTATION_0;
+             break;
+     case DRM_MODE_ROTATE_90:
+             rotation = BIT_DPU_LAY_ROTATION_90;
+             break;
+     case DRM_MODE_ROTATE_180:
+             rotation = BIT_DPU_LAY_ROTATION_180;
+             break;
+     case DRM_MODE_ROTATE_270:
+             rotation = BIT_DPU_LAY_ROTATION_270;
+             break;
+     case DRM_MODE_REFLECT_Y:
+             rotation = BIT_DPU_LAY_ROTATION_180_M;
+             break;
+     case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
+             rotation = BIT_DPU_LAY_ROTATION_90_M;
+             break;
+     case DRM_MODE_REFLECT_X:
+             rotation = BIT_DPU_LAY_ROTATION_0_M;
+             break;
+     case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
+             rotation = BIT_DPU_LAY_ROTATION_270_M;
+             break;
+     }
+
+     return rotation;
+}
+
+static u32 drm_blend_to_dpu(struct drm_plane_state *state)
+{
+     u32 blend = 0;
+
+     switch (state->pixel_blend_mode) {
+     case DRM_MODE_BLEND_COVERAGE:
+             /* alpha mode select - combo alpha */
+             blend |= BIT_DPU_LAY_COMBO_ALPHA;
+             /* Normal mode */
+             blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
+             break;
+     case DRM_MODE_BLEND_PREMULTI:
+             /* alpha mode select - combo alpha */
+             blend |= BIT_DPU_LAY_COMBO_ALPHA;
+             /* Pre-mult mode */
+             blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
+             break;
+     case DRM_MODE_BLEND_PIXEL_NONE:
+     default:

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+             /* don't do blending, maybe RGBX */
+             /* alpha mode select - layer alpha */
+             blend |= BIT_DPU_LAY_LAYER_ALPHA;
+             break;
+     }
+
+     return blend;
+}
+
+static void sprd_dpu_layer(struct sprd_dpu *dpu, struct sprd_plane

*plane,

Quoted 15 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +15 -0

+                     struct drm_plane_state *state)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+     struct drm_gem_cma_object *cma_obj;
+     const struct drm_format_info *info;
+     struct drm_framebuffer *fb = state->fb;
+     u32 addr, size, offset, pitch, blend, format, rotation;
+     u32 src_x = state->src_x >> 16;
+     u32 src_y = state->src_y >> 16;
+     u32 src_w = state->src_w >> 16;
+     u32 src_h = state->src_h >> 16;
+     u32 dst_x = state->crtc_x;
+     u32 dst_y = state->crtc_y;
+     u32 alpha = state->alpha;
+     int i;

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+
+     offset = (dst_x & 0xffff) | (dst_y << 16);
+     size = (src_w & 0xffff) | (src_h << 16);
+
+     for (i = 0; i < fb->format->num_planes; i++) {
+             cma_obj = drm_fb_cma_get_gem_obj(fb, i);
+             addr = cma_obj->paddr + fb->offsets[i];
+
+             if (i == 0)
+                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr,

plane->index);

drivers/gpu/drm/sprd/sprd_dpu.c line 399

Quoted 2 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +2 -0

+             else if (i == 1)
+                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr,

plane->index);

drivers/gpu/drm/sprd/sprd_dpu.c line 401

Quoted 2 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +2 -0

+             else
+                     layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr,

plane->index);

Quoted 97 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +97 -0

+     }
+
+     info = drm_format_info(fb->format->format);
+     if (fb->format->num_planes == 3) {
+             /* UV pitch is 1/2 of Y pitch */
+             pitch = (fb->pitches[0] / info->cpp[0]) |
+                             (fb->pitches[0] / info->cpp[0] << 15);
+     } else {
+             pitch = fb->pitches[0] / info->cpp[0];
+     }
+
+     layer_reg_wr(ctx, REG_LAY_POS, offset, plane->index);
+     layer_reg_wr(ctx, REG_LAY_SIZE, size, plane->index);
+     layer_reg_wr(ctx, REG_LAY_CROP_START,
+                     src_y << 16 | src_x, plane->index);
+     layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, plane->index);
+     layer_reg_wr(ctx, REG_LAY_PITCH, pitch, plane->index);
+
+     format = drm_format_to_dpu(fb);
+     blend = drm_blend_to_dpu(state);
+     rotation = drm_rotation_to_dpu(state);
+
+     layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
+                             format |
+                             blend |
+                             rotation,
+                             plane->index);
+}
+
+static void sprd_dpu_flip(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+     u32 reg_val;
+
+     /*
+      * Make sure the dpu is in stop status. DPU has no shadow
+      * registers in EDPI mode. So the config registers can only be
+      * updated in the rising edge of DPU_RUN bit.
+      */
+     if (ctx->if_type == SPRD_DPU_IF_EDPI)
+             dpu_wait_stop_done(dpu);
+
+     /* update trigger and wait */
+     if (ctx->if_type == SPRD_DPU_IF_DPI) {
+             if (!ctx->stopped) {
+                     dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
+                     dpu_wait_update_done(dpu);
+             }
+
+             dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
+     } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
+             dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
+
+             ctx->stopped = false;
+     }
+
+     /*
+      * If the following interrupt was disabled in isr,
+      * re-enable it.
+      */
+     reg_val = BIT_DPU_INT_MMU_VAOR_RD |
+               BIT_DPU_INT_MMU_VAOR_WR |
+               BIT_DPU_INT_MMU_INV_RD |
+               BIT_DPU_INT_MMU_INV_WR;
+     dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val);
+}
+
+static void sprd_dpu_init(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+     u32 size;
+
+     writel(0x00, ctx->base + REG_BG_COLOR);
+
+     size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
+     writel(size, ctx->base + REG_PANEL_SIZE);
+     writel(size, ctx->base + REG_BLEND_SIZE);
+
+     writel(0x00, ctx->base + REG_MMU_EN);
+     writel(0x00, ctx->base + REG_MMU_PPN1);
+     writel(0xffff, ctx->base + REG_MMU_RANGE1);
+     writel(0x00, ctx->base + REG_MMU_PPN2);
+     writel(0xffff, ctx->base + REG_MMU_RANGE2);
+     writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
+}
+
+static void sprd_dpu_fini(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;
+
+     writel(0x00, ctx->base + REG_DPU_INT_EN);
+     writel(0xff, ctx->base + REG_DPU_INT_CLR);
+}
+
+static void sprd_dpi_init(struct sprd_dpu *dpu)
+{
+     struct dpu_context *ctx = &dpu->ctx;

drivers/gpu/drm/sprd/sprd_dpu.c

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+     u32 int_mask = 0;
+     u32 reg_val;
+
+     if (ctx->if_type == SPRD_DPU_IF_DPI) {
+             /* use dpi as interface */
+             dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
+             /* disable Halt function for SPRD DSI */
+             dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
+             /* select te from external pad */
+             dpu_reg_set(ctx, REG_DPI_CTRL,

BIT_DPU_EDPI_FROM_EXTERNAL_PAD);

Quoted 10 lines

drivers/gpu/drm/sprd/sprd_dpu.c new file +10 -0

+
+             /* set dpi timing */
+             reg_val = ctx->vm.hsync_len << 0 |
+                       ctx->vm.hback_porch << 8 |
+                       ctx->vm.hfront_porch << 20;
+             writel(reg_val, ctx->base + REG_DPI_H_TIMING);
+
+             reg_val = ctx->vm.vsync_len << 0 |
+                       ctx->vm.vback_porch << 8 |
+                       ctx->vm.vfront_porch << 20;