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pinctrl: add BCM63XX pincontrol support

PATCH Superseded Álvaro Fernández Rojas 6 participants 24 messages Mar 6, 2021 – Mar 20, 2021

Subsystems (4)

v5 of 9 Superseded Latest is v9 →

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#0 lore raw

v5 cover pinctrl: add BCM63XX pincontrol support

First of all, I've based this on the patches sent by Jonas Gorski back in 2016:
https://www.spinics.net/lists/linux-gpio/msg15983.html
http://patchwork.ozlabs.org/project/linux-gpio/patch/[email protected]/

I've tried to address all coments from Linus Walleij, but I know that this may still need some other modifications

This patchset adds appropriate binding documentation and drivers for pin controller cores found in the BCM63XX MIPS SoCs currently supported.

While the GPIO part is always the same, the pinmux part varies quite a lot between different SoCs. Sometimes they have defined groups which can be muxed into different functions, sometimes each function has a different group. Sometimes you can mux individual pins. Often it is a combination of single pins and groups.

Some core versions require the GPIO direction to be set according to the function, most do not. Sometimes the mux register(s) contain bits for unrelated other functions.

v5: introduce changes suggested by Andy Shevchenko.
v4: fix gpiochip_irqchip_add_domain(), remove IRQ Kconfig selections and add
missing of_node_put().
v3: introduce new files for shared code and add more changes suggested by
Linus Walleij. Also add a new patch needed for properly parsing gpio-ranges.
v2: introduce changes suggested by Linus Walleij and remove interrupts
- In order to use GPIO_REGMAP, the need to get gpio_chip from gpio_regmap and use it for pinctrl_add_gpio_range() and gpio_chip.direction_input() and gpio_chip.direction_output().

Álvaro Fernández Rojas (15):
gpio: guard gpiochip_irqchip_add_domain() with GPIOLIB_IRQCHIP
gpio: regmap: set gpio_chip of_node
pinctrl: bcm: add bcm63xx base code
dt-bindings: add BCM6328 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM6328
dt-bindings: add BCM6358 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM6358
dt-bindings: add BCM6362 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM6362
dt-bindings: add BCM6368 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM6368
dt-bindings: add BCM63268 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM63268
dt-bindings: add BCM6318 pincontroller binding documentation
pinctrl: add a pincontrol driver for BCM6318

 .../pinctrl/brcm,bcm6318-pinctrl.yaml         | 187 +++++
 .../pinctrl/brcm,bcm63268-pinctrl.yaml        | 208 ++++++
 .../pinctrl/brcm,bcm6328-pinctrl.yaml         | 171 +++++
 .../pinctrl/brcm,bcm6358-pinctrl.yaml         | 137 ++++
 .../pinctrl/brcm,bcm6362-pinctrl.yaml         | 250 +++++++
 .../pinctrl/brcm,bcm6368-pinctrl.yaml         | 261 +++++++
 drivers/gpio/gpio-regmap.c                    |   4 +
 drivers/pinctrl/bcm/Kconfig                   |  55 ++
 drivers/pinctrl/bcm/Makefile                  |   7 +
 drivers/pinctrl/bcm/pinctrl-bcm6318.c         | 498 ++++++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm63268.c        | 643 ++++++++++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm6328.c         | 404 +++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm6358.c         | 369 ++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm6362.c         | 617 +++++++++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm6368.c         | 523 ++++++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm63xx.c         | 112 +++
 drivers/pinctrl/bcm/pinctrl-bcm63xx.h         |  43 ++
 include/linux/gpio/driver.h                   |   9 +
 include/linux/gpio/regmap.h                   |   3 +
 19 files changed, 4501 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6318.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63268.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6328.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6358.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6362.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6368.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.h
Signature · 1 line
2.20.1
#1 lore raw

PATCH v5 1/15 gpio: guard gpiochip_irqchip_add_domain() with GPIOLIB_IRQCHIP

The current code doesn't check if GPIOLIB_IRQCHIP is enabled, which results in a compilation error when trying to build gpio-regmap if CONFIG_GPIOLIB_IRQCHIP isn't enabled.

Fixes 6a45b0e2589f ("gpiolib: Introduce gpiochip_irqchip_add_domain()")

---
v5: add missing Suggested-by tag
v4: add patch (fix include instead of gpio-regmap.c)

 include/linux/gpio/driver.h | 9 +++++++++
 1 file changed, 9 insertions(+)
include/linux/gpio/driver.h +9 -0
index 286de0520574..ecf0032a0995 100644
@@ -624,8 +624,17 @@ void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
 				unsigned int offset);
 
+#ifdef CONFIG_GPIOLIB_IRQCHIP
 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
 				struct irq_domain *domain);
+#else
+static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
+					      struct irq_domain *domain)
+{
+	WARN_ON(1);
+	return -EINVAL;
+}
+#endif
 
 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
Signature · 1 line
2.20.1
Reviewed-by on v5 1/15
#2 lore raw

Re: [PATCH v5 01/15] gpio: guard gpiochip_irqchip_add_domain() with GPIOLIB_IRQCHIP

Am 2021-03-06 16:56, schrieb Álvaro Fernández Rojas:

Quoted 7 lines

The current code doesn't check if GPIOLIB_IRQCHIP is enabled, which results in a compilation error when trying to build gpio-regmap if CONFIG_GPIOLIB_IRQCHIP isn't enabled.

Fixes 6a45b0e2589f ("gpiolib: Introduce gpiochip_irqchip_add_domain()")

Thanks!
-michael

#3 lore raw

PATCH v5 2/15 gpio: regmap: set gpio_chip of_node

In reply to Álvaro Fernández Rojas

This is needed for properly registering GPIO regmap as a child of a regmap pin controller.

---
v5: switch to fwnode
v4: fix documentation
v3: introduce patch needed for properly parsing gpio-range

 drivers/gpio/gpio-regmap.c  | 4 ++++
 include/linux/gpio/regmap.h | 3 +++
 2 files changed, 7 insertions(+)
drivers/gpio/gpio-regmap.c +4 -0
index 5412cb3b0b2a..626433934d69 100644
@@ -249,6 +249,10 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
 
 	chip = &gpio->gpio_chip;
 	chip->parent = config->parent;
+	if (config->fwnode)
+		chip->of_node = to_of_node(config->fwnode);
+	else
+		chip->of_node = dev_of_node(config->parent);
 	chip->base = -1;
 	chip->ngpio = config->ngpio;
 	chip->names = config->names;
include/linux/gpio/regmap.h +3 -0
index ad76f3d0a6ba..c12e8d1d171b 100644
@@ -4,6 +4,7 @@
 #define _LINUX_GPIO_REGMAP_H
 
 struct device;
+struct fwnode_handle;
 struct gpio_regmap;
 struct irq_domain;
 struct regmap;
@@ -16,6 +17,7 @@ struct regmap;
  * @parent:		The parent device
  * @regmap:		The regmap used to access the registers
  *			given, the name of the device is used
+ * @fwnode:		(Optional) The firmware node
  * @label:		(Optional) Descriptive name for GPIO controller.
  *			If not given, the name of the device is used.
  * @ngpio:		Number of GPIOs
@@ -57,6 +59,7 @@ struct regmap;
 struct gpio_regmap_config {
 	struct device *parent;
 	struct regmap *regmap;
+	struct fwnode_handle *fwnode;
 
 	const char *label;
 	int ngpio;
Signature · 1 line
2.20.1
#4 lore raw

Re: [PATCH v5 02/15] gpio: regmap: set gpio_chip of_node

Quoted 3 lines · Álvaro Fernández Rojas

This is needed for properly registering GPIO regmap as a child of a regmap pin controller.

Thanks for an update!

...

Quoted 3 lines
        chip->parent = config->parent;

+ if (config->fwnode)

This...

drivers/gpio/gpio-regmap.c struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config · line 255

Quoted 4 lines
drivers/gpio/gpio-regmap.c +3 -0
+               chip->of_node = to_of_node(config->fwnode);
 
+       else
+               chip->of_node = dev_of_node(config->parent);

...and these lines are not needed. If there is no of_node in the chip, the GPIO library will take care of it to be parent's one.

Signature · 2 lines
With Best Regards,
Andy Shevchenko
#5 lore raw

Re: [PATCH v5 02/15] gpio: regmap: set gpio_chip of_node

In reply to Álvaro Fernández Rojas
Thank you for the patch! Yet something to improve:

Hi "Álvaro,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on pinctrl/devel]
[also build test ERROR on robh/for-next gpio/for-next v5.12-rc3 next-20210319] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/lvaro-Fern-ndez-Rojas/pinctrl-add-BCM63XX-pincontrol-support/20210307-115258
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: xtensa-randconfig-r014-20210318 (attached as .config)
compiler: xtensa-linux-gcc (GCC) 9.3.0

reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/46aec6ed90edf467c2e19c6e91e17d6b7567967f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review lvaro-Fern-ndez-Rojas/pinctrl-add-BCM63XX-pincontrol-support/20210307-115258 git checkout 46aec6ed90edf467c2e19c6e91e17d6b7567967f
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=xtensa

If you fix the issue, kindly add following tag as appropriate

All errors (new ones prefixed by >>):

drivers/gpio/gpio-regmap.c: In function 'gpio_regmap_register':

>> drivers/gpio/gpio-regmap.c:253:7: error: 'struct gpio_chip' has no member named 'of_node'
     253 |   chip->of_node = to_of_node(config->fwnode);
         |       ^~
   drivers/gpio/gpio-regmap.c:255:7: error: 'struct gpio_chip' has no member named 'of_node'
     255 |   chip->of_node = dev_of_node(config->parent);
         |       ^~

vim +253 drivers/gpio/gpio-regmap.c

192
193 /**
194 * gpio_regmap_register() - Register a generic regmap GPIO controller
195 * @config: configuration for gpio_regmap
196 *
197 * Return: A pointer to the registered gpio_regmap or ERR_PTR error value.
198 */
199 struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config)
200 {
201 struct gpio_regmap *gpio;
202 struct gpio_chip *chip;
203 int ret;
204
205 if (!config->parent)
206 return ERR_PTR(-EINVAL);
207
208 if (!config->ngpio)
209 return ERR_PTR(-EINVAL);
210
211 /* we need at least one */
212 if (!config->reg_dat_base && !config->reg_set_base)
213 return ERR_PTR(-EINVAL);
214
215 /* if we have a direction register we need both input and output */
216 if ((config->reg_dir_out_base || config->reg_dir_in_base) &&
217 (!config->reg_dat_base || !config->reg_set_base))
218 return ERR_PTR(-EINVAL);
219
220 /* we don't support having both registers simultaneously for now */
221 if (config->reg_dir_out_base && config->reg_dir_in_base)
222 return ERR_PTR(-EINVAL);
223
224 gpio = kzalloc(sizeof(*gpio), GFP_KERNEL);
225 if (!gpio)
226 return ERR_PTR(-ENOMEM);
227
228 gpio->parent = config->parent;
229 gpio->regmap = config->regmap;
230 gpio->ngpio_per_reg = config->ngpio_per_reg;
231 gpio->reg_stride = config->reg_stride;
232 gpio->reg_mask_xlate = config->reg_mask_xlate;
233 gpio->reg_dat_base = config->reg_dat_base;
234 gpio->reg_set_base = config->reg_set_base;
235 gpio->reg_clr_base = config->reg_clr_base;
236 gpio->reg_dir_in_base = config->reg_dir_in_base;
237 gpio->reg_dir_out_base = config->reg_dir_out_base;
238
239 /* if not set, assume there is only one register */
240 if (!gpio->ngpio_per_reg)
241 gpio->ngpio_per_reg = config->ngpio;
242
243 /* if not set, assume they are consecutive */
244 if (!gpio->reg_stride)
245 gpio->reg_stride = 1;
246
247 if (!gpio->reg_mask_xlate)
248 gpio->reg_mask_xlate = gpio_regmap_simple_xlate;
249
250 chip = &gpio->gpio_chip;
251 chip->parent = config->parent;
252 if (config->fwnode)

 > 253			chip->of_node = to_of_node(config->fwnode);

254 else
255 chip->of_node = dev_of_node(config->parent);
256 chip->base = -1;
257 chip->ngpio = config->ngpio;
258 chip->names = config->names;
259 chip->label = config->label ?: dev_name(config->parent);
260
261 /*
262 * If our regmap is fast_io we should probably set can_sleep to false.
263 * Right now, the regmap doesn't save this property, nor is there any
264 * access function for it.
265 * The only regmap type which uses fast_io is regmap-mmio. For now,
266 * assume a safe default of true here.
267 */
268 chip->can_sleep = true;
269
270 chip->get = gpio_regmap_get;
271 if (gpio->reg_set_base && gpio->reg_clr_base)
272 chip->set = gpio_regmap_set_with_clear;
273 else if (gpio->reg_set_base)
274 chip->set = gpio_regmap_set;
275
276 if (gpio->reg_dir_in_base || gpio->reg_dir_out_base) {
277 chip->get_direction = gpio_regmap_get_direction;
278 chip->direction_input = gpio_regmap_direction_input;
279 chip->direction_output = gpio_regmap_direction_output;
280 }
281
282 ret = gpiochip_add_data(chip, gpio);
283 if (ret < 0)
284 goto err_free_gpio;
285
286 if (config->irq_domain) {
287 ret = gpiochip_irqchip_add_domain(chip, config->irq_domain);
288 if (ret)
289 goto err_remove_gpiochip;
290 }
291
292 return gpio;
293
294 err_remove_gpiochip:
295 gpiochip_remove(chip);
296 err_free_gpio:
297 kfree(gpio);
298 return ERR_PTR(ret);
299 }
300 EXPORT_SYMBOL_GPL(gpio_regmap_register);
301

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

#6 lore raw

PATCH v5 3/15 pinctrl: bcm: add bcm63xx base code

In reply to Álvaro Fernández Rojas

Add a helper for registering BCM63XX pin controllers.

---
v5: add changes suggested by Andy Shevchenko
v4: drop IRQ selects from Kconfig and add missing of_node_put()
v3: add new patch with shared code

 drivers/pinctrl/bcm/Kconfig           |   7 ++
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm63xx.c | 112 ++++++++++++++++++++++++++
 drivers/pinctrl/bcm/pinctrl-bcm63xx.h |  43 ++++++++++
 4 files changed, 163 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.c
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.h
drivers/pinctrl/bcm/Kconfig +7 -0
index 0ed14de0134c..882f19bdc243 100644
@@ -29,6 +29,13 @@ config PINCTRL_BCM2835
 	help
 	   Say Y here to enable the Broadcom BCM2835 GPIO driver.
 
+config PINCTRL_BCM63XX
+	bool
+	select GENERIC_PINCONF
+	select GPIO_REGMAP
+	select PINCONF
+	select PINMUX
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index 79d5e49fdd9a..0e3cf9b15c65 100644
@@ -3,6 +3,7 @@
 
 obj-$(CONFIG_PINCTRL_BCM281XX)		+= pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
+obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +112 -0

112 lines not on this page · raw message

drivers/pinctrl/bcm/pinctrl-bcm63xx.h new file +43 -0

43 lines not on this page · raw message

Signature · 1 line
2.20.1
#7 lore raw

Re: [PATCH v5 03/15] pinctrl: bcm: add bcm63xx base code

Quoted 2 lines · Álvaro Fernández Rojas

Add a helper for registering BCM63XX pin controllers.

Thanks for this, but I think we may use the fwnode API. See below.

...

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 11

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+#include <linux/gpio/regmap.h>
+#include <linux/mfd/syscon.h>
 
+#include <linux/of.h>

+ property.h
+ mod_devicetable.h

Quoted 8 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+#include <linux/platform_device.h>
+
+#include "pinctrl-bcm63xx.h"
 
+static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
+                                 unsigned int base, unsigned int offset,
+                                 unsigned int *reg, unsigned int *mask)
+{

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 44

Quoted 10 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +9 -0
+       unsigned int line = offset % BCM63XX_BANK_GPIOS;
+       unsigned int stride = offset / BCM63XX_BANK_GPIOS;
+
+       *reg = base - stride * BCM63XX_BANK_SIZE;
+       *mask = BIT(line);
+
+       return 0;
+}
 
+static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node,

device_node *node -> fwnode_handle *fwnode

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 51

Quoted 8 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+                             const struct bcm63xx_pinctrl_soc *soc,
+                             struct bcm63xx_pinctrl *pc)
+{
+       struct gpio_regmap_config grc = {0};
+
+       grc.parent = dev;
 
+       grc.fwnode = &node->fwnode;

grc.fwnode = fwnode;

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 57

Quoted 6 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +5 -0
+       grc.ngpio = soc->ngpios;
+       grc.ngpio_per_reg = BCM63XX_BANK_GPIOS;
+       grc.regmap = pc->regs;
+       grc.reg_mask_xlate = bcm63xx_reg_mask_xlate;
 
+       if (of_property_read_u32(node, "data", &grc.reg_dat_base))

fwnode_property_read_u32()

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 61

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+               grc.reg_dat_base = BCM63XX_DATA_REG;
+       grc.reg_set_base = grc.reg_dat_base;
 
+       if (of_property_read_u32(node, "dirout", &grc.reg_dir_out_base))

Ditto.

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 73

Quoted 13 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +12 -0
+               grc.reg_dir_out_base = BCM63XX_DIROUT_REG;
+
+       return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc));
+}
+
+int bcm63xx_pinctrl_probe(struct platform_device *pdev,
+                         const struct bcm63xx_pinctrl_soc *soc,
+                         void *driver_data)
+{
+       struct device *dev = &pdev->dev;
+       struct bcm63xx_pinctrl *pc;
 
+       struct device_node *node;

struct fwnode_handle *fwnode;

Quoted 17 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +16 -0
+       int err;
+
+       pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+       if (!pc)
+               return -ENOMEM;
+
+       platform_set_drvdata(pdev, pc);
+
+       pc->dev = dev;
+       pc->driver_data = driver_data;
 
+       pc->regs = syscon_node_to_regmap(dev->parent->of_node);
+       if (IS_ERR(pc->regs))
+               return PTR_ERR(pc->regs);
+
+       pc->pctl_desc.name = dev_name(dev);
+       pc->pctl_desc.pins = soc->pins;

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 100

Quoted 10 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +9 -0
+       pc->pctl_desc.npins = soc->npins;
+       pc->pctl_desc.pctlops = soc->pctl_ops;
+       pc->pctl_desc.pmxops = soc->pmx_ops;
+       pc->pctl_desc.owner = THIS_MODULE;
+
+       pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+       if (IS_ERR(pc->pctl_dev))
+               return PTR_ERR(pc->pctl_dev);
 
+       for_each_child_of_node(dev->of_node, node) {

device_for_each_child_node(dev, fwnode) {

Quoted 1 line

+ if (of_match_node(bcm63xx_gpio_of_match, node)) {

// for now, since we have not an analogue (yet)
node ==> to_of_node(fwnode)

Quoted 1 line

+ err = bcm63xx_gpio_probe(dev, node, soc, pc);

...(dev, fwnode, soc, pc);

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 105

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+                       if (err) {
+                               dev_err(dev, "could not add GPIO chip\n");
 
+                               of_node_put(node);

fwnode_handle_put(fwnode);

Quoted 57 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+                               return err;
+                       }
+               }
+       }
+
+       return 0;
+}
drivers/pinctrl/bcm/pinctrl-bcm63xx.h new file +43 -1
new file mode 100644
index 000000000000..3bdb50021f1b
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
+ * Copyright (C) 2016 Jonas Gorski <[email protected]>
+ */
+
+#ifndef __PINCTRL_BCM63XX_H__
+#define __PINCTRL_BCM63XX_H__
+
+#include <linux/pinctrl/pinctrl.h>
+
+#define BCM63XX_BANK_GPIOS 32
+
+struct bcm63xx_pinctrl_soc {
+       struct pinctrl_ops *pctl_ops;
+       struct pinmux_ops *pmx_ops;
+
+       const struct pinctrl_pin_desc *pins;
+       unsigned npins;
+
+       unsigned int ngpios;
+};
+
+struct bcm63xx_pinctrl {
+       struct device *dev;
+       struct regmap *regs;
+
+       struct pinctrl_desc pctl_desc;
+       struct pinctrl_dev *pctl_dev;
+
+       void *driver_data;
+};
+
+static inline unsigned int bcm63xx_bank_pin(unsigned int pin)
+{
+       return pin % BCM63XX_BANK_GPIOS;
+}
+
+int bcm63xx_pinctrl_probe(struct platform_device *pdev,
+                         const struct bcm63xx_pinctrl_soc *soc,
+                         void *driver_data);
+
+#endif /* __PINCTRL_BCM63XX_H__ */
--
Quoted 2 lines

2.20.1

--
With Best Regards,
Andy Shevchenko

#8 lore raw

Re: [PATCH v5 03/15] pinctrl: bcm: add bcm63xx base code

Hi Andy,

Quoted 108 lines · Andy Shevchenko
Quoted 2 lines · Álvaro Fernández Rojas

Add a helper for registering BCM63XX pin controllers.

Thanks for this, but I think we may use the fwnode API. See below.

...

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 11

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+#include <linux/gpio/regmap.h>
+#include <linux/mfd/syscon.h>
 
+#include <linux/of.h>

+ property.h
+ mod_devicetable.h

Quoted 8 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+#include <linux/platform_device.h>
+
+#include "pinctrl-bcm63xx.h"
 
+static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
+                                 unsigned int base, unsigned int offset,
+                                 unsigned int *reg, unsigned int *mask)
+{

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 44

Quoted 10 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +9 -0
+       unsigned int line = offset % BCM63XX_BANK_GPIOS;
+       unsigned int stride = offset / BCM63XX_BANK_GPIOS;
+
+       *reg = base - stride * BCM63XX_BANK_SIZE;
+       *mask = BIT(line);
+
+       return 0;
+}
 
+static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node,

device_node *node -> fwnode_handle *fwnode

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 51

Quoted 8 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+                             const struct bcm63xx_pinctrl_soc *soc,
+                             struct bcm63xx_pinctrl *pc)
+{
+       struct gpio_regmap_config grc = {0};
+
+       grc.parent = dev;
 
+       grc.fwnode = &node->fwnode;

grc.fwnode = fwnode;

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 57

Quoted 6 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +5 -0
+       grc.ngpio = soc->ngpios;
+       grc.ngpio_per_reg = BCM63XX_BANK_GPIOS;
+       grc.regmap = pc->regs;
+       grc.reg_mask_xlate = bcm63xx_reg_mask_xlate;
 
+       if (of_property_read_u32(node, "data", &grc.reg_dat_base))

fwnode_property_read_u32()

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 61

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+               grc.reg_dat_base = BCM63XX_DATA_REG;
+       grc.reg_set_base = grc.reg_dat_base;
 
+       if (of_property_read_u32(node, "dirout", &grc.reg_dir_out_base))

Ditto.

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 73

Quoted 13 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +12 -0
+               grc.reg_dir_out_base = BCM63XX_DIROUT_REG;
+
+       return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc));
+}
+
+int bcm63xx_pinctrl_probe(struct platform_device *pdev,
+                         const struct bcm63xx_pinctrl_soc *soc,
+                         void *driver_data)
+{
+       struct device *dev = &pdev->dev;
+       struct bcm63xx_pinctrl *pc;
 
+       struct device_node *node;

struct fwnode_handle *fwnode;

Quoted 25 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +24 -0
+       int err;
+
+       pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+       if (!pc)
+               return -ENOMEM;
+
+       platform_set_drvdata(pdev, pc);
+
+       pc->dev = dev;
+       pc->driver_data = driver_data;
 
+       pc->regs = syscon_node_to_regmap(dev->parent->of_node);
+       if (IS_ERR(pc->regs))
+               return PTR_ERR(pc->regs);
+
+       pc->pctl_desc.name = dev_name(dev);
+       pc->pctl_desc.pins = soc->pins;
+       pc->pctl_desc.npins = soc->npins;
+       pc->pctl_desc.pctlops = soc->pctl_ops;
+       pc->pctl_desc.pmxops = soc->pmx_ops;
+       pc->pctl_desc.owner = THIS_MODULE;
+
+       pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
+       if (IS_ERR(pc->pctl_dev))
+               return PTR_ERR(pc->pctl_dev);
Quoted 8 lines
Quoted 1 line

+ for_each_child_of_node(dev->of_node, node) {

device_for_each_child_node(dev, fwnode) {

Quoted 1 line

+ if (of_match_node(bcm63xx_gpio_of_match, node)) {

// for now, since we have not an analogue (yet)
node ==> to_of_node(fwnode)

So you want me to convert everything to fwnode, but then I would need to use of_node here… It makes more sense to me to use of_node for now and convert it to fwnode in the future… @Linus, what do you think?

Quoted 68 lines
Quoted 2 lines

+ err = bcm63xx_gpio_probe(dev, node, soc, pc);

...(dev, fwnode, soc, pc);

drivers/pinctrl/bcm/pinctrl-bcm63xx.c line 105

Quoted 4 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +3 -0
+                       if (err) {
+                               dev_err(dev, "could not add GPIO chip\n");
 
+                               of_node_put(node);

fwnode_handle_put(fwnode);

Quoted 56 lines
drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file +7 -0
+                               return err;
+                       }
+               }
+       }
+
+       return 0;
+}
drivers/pinctrl/bcm/pinctrl-bcm63xx.h new file +43 -0
new file mode 100644
index 000000000000..3bdb50021f1b
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
+ * Copyright (C) 2016 Jonas Gorski <[email protected]>
+ */
+
+#ifndef __PINCTRL_BCM63XX_H__
+#define __PINCTRL_BCM63XX_H__
+
+#include <linux/pinctrl/pinctrl.h>
+
+#define BCM63XX_BANK_GPIOS 32
+
+struct bcm63xx_pinctrl_soc {
+       struct pinctrl_ops *pctl_ops;
+       struct pinmux_ops *pmx_ops;
+
+       const struct pinctrl_pin_desc *pins;
+       unsigned npins;
+
+       unsigned int ngpios;
+};
+
+struct bcm63xx_pinctrl {
+       struct device *dev;
+       struct regmap *regs;
+
+       struct pinctrl_desc pctl_desc;
+       struct pinctrl_dev *pctl_dev;
+
+       void *driver_data;
+};
+
+static inline unsigned int bcm63xx_bank_pin(unsigned int pin)
+{
+       return pin % BCM63XX_BANK_GPIOS;
+}
+
+int bcm63xx_pinctrl_probe(struct platform_device *pdev,
+                         const struct bcm63xx_pinctrl_soc *soc,
+                         void *driver_data);
+
+#endif /* __PINCTRL_BCM63XX_H__ */
Quoted 8 lines
Quoted 3 lines

--
2.20.1

--
With Best Regards,
Andy Shevchenko

Best regards,
Álvaro.

#9 lore raw

Re: [PATCH v5 03/15] pinctrl: bcm: add bcm63xx base code

Quoted 7 lines · Álvaro Fernández Rojas
Quoted 3 lines

// for now, since we have not an analogue (yet)

node ==> to_of_node(fwnode)

So you want me to convert everything to fwnode, but then I would need to use of_node here… It makes more sense to me to use of_node for now and convert it to fwnode in the future… @Linus, what do you think?

I am aware of the ambition to use fwnode more to more things.

To me it is most important on things that will potentially run with both OF and ACPI.
Typical example: ARM Qualcomm SoCs. New drivers for Aarch64 platforms.

This is a legacy MIPS platform, and we have tons of legacy platforms for ARM etc which will never get converted to fwnode, sadly.

Is it realistic that these MIPS platforms will run ACPI in addition to OF? Is ACPI even available on MIPS? Isn't OF the preferred HW description language for anything MIPS?

Yours,
Linus Walleij

#10 lore raw

PATCH v5 4/15 dt-bindings: add BCM6328 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6328 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6328-pinctrl.yaml         | 171 ++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +171 -0
new file mode 100644
index 000000000000..d4e3c7897f19
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6328 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6328-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6328-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,
+                  led, ephy0_act_led, ephy1_act_led, ephy2_act_led,
+                  ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,
+                  gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
+                  usb_port1 ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@10000080 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0x10000080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6328-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm6328-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 32>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio6";
+          };
+
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio7";
+          };
+        };
+
+        pinctrl_inet_act_led: inet_act_led {
+          function = "inet_act_led";
+          pins = "gpio11";
+        };
+
+        pinctrl_pcie_clkreq: pcie_clkreq {
+          function = "pcie_clkreq";
+          pins = "gpio16";
+        };
+
+        pinctrl_ephy0_spd_led: ephy0_spd_led {
+          function = "led";
+          pins = "gpio17";
+        };
+
+        pinctrl_ephy1_spd_led: ephy1_spd_led {
+          function = "led";
+          pins = "gpio18";
+        };
+
+        pinctrl_ephy2_spd_led: ephy2_spd_led {
+          function = "led";
+          pins = "gpio19";
+        };
+
+        pinctrl_ephy3_spd_led: ephy3_spd_led {
+          function = "led";
+          pins = "gpio20";
+        };
+
+        pinctrl_ephy0_act_led: ephy0_act_led {
+          function = "ephy0_act_led";
+          pins = "gpio25";
+        };
+
+        pinctrl_ephy1_act_led: ephy1_act_led {
+          function = "ephy1_act_led";
+          pins = "gpio26";
+        };
+
+        pinctrl_ephy2_act_led: ephy2_act_led {
+          function = "ephy2_act_led";
+          pins = "gpio27";
+        };
+
+        pinctrl_ephy3_act_led: ephy3_act_led {
+          function = "ephy3_act_led";
+          pins = "gpio28";
+        };
+
+        pinctrl_hsspi_cs1: hsspi_cs1 {
+          function = "hsspi_cs1";
+          pins = "hsspi_cs1";
+        };
+
+        pinctrl_usb_port1_device: usb_port1_device {
+          function = "usb_device_port";
+          pins = "usb_port1";
+        };
+
+        pinctrl_usb_port1_host: usb_port1_host {
+          function = "usb_host_port";
+          pins = "usb_port1";
+        };
+      };
+    };
Signature · 1 line
2.20.1
maintainer
#11 lore raw

Re: [PATCH v5 04/15] dt-bindings: add BCM6328 pincontroller binding documentation

Quoted 35 lines · Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6328 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6328-pinctrl.yaml         | 171 ++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +14 -0
new file mode 100644
index 000000000000..d4e3c7897f19
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6328 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.

Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml line 24

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +10 -0
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6328-pinctrl
+
+patternProperties:
+  '^gpio$':

Not a pattern, move to 'properties'

Quoted 22 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +22 -0
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6328-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1

Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml line 56

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +10 -0
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:

Instead of this hack (which shouldn't work because 'gpio' is also a node), use some defined node name pattern (e.g. '-pins$')

You need an 'additionalProperties: false' at this level.

Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml line 59

Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +3 -0
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"

Reference the pinctrl schemas which define these properties.

Quoted 9 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +9 -0
+          enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,
+                  led, ephy0_act_led, ephy1_act_led, ephy2_act_led,
+                  ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,
+                  gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
+                  usb_port1 ]

Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml line 78

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +10 -0
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@10000080 {
+      compatible = "syscon", "simple-mfd";

syscon needs a specific compatible for the SoC block.

What else is in this block besides pinctrl?

Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml line 82

Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +4 -0
+      reg = <0x10000080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6328-pinctrl";

Is there a register range of just pinctrl registers? If so, add 'reg' and define the sub-range.

Quoted 92 lines
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file +89 -0
+
+        gpio {
+          compatible = "brcm,bcm6328-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 32>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio6";
+          };
+
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio7";
+          };
+        };
+
+        pinctrl_inet_act_led: inet_act_led {
+          function = "inet_act_led";
+          pins = "gpio11";
+        };
+
+        pinctrl_pcie_clkreq: pcie_clkreq {
+          function = "pcie_clkreq";
+          pins = "gpio16";
+        };
+
+        pinctrl_ephy0_spd_led: ephy0_spd_led {
+          function = "led";
+          pins = "gpio17";
+        };
+
+        pinctrl_ephy1_spd_led: ephy1_spd_led {
+          function = "led";
+          pins = "gpio18";
+        };
+
+        pinctrl_ephy2_spd_led: ephy2_spd_led {
+          function = "led";
+          pins = "gpio19";
+        };
+
+        pinctrl_ephy3_spd_led: ephy3_spd_led {
+          function = "led";
+          pins = "gpio20";
+        };
+
+        pinctrl_ephy0_act_led: ephy0_act_led {
+          function = "ephy0_act_led";
+          pins = "gpio25";
+        };
+
+        pinctrl_ephy1_act_led: ephy1_act_led {
+          function = "ephy1_act_led";
+          pins = "gpio26";
+        };
+
+        pinctrl_ephy2_act_led: ephy2_act_led {
+          function = "ephy2_act_led";
+          pins = "gpio27";
+        };
+
+        pinctrl_ephy3_act_led: ephy3_act_led {
+          function = "ephy3_act_led";
+          pins = "gpio28";
+        };
+
+        pinctrl_hsspi_cs1: hsspi_cs1 {
+          function = "hsspi_cs1";
+          pins = "hsspi_cs1";
+        };
+
+        pinctrl_usb_port1_device: usb_port1_device {
+          function = "usb_device_port";
+          pins = "usb_port1";
+        };
+
+        pinctrl_usb_port1_host: usb_port1_host {
+          function = "usb_host_port";
+          pins = "usb_port1";
+        };
+      };
+    };
Signature · 1 line
2.20.1
#12 lore raw

PATCH v5 5/15 pinctrl: add a pincontrol driver for BCM6328

In reply to Álvaro Fernández Rojas

Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig           |   8 +
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm6328.c | 404 ++++++++++++++++++++++++++
 3 files changed, 413 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6328.c
drivers/pinctrl/bcm/Kconfig +8 -0
index 882f19bdc243..d35e5d3fe26f 100644
@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX
 	select PINCONF
 	select PINMUX
 
+config PINCTRL_BCM6328
+	bool "Broadcom BCM6328 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM6328 GPIO driver.
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index 0e3cf9b15c65..57e5434a6db6 100644
@@ -4,6 +4,7 @@
 obj-$(CONFIG_PINCTRL_BCM281XX)		+= pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
+obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm6328.c new file +404 -0

404 lines not on this page · raw message

Signature · 1 line
2.20.1
#13 lore raw

PATCH v5 6/15 dt-bindings: add BCM6358 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6358 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6358-pinctrl.yaml         | 137 ++++++++++++++++++
 1 file changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml new file +137 -0
new file mode 100644
index 000000000000..eb14dd4cdaaa
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6358 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6358-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6358-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia,
+                  pwm_syn_clk, sys_irq ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,
+                  led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@fffe0080 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0xfffe0080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6358-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm6358-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 40>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_ebi_cs: ebi_cs {
+          function = "ebi_cs";
+          groups = "ebi_cs_grp";
+        };
+
+        pinctrl_uart1: uart1 {
+          function = "uart1";
+          groups = "uart1_grp";
+        };
+
+        pinctrl_serial_led: serial_led {
+          function = "serial_led";
+          groups = "serial_led_grp";
+        };
+
+        pinctrl_legacy_led: legacy_led {
+          function = "legacy_led";
+          groups = "legacy_led_grp";
+        };
+
+        pinctrl_led: led {
+          function = "led";
+          groups = "led_grp";
+        };
+
+        pinctrl_spi_cs_23: spi_cs {
+          function = "spi_cs";
+          groups = "spi_cs_grp";
+        };
+
+        pinctrl_utopia: utopia {
+          function = "utopia";
+          groups = "utopia_grp";
+        };
+
+        pinctrl_pwm_syn_clk: pwm_syn_clk {
+          function = "pwm_syn_clk";
+          groups = "pwm_syn_clk_grp";
+        };
+
+        pinctrl_sys_irq: sys_irq {
+          function = "sys_irq";
+          groups = "sys_irq_grp";
+        };
+      };
+    };
Signature · 1 line
2.20.1
#14 lore raw

PATCH v5 7/15 pinctrl: add a pincontrol driver for BCM6358

In reply to Álvaro Fernández Rojas

Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig           |   8 +
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm6358.c | 369 ++++++++++++++++++++++++++
 3 files changed, 378 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6358.c
drivers/pinctrl/bcm/Kconfig +8 -0
index d35e5d3fe26f..ced7cc6ab44f 100644
@@ -44,6 +44,14 @@ config PINCTRL_BCM6328
 	help
 	   Say Y here to enable the Broadcom BCM6328 GPIO driver.
 
+config PINCTRL_BCM6358
+	bool "Broadcom BCM6358 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM6358 GPIO driver.
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index 57e5434a6db6..c3f5b7b2f2f0 100644
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX)		+= pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
 obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
+obj-$(CONFIG_PINCTRL_BCM6358)		+= pinctrl-bcm6358.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm6358.c new file +369 -0

369 lines not on this page · raw message

Signature · 1 line
2.20.1
#15 lore raw

PATCH v5 8/15 dt-bindings: add BCM6362 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6362 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6362-pinctrl.yaml         | 250 ++++++++++++++++++
 1 file changed, 250 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml new file +250 -0
new file mode 100644
index 000000000000..f33b56cd883f
@@ -0,0 +1,250 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6362 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6362-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6362-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data,
+                  robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1,
+                  inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts,
+                  uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso,
+                  adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led,
+                  ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1,
+                  ext_irq2, ext_irq3, nand ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+                  gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
+                  gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
+                  gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@10000080 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0x10000080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6362-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm6362-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 48>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_usb_device_led: usb_device_led {
+          function = "usb_device_led";
+          pins = "gpio0";
+        };
+
+        pinctrl_sys_irq: sys_irq {
+          function = "sys_irq";
+          pins = "gpio1";
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio2";
+          };
+
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio3";
+          };
+        };
+
+        pinctrl_robosw_led_data: robosw_led_data {
+          function = "robosw_led_data";
+          pins = "gpio4";
+        };
+
+        pinctrl_robosw_led_clk: robosw_led_clk {
+          function = "robosw_led_clk";
+          pins = "gpio5";
+        };
+
+        pinctrl_robosw_led0: robosw_led0 {
+          function = "robosw_led0";
+          pins = "gpio6";
+        };
+
+        pinctrl_robosw_led1: robosw_led1 {
+          function = "robosw_led1";
+          pins = "gpio7";
+        };
+
+        pinctrl_inet_led: inet_led {
+          function = "inet_led";
+          pins = "gpio8";
+        };
+
+        pinctrl_spi_cs2: spi_cs2 {
+          function = "spi_cs2";
+          pins = "gpio9";
+        };
+
+        pinctrl_spi_cs3: spi_cs3 {
+          function = "spi_cs3";
+          pins = "gpio10";
+        };
+
+        pinctrl_ntr_pulse: ntr_pulse {
+          function = "ntr_pulse";
+          pins = "gpio11";
+        };
+
+        pinctrl_uart1_scts: uart1_scts {
+          function = "uart1_scts";
+          pins = "gpio12";
+        };
+
+        pinctrl_uart1_srts: uart1_srts {
+          function = "uart1_srts";
+          pins = "gpio13";
+        };
+
+        pinctrl_uart1: uart1 {
+          pinctrl_uart1_sdin: uart1_sdin {
+            function = "uart1_sdin";
+            pins = "gpio14";
+          };
+
+          pinctrl_uart1_sdout: uart1_sdout {
+            function = "uart1_sdout";
+            pins = "gpio15";
+          };
+        };
+
+        pinctrl_adsl_spi: adsl_spi {
+          pinctrl_adsl_spi_miso: adsl_spi_miso {
+            function = "adsl_spi_miso";
+            pins = "gpio16";
+          };
+
+          pinctrl_adsl_spi_mosi: adsl_spi_mosi {
+            function = "adsl_spi_mosi";
+            pins = "gpio17";
+          };
+
+          pinctrl_adsl_spi_clk: adsl_spi_clk {
+            function = "adsl_spi_clk";
+            pins = "gpio18";
+          };
+
+          pinctrl_adsl_spi_cs: adsl_spi_cs {
+            function = "adsl_spi_cs";
+            pins = "gpio19";
+          };
+        };
+
+        pinctrl_ephy0_led: ephy0_led {
+          function = "ephy0_led";
+          pins = "gpio20";
+        };
+
+        pinctrl_ephy1_led: ephy1_led {
+          function = "ephy1_led";
+          pins = "gpio21";
+        };
+
+        pinctrl_ephy2_led: ephy2_led {
+          function = "ephy2_led";
+          pins = "gpio22";
+        };
+
+        pinctrl_ephy3_led: ephy3_led {
+          function = "ephy3_led";
+          pins = "gpio23";
+        };
+
+        pinctrl_ext_irq0: ext_irq0 {
+          function = "ext_irq0";
+          pins = "gpio24";
+        };
+
+        pinctrl_ext_irq1: ext_irq1 {
+          function = "ext_irq1";
+          pins = "gpio25";
+        };
+
+        pinctrl_ext_irq2: ext_irq2 {
+          function = "ext_irq2";
+          pins = "gpio26";
+        };
+
+        pinctrl_ext_irq3: ext_irq3 {
+          function = "ext_irq3";
+          pins = "gpio27";
+        };
+
+        pinctrl_nand: nand {
+          function = "nand";
+          group = "nand_grp";
+        };
+      };
+    };
Signature · 1 line
2.20.1
#16 lore raw

PATCH v5 9/15 pinctrl: add a pincontrol driver for BCM6362

In reply to Álvaro Fernández Rojas

Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig           |   8 +
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm6362.c | 617 ++++++++++++++++++++++++++
 3 files changed, 626 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6362.c
drivers/pinctrl/bcm/Kconfig +8 -0
index ced7cc6ab44f..d3101d5e750f 100644
@@ -52,6 +52,14 @@ config PINCTRL_BCM6358
 	help
 	   Say Y here to enable the Broadcom BCM6358 GPIO driver.
 
+config PINCTRL_BCM6362
+	bool "Broadcom BCM6362 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM6362 GPIO driver.
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index c3f5b7b2f2f0..b9b09e5b914c 100644
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
 obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
 obj-$(CONFIG_PINCTRL_BCM6358)		+= pinctrl-bcm6358.o
+obj-$(CONFIG_PINCTRL_BCM6362)		+= pinctrl-bcm6362.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm6362.c new file +617 -0

617 lines not on this page · raw message

Signature · 1 line
2.20.1
#17 lore raw

PATCH v5 10/15 dt-bindings: add BCM6368 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6368 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6368-pinctrl.yaml         | 261 ++++++++++++++++++
 1 file changed, 261 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml new file +261 -0
new file mode 100644
index 000000000000..6a289c93d6b4
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6368 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6368-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6368-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data,
+                  serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led,
+                  ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0,
+                  robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb,
+                  pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1,
+                  pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4,
+                  spi_cs5, uart1 ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+                  gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
+                  gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23,
+                  gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
+                  gpio31, uart1_grp ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@10000080 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0x10000080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6368-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm6368-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 38>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_analog_afe_0: analog_afe_0 {
+          function = "analog_afe_0";
+          pins = "gpio0";
+        };
+
+        pinctrl_analog_afe_1: analog_afe_1 {
+          function = "analog_afe_1";
+          pins = "gpio1";
+        };
+
+        pinctrl_sys_irq: sys_irq {
+          function = "sys_irq";
+          pins = "gpio2";
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio3";
+          };
+
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio4";
+          };
+        };
+
+        pinctrl_inet_led: inet_led {
+          function = "inet_led";
+          pins = "gpio5";
+        };
+
+        pinctrl_ephy0_led: ephy0_led {
+          function = "ephy0_led";
+          pins = "gpio6";
+        };
+
+        pinctrl_ephy1_led: ephy1_led {
+          function = "ephy1_led";
+          pins = "gpio7";
+        };
+
+        pinctrl_ephy2_led: ephy2_led {
+          function = "ephy2_led";
+          pins = "gpio8";
+        };
+
+        pinctrl_ephy3_led: ephy3_led {
+          function = "ephy3_led";
+          pins = "gpio9";
+        };
+
+        pinctrl_robosw_led_data: robosw_led_data {
+          function = "robosw_led_data";
+          pins = "gpio10";
+        };
+
+        pinctrl_robosw_led_clk: robosw_led_clk {
+          function = "robosw_led_clk";
+          pins = "gpio11";
+        };
+
+        pinctrl_robosw_led0: robosw_led0 {
+          function = "robosw_led0";
+          pins = "gpio12";
+        };
+
+        pinctrl_robosw_led1: robosw_led1 {
+          function = "robosw_led1";
+          pins = "gpio13";
+        };
+
+        pinctrl_usb_device_led: usb_device_led {
+          function = "usb_device_led";
+          pins = "gpio14";
+        };
+
+        pinctrl_pci: pci {
+          pinctrl_pci_req1: pci_req1 {
+            function = "pci_req1";
+            pins = "gpio16";
+          };
+
+          pinctrl_pci_gnt1: pci_gnt1 {
+            function = "pci_gnt1";
+            pins = "gpio17";
+          };
+
+          pinctrl_pci_intb: pci_intb {
+            function = "pci_intb";
+            pins = "gpio18";
+          };
+
+          pinctrl_pci_req0: pci_req0 {
+            function = "pci_req0";
+            pins = "gpio19";
+          };
+
+          pinctrl_pci_gnt0: pci_gnt0 {
+            function = "pci_gnt0";
+            pins = "gpio20";
+          };
+        };
+
+        pinctrl_pcmcia: pcmcia {
+          pinctrl_pcmcia_cd1: pcmcia_cd1 {
+            function = "pcmcia_cd1";
+            pins = "gpio22";
+          };
+
+          pinctrl_pcmcia_cd2: pcmcia_cd2 {
+            function = "pcmcia_cd2";
+            pins = "gpio23";
+          };
+
+          pinctrl_pcmcia_vs1: pcmcia_vs1 {
+            function = "pcmcia_vs1";
+            pins = "gpio24";
+          };
+
+          pinctrl_pcmcia_vs2: pcmcia_vs2 {
+            function = "pcmcia_vs2";
+            pins = "gpio25";
+          };
+        };
+
+        pinctrl_ebi_cs2: ebi_cs2 {
+          function = "ebi_cs2";
+          pins = "gpio26";
+        };
+
+        pinctrl_ebi_cs3: ebi_cs3 {
+          function = "ebi_cs3";
+          pins = "gpio27";
+        };
+
+        pinctrl_spi_cs2: spi_cs2 {
+          function = "spi_cs2";
+          pins = "gpio28";
+        };
+
+        pinctrl_spi_cs3: spi_cs3 {
+          function = "spi_cs3";
+          pins = "gpio29";
+        };
+
+        pinctrl_spi_cs4: spi_cs4 {
+          function = "spi_cs4";
+          pins = "gpio30";
+        };
+
+        pinctrl_spi_cs5: spi_cs5 {
+          function = "spi_cs5";
+          pins = "gpio31";
+        };
+
+        pinctrl_uart1: uart1 {
+          function = "uart1";
+          group = "uart1_grp";
+        };
+      };
+    };
Signature · 1 line
2.20.1
#18 lore raw

PATCH v5 11/15 pinctrl: add a pincontrol driver for BCM6368

In reply to Álvaro Fernández Rojas

Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig           |   8 +
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm6368.c | 523 ++++++++++++++++++++++++++
 3 files changed, 532 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6368.c
drivers/pinctrl/bcm/Kconfig +8 -0
index d3101d5e750f..aabd4b762aed 100644
@@ -60,6 +60,14 @@ config PINCTRL_BCM6362
 	help
 	   Say Y here to enable the Broadcom BCM6362 GPIO driver.
 
+config PINCTRL_BCM6368
+	bool "Broadcom BCM6368 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM6368 GPIO driver.
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index b9b09e5b914c..a1331bb9680e 100644
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
 obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
 obj-$(CONFIG_PINCTRL_BCM6358)		+= pinctrl-bcm6358.o
 obj-$(CONFIG_PINCTRL_BCM6362)		+= pinctrl-bcm6362.o
+obj-$(CONFIG_PINCTRL_BCM6368)		+= pinctrl-bcm6368.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm6368.c new file +523 -0

523 lines not on this page · raw message

Signature · 1 line
2.20.1
#19 lore raw

PATCH v5 12/15 dt-bindings: add BCM63268 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in the BCM63268 family SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm63268-pinctrl.yaml        | 208 ++++++++++++++++++
 1 file changed, 208 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml new file +208 -0
new file mode 100644
index 000000000000..1668ab567e35
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM63268 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm63268-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm63268-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
+                  hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
+                  vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
+                  nand, gpio35_alt, dectpd, vdsl_phy_override_0,
+                  vdsl_phy_override_1, vdsl_phy_override_2,
+                  vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
+                  gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
+                  dectpd_grp, vdsl_phy_override_0_grp,
+                  vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
+                  vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@100000c0 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0x100000c0 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm63268-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm63268-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 52>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio0";
+          };
+
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio1";
+          };
+        };
+
+        pinctrl_hsspi_cs4: hsspi_cs4 {
+          function = "hsspi_cs4";
+          pins = "gpio16";
+        };
+
+        pinctrl_hsspi_cs5: hsspi_cs5 {
+          function = "hsspi_cs5";
+          pins = "gpio17";
+        };
+
+        pinctrl_hsspi_cs6: hsspi_cs6 {
+          function = "hsspi_cs6";
+          pins = "gpio8";
+        };
+
+        pinctrl_hsspi_cs7: hsspi_cs7 {
+          function = "hsspi_cs7";
+          pins = "gpio9";
+        };
+
+        pinctrl_adsl_spi: adsl_spi {
+          pinctrl_adsl_spi_miso: adsl_spi_miso {
+            function = "adsl_spi_miso";
+            pins = "gpio18";
+          };
+
+          pinctrl_adsl_spi_mosi: adsl_spi_mosi {
+            function = "adsl_spi_mosi";
+            pins = "gpio19";
+          };
+        };
+
+        pinctrl_vreq_clk: vreq_clk {
+          function = "vreq_clk";
+          pins = "gpio22";
+        };
+
+        pinctrl_pcie_clkreq_b: pcie_clkreq_b {
+          function = "pcie_clkreq_b";
+          pins = "gpio23";
+        };
+
+        pinctrl_robosw_led_clk: robosw_led_clk {
+          function = "robosw_led_clk";
+          pins = "gpio30";
+        };
+
+        pinctrl_robosw_led_data: robosw_led_data {
+          function = "robosw_led_data";
+          pins = "gpio31";
+        };
+
+        pinctrl_nand: nand {
+          function = "nand";
+          group = "nand_grp";
+        };
+
+        pinctrl_gpio35_alt: gpio35_alt {
+          function = "gpio35_alt";
+          pin = "gpio35";
+        };
+
+        pinctrl_dectpd: dectpd {
+          function = "dectpd";
+          group = "dectpd_grp";
+        };
+
+        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {
+          function = "vdsl_phy_override_0";
+          group = "vdsl_phy_override_0_grp";
+        };
+
+        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {
+          function = "vdsl_phy_override_1";
+          group = "vdsl_phy_override_1_grp";
+        };
+
+        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {
+          function = "vdsl_phy_override_2";
+          group = "vdsl_phy_override_2_grp";
+        };
+
+        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {
+          function = "vdsl_phy_override_3";
+          group = "vdsl_phy_override_3_grp";
+        };
+
+        pinctrl_dsl_gpio8: dsl_gpio8 {
+          function = "dsl_gpio8";
+          group = "dsl_gpio8";
+        };
+
+        pinctrl_dsl_gpio9: dsl_gpio9 {
+          function = "dsl_gpio9";
+          group = "dsl_gpio9";
+        };
+      };
+    };
Signature · 1 line
2.20.1
#20 lore raw

PATCH v5 13/15 pinctrl: add a pincontrol driver for BCM63268

In reply to Álvaro Fernández Rojas

Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig            |   8 +
 drivers/pinctrl/bcm/Makefile           |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm63268.c | 643 +++++++++++++++++++++++++
 3 files changed, 652 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63268.c
drivers/pinctrl/bcm/Kconfig +8 -0
index aabd4b762aed..186985846120 100644
@@ -68,6 +68,14 @@ config PINCTRL_BCM6368
 	help
 	   Say Y here to enable the Broadcom BCM6368 GPIO driver.
 
+config PINCTRL_BCM63268
+	bool "Broadcom BCM63268 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM63268 GPIO driver.
+
 config PINCTRL_IPROC_GPIO
 	bool "Broadcom iProc GPIO (with PINCONF) driver"
 	depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index a1331bb9680e..4117847fd279 100644
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
 obj-$(CONFIG_PINCTRL_BCM6358)		+= pinctrl-bcm6358.o
 obj-$(CONFIG_PINCTRL_BCM6362)		+= pinctrl-bcm6362.o
 obj-$(CONFIG_PINCTRL_BCM6368)		+= pinctrl-bcm6368.o
+obj-$(CONFIG_PINCTRL_BCM63268)		+= pinctrl-bcm63268.o
 obj-$(CONFIG_PINCTRL_IPROC_GPIO)	+= pinctrl-iproc-gpio.o
 obj-$(CONFIG_PINCTRL_CYGNUS_MUX)	+= pinctrl-cygnus-mux.o
 obj-$(CONFIG_PINCTRL_NS)		+= pinctrl-ns.o
drivers/pinctrl/bcm/pinctrl-bcm63268.c new file +643 -0

643 lines not on this page · raw message

Signature · 1 line
2.20.1
#21 lore raw

PATCH v5 14/15 dt-bindings: add BCM6318 pincontroller binding documentation

In reply to Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6318 SoCs.

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

 .../pinctrl/brcm,bcm6318-pinctrl.yaml         | 187 ++++++++++++++++++
 1 file changed, 187 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml new file +187 -0
new file mode 100644
index 000000000000..979b9d06de15
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM6318 pin controller
+
+maintainers:
+  - Álvaro Fernández Rojas <[email protected]>
+  - Jonas Gorski <[email protected]>
+
+description: |+
+  The pin controller node should be the child of a syscon node.
+
+  Refer to the the bindings described in
+  Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+  compatible:
+    const: brcm,bcm6318-pinctrl
+
+patternProperties:
+  '^gpio$':
+    type: object
+    properties:
+      compatible:
+        const: brcm,bcm6318-gpio
+
+      data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the data register (in bytes).
+
+      dirout:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          Offset in the register map for the dirout register (in bytes).
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+    required:
+      - gpio-controller
+      - gpio-ranges
+      - '#gpio-cells'
+
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        function:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led,
+                  ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led,
+                  serial_led_data, serial_led_clk, inet_act_led, inet_fail_led,
+                  dsl_led, post_fail_led, wlan_wps_led, usb_pwron,
+                  usb_device_led, usb_active ]
+
+        pins:
+          $ref: "/schemas/types.yaml#/definitions/string"
+          enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+                  gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio_cntl@10000080 {
+      compatible = "syscon", "simple-mfd";
+      reg = <0x10000080 0x80>;
+
+      pinctrl: pinctrl {
+        compatible = "brcm,bcm6318-pinctrl";
+
+        gpio {
+          compatible = "brcm,bcm6318-gpio";
+          data = <0xc>;
+          dirout = <0x4>;
+
+          gpio-controller;
+          gpio-ranges = <&pinctrl 0 0 50>;
+          #gpio-cells = <2>;
+        };
+
+        pinctrl_ephy0_spd_led: ephy0_spd_led {
+          function = "ephy0_spd_led";
+          pins = "gpio0";
+        };
+
+        pinctrl_ephy1_spd_led: ephy1_spd_led {
+          function = "ephy1_spd_led";
+          pins = "gpio1";
+        };
+
+        pinctrl_ephy2_spd_led: ephy2_spd_led {
+          function = "ephy2_spd_led";
+          pins = "gpio2";
+        };
+
+        pinctrl_ephy3_spd_led: ephy3_spd_led {
+          function = "ephy3_spd_led";
+          pins = "gpio3";
+        };
+
+        pinctrl_ephy0_act_led: ephy0_act_led {
+          function = "ephy0_act_led";
+          pins = "gpio4";
+        };
+
+        pinctrl_ephy1_act_led: ephy1_act_led {
+          function = "ephy1_act_led";
+          pins = "gpio5";
+        };
+
+        pinctrl_ephy2_act_led: ephy2_act_led {
+          function = "ephy2_act_led";
+          pins = "gpio6";
+        };
+
+        pinctrl_ephy3_act_led: ephy3_act_led {
+          function = "ephy3_act_led";
+          pins = "gpio7";
+        };
+
+        pinctrl_serial_led: serial_led {
+          pinctrl_serial_led_data: serial_led_data {
+            function = "serial_led_data";
+            pins = "gpio6";
+          };
+
+          pinctrl_serial_led_clk: serial_led_clk {
+            function = "serial_led_clk";
+            pins = "gpio7";
+          };
+        };
+
+        pinctrl_inet_act_led: inet_act_led {
+          function = "inet_act_led";
+          pins = "gpio8";
+        };
+
+        pinctrl_inet_fail_led: inet_fail_led {
+          function = "inet_fail_led";
+          pins = "gpio9";
+        };
+
+        pinctrl_dsl_led: dsl_led {
+          function = "dsl_led";
+          pins = "gpio10";
+        };
+
+        pinctrl_post_fail_led: post_fail_led {
+          function = "post_fail_led";
+          pins = "gpio11";
+        };
+
+        pinctrl_wlan_wps_led: wlan_wps_led {
+          function = "wlan_wps_led";
+          pins = "gpio12";
+        };
+
+        pinctrl_usb_pwron: usb_pwron {
+          function = "usb_pwron";
+          pins = "gpio13";
+        };
+
+        pinctrl_usb_device_led: usb_device_led {
+          function = "usb_device_led";
+          pins = "gpio13";
+        };
+
+        pinctrl_usb_active: usb_active {
+          function = "usb_active";
+          pins = "gpio40";
+        };
+      };
+    };
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#22 lore raw

Re: [PATCH v5 14/15] dt-bindings: add BCM6318 pincontroller binding documentation

Quoted 1 line · Álvaro Fernández Rojas

Add binding documentation for the pincontrol core found in BCM6318 SoCs.

In case it's not clear, the same comments apply to all the binding patches.

Quoted 9 lines

---
v5: change Documentation to dt-bindings in commit title
v4: no changes
v3: add new gpio node
v2: remove interrupts

4 versions in a week is a bit much. Give folks time to review things.

Rob

#23 lore raw

PATCH v5 15/15 pinctrl: add a pincontrol driver for BCM6318

In reply to Álvaro Fernández Rojas

Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number.

---
v5: add changes suggested by Andy Shevchenko
v4: no changes
v3: use new shared code
v2: switch to GPIO_REGMAP

 drivers/pinctrl/bcm/Kconfig           |   8 +
 drivers/pinctrl/bcm/Makefile          |   1 +
 drivers/pinctrl/bcm/pinctrl-bcm6318.c | 498 ++++++++++++++++++++++++++
 3 files changed, 507 insertions(+)
 create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6318.c
drivers/pinctrl/bcm/Kconfig +8 -0
index 186985846120..33660e8fec05 100644
@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX
 	select PINCONF
 	select PINMUX
 
+config PINCTRL_BCM6318
+	bool "Broadcom BCM6318 GPIO driver"
+	depends on (BMIPS_GENERIC || COMPILE_TEST)
+	select PINCTRL_BCM63XX
+	default BMIPS_GENERIC
+	help
+	   Say Y here to enable the Broadcom BCM6318 GPIO driver.
+
 config PINCTRL_BCM6328
 	bool "Broadcom BCM6328 GPIO driver"
 	depends on (BMIPS_GENERIC || COMPILE_TEST)
drivers/pinctrl/bcm/Makefile +1 -0
index 4117847fd279..00c7b7775e63 100644
@@ -4,6 +4,7 @@
 obj-$(CONFIG_PINCTRL_BCM281XX)		+= pinctrl-bcm281xx.o
 obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
 obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
+obj-$(CONFIG_PINCTRL_BCM6318)		+= pinctrl-bcm6318.o
 obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
 obj-$(CONFIG_PINCTRL_BCM6358)		+= pinctrl-bcm6358.o
 obj-$(CONFIG_PINCTRL_BCM6362)		+= pinctrl-bcm6362.o
drivers/pinctrl/bcm/pinctrl-bcm6318.c new file +498 -0

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