ARM: dts: aspeed: Updates for Rainier and Everest machines
Subsystems (3)
cover ARM: dts: aspeed: Updates for Rainier and Everest machines
This series updates the device trees for the Rainier and Everest system BMCs. For Rainier, the changes have been tested fairly extensively in hardware. Everest has largely been tested in simulation and some basic hardware verification testing.
Alpana Kumari (3):
ARM: dts: aspeed: rainier: Add presence GPIOs
ARM: dts: aspeed: everest: GPIOs support
ARM: dts: aspeed: rainier: Support pass 2 planar
Brandon Wyman (2):
ARM: dts: aspeed: rainier: Add gpio-keys-polled for fans
ARM: dts: aspeed: everest: Add power supply i2c devices
Eddie James (7):
ARM: dts: aspeed: rainier: Add additional processor CFAMs
ARM: dts: aspeed: rainier: Enable fan watchdog
ARM: dts: aspeed: rainier 4U: Fix fan configuration
ARM: dts: Aspeed: Everest: Add FSI CFAMs and re-number engines
ARM: dts: Aspeed: Everest: Add RTC
ARM: dts: aspeed: everest: Enable fan watchdog
ARM: dts: aspeed: Add Rainier 1S4U machine
Jim Wright (1):
ARM: dts: aspeed: everest: Add UCD90320 power sequencer
Matthew Barth (2):
ARM: dts: Aspeed: Everest: Add max31785 fan controller device
ARM: dts: Aspeed: Everest: Add pca9552 fan presence
PriyangaRamasamy (1):
ARM: dts: aspeed: Everest: Add I2C components
Vishwanatha Subbanna (6):
ARM: dts: aspeed: rainier: Add Operator Panel LEDs
ARM: dts: aspeed: rainier: Add directly controlled LEDs
ARM: dts: aspeed: rainier: Add leds that are off PCA9552
ARM: dts: aspeed: rainier: Add leds that are off pic16f882
ARM: dts: aspeed: rainier: Add leds on optional DASD cards
ARM: dts: aspeed: rainier: Add leds on optional PCI cable cards
arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 1770 +++++++++++- .../boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts | 14 + .../boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts | 198 ++ .../boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 14 + .../boot/dts/aspeed-bmc-ibm-rainier-v2.dts | 198 ++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 2367 +++++++++++++++-- 7 files changed, 4290 insertions(+), 274 deletions(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-v2.dts
Signature · 1 line
2.27.0
PATCH 1/22 ARM: dts: aspeed: rainier: Add Operator Panel LEDs
From: Vishwanatha Subbanna <[email protected]>
These LEDs are on the op-panel and are connected via a pca9551 i2c LED expander.
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
Signed-off-by Joel Stanley <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 82 ++++++++++++++++++++ 1 file changed, 82 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +82 -0
@@ -131,6 +131,38 @@ i2c2mux3: i2c at 3 { reg = <3>; }; }; + + leds { + compatible = "gpio-leds"; + + /* System ID LED that is at front on Op Panel */ + front-sys-id0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca_oppanel 0 GPIO_ACTIVE_LOW>; + }; + + /* System Attention Indicator ID LED that is at front on Op Panel */ + front-check-log0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca_oppanel 1 GPIO_ACTIVE_LOW>; + }; + + /* Enclosure Fault LED that is at front on Op Panel */ + front-enc-fault1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca_oppanel 2 GPIO_ACTIVE_LOW>; + }; + + /* System PowerOn LED that is at front on Op Panel */ + front-sys-pwron0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca_oppanel 3 GPIO_ACTIVE_LOW>; + }; + }; }; &ehci1 {
@@ -849,6 +881,56 @@ ibm-panel at 62 { reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; }; + pca_oppanel: pca9551 at 60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + dps: dps310 at 76 { compatible = "infineon,dps310"; reg = <0x76>;
Signature · 1 line
2.27.0
PATCH 2/22 ARM: dts: aspeed: rainier: Add directly controlled LEDs
In reply to Eddie JamesFrom: Vishwanatha Subbanna <[email protected]>
These LEDs are directly connected to the BMC's GPIO bank.
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
Signed-off-by Joel Stanley <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 24 ++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +22 -2
@@ -135,6 +135,26 @@ i2c2mux3: i2c at 3 { leds { compatible = "gpio-leds"; + /* BMC Card fault LED at the back */ + bmc-ingraham0 { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure ID LED at the back */ + rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + /* System ID LED that is at front on Op Panel */ front-sys-id0 { retain-state-shutdown;
@@ -178,7 +198,7 @@ &gpio0 { /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","","","","","","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", + /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","",
@@ -186,7 +206,7 @@ &gpio0 { /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","pcieslot-power","","","", /*Q0-Q7*/ "cfam-reset","","","","","","","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
Signature · 1 line
2.27.0
PATCH 3/22 ARM: dts: aspeed: rainier: Add gpio-keys-polled for fans
In reply to Eddie JamesFrom: Brandon Wyman <[email protected]>
Add a gpio-keys-polled section to the Rainier device tree for the fan presence signals on the PCA9552 I2C device on bus 7.
Signed-off-by Brandon Wyman <[email protected]>
Signed-off-by Matthew Barth <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 43 ++++++++++++++++++++ 1 file changed, 43 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +43 -0
@@ -183,6 +183,49 @@ front-sys-pwron0 { gpios = <&pca_oppanel 3 GPIO_ACTIVE_LOW>; }; }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca0 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan5-presence { + label = "fan5-presence"; + gpios = <&pca0 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + }; }; &ehci1 {
Signature · 1 line
2.27.0
PATCH 4/22 ARM: dts: aspeed: rainier: Add additional processor CFAMs
In reply to Eddie JamesRainier has two dual-chip modules and therefore four CFAMs with their associated engines. Add these to the devicetree with the i2c busses that have devices on them.
Signed-off-by Eddie James <[email protected]>
Signed-off-by Joel Stanley <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 283 ++++++++++++++++++- 1 file changed, 281 insertions(+), 2 deletions(-)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +281 -2
@@ -12,6 +12,39 @@ / { compatible = "ibm,rainier-bmc", "aspeed,ast2600"; aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + i2c300 = &cfam2_i2c0; + i2c301 = &cfam2_i2c1; + i2c310 = &cfam2_i2c10; + i2c311 = &cfam2_i2c11; + i2c312 = &cfam2_i2c12; + i2c313 = &cfam2_i2c13; + i2c314 = &cfam2_i2c14; + i2c315 = &cfam2_i2c15; + i2c402 = &cfam3_i2c2; + i2c403 = &cfam3_i2c3; + i2c410 = &cfam3_i2c10; + i2c411 = &cfam3_i2c11; + i2c414 = &cfam3_i2c14; + i2c415 = &cfam3_i2c15; + i2c416 = &cfam3_i2c16; + i2c417 = &cfam3_i2c17; + serial4 = &uart5; i2c16 = &i2c2mux0; i2c17 = &i2c2mux1;
@@ -30,6 +63,10 @@ aliases { spi31 = &cfam2_spi1; spi32 = &cfam2_spi2; spi33 = &cfam2_spi3; + spi40 = &cfam3_spi0; + spi41 = &cfam3_spi1; + spi42 = &cfam3_spi2; + spi43 = &cfam3_spi3; }; chosen {
@@ -321,6 +358,38 @@ i2c at 1800 { reg = <0x1800 0x400>; #address-cells = <1>; #size-cells = <0>; + + cfam0_i2c0: i2c-bus at 0 { + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus at 1 { + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; }; fsi2spi at 1c00 {
@@ -412,8 +481,6 @@ fsi_hub0: hub at 3400 { reg = <0x3400 0x400>; #address-cells = <2>; #size-cells = <0>; - - no-scan-on-init; }; }; };
@@ -435,6 +502,38 @@ i2c at 1800 { reg = <0x1800 0x400>; #address-cells = <1>; #size-cells = <0>; + + cfam1_i2c2: i2c-bus at 2 { + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus at 3 { + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + }; }; fsi2spi at 1c00 {
@@ -547,6 +646,38 @@ i2c at 1800 { reg = <0x1800 0x400>; #address-cells = <1>; #size-cells = <0>; + + cfam2_i2c0: i2c-bus at 0 { + reg = <0>; /* OM01 */ + }; + + cfam2_i2c1: i2c-bus at 1 { + reg = <1>; /* OM23 */ + }; + + cfam2_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam2_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam2_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + }; + + cfam2_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + }; + + cfam2_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam2_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; }; fsi2spi at 1c00 {
@@ -642,6 +773,150 @@ fsi_hub2: hub at 3400 { no-scan-on-init; }; }; + + cfam at 3,0 { + reg = <3 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <3>; + + scom at 1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_i2c2: i2c-bus at 2 { + reg = <2>; /* OM45 */ + }; + + cfam3_i2c3: i2c-bus at 3 { + reg = <3>; /* OM67 */ + }; + + cfam3_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam3_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam3_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam3_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + + cfam3_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + }; + + cfam3_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_spi0: spi at 0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi1: spi at 20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi2: spi at 40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi3: spi at 60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ3: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub3: hub at 3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; }; /* Legacy OCC numbering (to get rid of when userspace is fixed) */
@@ -657,6 +932,10 @@ &fsi_occ2 { reg = <3>; }; +&fsi_occ3 { + reg = <4>; +}; + &ibt { status = "okay"; };
Signature · 1 line
2.27.0
PATCH 5/22 ARM: dts: aspeed: rainier: Add leds that are off PCA9552
In reply to Eddie JamesFrom: Vishwanatha Subbanna <[email protected]>
These LEDs are on the fans and are connected via a pca9551 i2c expander.
A comment from Milton on why to expose the pins as GPIOs rather than configuring the pca955x driver to drive the LEDs directly:
The led system insistes on creating a compact map (no holes) (as does the reset subsystem).
However, this means the relative led number for a pin changes as the prior pins change from gpio to led configuration. For example if pins 2 and 7 are leds, they become leds 0 and 1. Changing pin 5 to also be an led means that pin 7 is now led 2 not led 1 on the led subsystem.
The workaround we have done for existing systems has been to use gpio leds for pca family devices.
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +41 -0
@@ -263,6 +263,47 @@ fan5-presence { linux,code = <11>; }; }; + + leds { + compatible = "gpio-leds"; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + }; + + fan4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + }; + + fan5 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + }; + }; + }; &ehci1 {
Signature · 1 line
2.27.0
PATCH 6/22 ARM: dts: aspeed: rainier: Add leds that are off pic16f882
In reply to Eddie JamesFrom: Vishwanatha Subbanna <[email protected]>
There are many LEDs that are connected to PIC16F882. PIC has the software implementation of pca9552
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 690 +++++++++++++++++++ 1 file changed, 690 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +690 -0
@@ -302,6 +302,336 @@ fan5 { default-state = "keep"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; }; + + ddimm0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 0 GPIO_ACTIVE_LOW>; + }; + + ddimm1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 1 GPIO_ACTIVE_LOW>; + }; + + ddimm2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 2 GPIO_ACTIVE_LOW>; + }; + + ddimm3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 3 GPIO_ACTIVE_LOW>; + }; + + ddimm4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 4 GPIO_ACTIVE_LOW>; + }; + + ddimm5 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 5 GPIO_ACTIVE_LOW>; + }; + + ddimm6 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 6 GPIO_ACTIVE_LOW>; + }; + + ddimm7 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 7 GPIO_ACTIVE_LOW>; + }; + + ddimm8 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 8 GPIO_ACTIVE_LOW>; + }; + + ddimm9 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 9 GPIO_ACTIVE_LOW>; + }; + + ddimm10 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 10 GPIO_ACTIVE_LOW>; + }; + + ddimm11 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 11 GPIO_ACTIVE_LOW>; + }; + + ddimm12 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 12 GPIO_ACTIVE_LOW>; + }; + + ddimm13 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 13 GPIO_ACTIVE_LOW>; + }; + + ddimm14 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 14 GPIO_ACTIVE_LOW>; + }; + + ddimm15 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic1 15 GPIO_ACTIVE_LOW>; + }; + + ddimm16 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 0 GPIO_ACTIVE_LOW>; + }; + + ddimm17 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 1 GPIO_ACTIVE_LOW>; + }; + + ddimm18 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 2 GPIO_ACTIVE_LOW>; + }; + + ddimm19 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 3 GPIO_ACTIVE_LOW>; + }; + + ddimm20 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 4 GPIO_ACTIVE_LOW>; + }; + + ddimm21 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 5 GPIO_ACTIVE_LOW>; + }; + + ddimm22 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 6 GPIO_ACTIVE_LOW>; + }; + + ddimm23 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 7 GPIO_ACTIVE_LOW>; + }; + + ddimm24 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 8 GPIO_ACTIVE_LOW>; + }; + + ddimm25 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 9 GPIO_ACTIVE_LOW>; + }; + + ddimm26 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 10 GPIO_ACTIVE_LOW>; + }; + + ddimm27 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 11 GPIO_ACTIVE_LOW>; + }; + + ddimm28 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 12 GPIO_ACTIVE_LOW>; + }; + + ddimm29 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 13 GPIO_ACTIVE_LOW>; + }; + + ddimm30 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 14 GPIO_ACTIVE_LOW>; + }; + + ddimm31 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic2 15 GPIO_ACTIVE_LOW>; + }; + + pcieslot0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 0 GPIO_ACTIVE_LOW>; + }; + + pcieslot1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 1 GPIO_ACTIVE_LOW>; + }; + + pcieslot2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 2 GPIO_ACTIVE_LOW>; + }; + + pcieslot3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 3 GPIO_ACTIVE_LOW>; + }; + + pcieslot4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 4 GPIO_ACTIVE_LOW>; + }; + + cpu1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 5 GPIO_ACTIVE_LOW>; + }; + + cpu1-vrm0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 6 GPIO_ACTIVE_LOW>; + }; + + lcd-russel { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic3 8 GPIO_ACTIVE_LOW>; + }; + + planar { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 0 GPIO_ACTIVE_LOW>; + }; + + cpu0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 1 GPIO_ACTIVE_LOW>; + }; + + dasd-pyramid0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 3 GPIO_ACTIVE_LOW>; + }; + + dasd-pyramid1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 4 GPIO_ACTIVE_LOW>; + }; + + dasd-pyramid2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 5 GPIO_ACTIVE_LOW>; + }; + + cpu0-vrm0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 6 GPIO_ACTIVE_LOW>; + }; + + rtc-battery { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 7 GPIO_ACTIVE_LOW>; + }; + + base-blyth { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 8 GPIO_ACTIVE_LOW>; + }; + + pcieslot6 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 9 GPIO_ACTIVE_LOW>; + }; + + pcieslot7 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 10 GPIO_ACTIVE_LOW>; + }; + + pcieslot8 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 11 GPIO_ACTIVE_LOW>; + }; + + pcieslot9 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 12 GPIO_ACTIVE_LOW>; + }; + + pcieslot10 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 13 GPIO_ACTIVE_LOW>; + }; + + pcieslot11 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 14 GPIO_ACTIVE_LOW>; + }; + + tpm-wilson { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pic4 15 GPIO_ACTIVE_LOW>; + }; }; };
@@ -1314,6 +1644,366 @@ gpio at 7 { }; }; + pic1: pca9952 at 32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pic2: pca9552 at 31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pic3: pca9552 at 30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pic4: pca9552 at 33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + dps: dps310 at 76 { compatible = "infineon,dps310"; reg = <0x76>;
Signature · 1 line
2.27.0
PATCH 7/22 ARM: dts: aspeed: rainier: Add leds on optional DASD cards
In reply to Eddie JamesFrom: Vishwanatha Subbanna <[email protected]>
These cards are not hot pluggable and must be installed prior to boot. LEDs on these are controlled by PCA9552 i2c expander
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 425 +++++++++++++++++++ 1 file changed, 425 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +425 -0
@@ -634,6 +634,161 @@ tpm-wilson { }; }; + leds-optional-dasd-pyramid0 { + compatible = "gpio-leds"; + + nvme0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 0 GPIO_ACTIVE_LOW>; + }; + + nvme1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 1 GPIO_ACTIVE_LOW>; + }; + + nvme2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 2 GPIO_ACTIVE_LOW>; + }; + + nvme3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 3 GPIO_ACTIVE_LOW>; + }; + + nvme4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 4 GPIO_ACTIVE_LOW>; + }; + + nvme5 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 5 GPIO_ACTIVE_LOW>; + }; + + nvme6 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 6 GPIO_ACTIVE_LOW>; + }; + + nvme7 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca2 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds-optional-dasd-pyramid1 { + compatible = "gpio-leds"; + + nvme8 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 0 GPIO_ACTIVE_LOW>; + }; + + nvme9 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 1 GPIO_ACTIVE_LOW>; + }; + + nvme10 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 2 GPIO_ACTIVE_LOW>; + }; + + nvme11 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 3 GPIO_ACTIVE_LOW>; + }; + + nvme12 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 4 GPIO_ACTIVE_LOW>; + }; + + nvme13 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 5 GPIO_ACTIVE_LOW>; + }; + + nvme14 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 6 GPIO_ACTIVE_LOW>; + }; + + nvme15 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca3 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds-optional-dasd-pyramid2 { + compatible = "gpio-leds"; + + nvme16 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 0 GPIO_ACTIVE_LOW>; + }; + + nvme17 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 1 GPIO_ACTIVE_LOW>; + }; + + nvme18 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 2 GPIO_ACTIVE_LOW>; + }; + + nvme19 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 3 GPIO_ACTIVE_LOW>; + }; + + nvme20 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 4 GPIO_ACTIVE_LOW>; + }; + + nvme21 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 5 GPIO_ACTIVE_LOW>; + }; + + nvme22 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 6 GPIO_ACTIVE_LOW>; + }; + + nvme23 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca4 7 GPIO_ACTIVE_LOW>; + }; + }; }; &ehci1 {
@@ -2218,6 +2373,96 @@ eeprom at 50 { compatible = "atmel,24c64"; reg = <0x50>; }; + + pca2: pca9552 at 60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c14 {
@@ -2227,6 +2472,96 @@ eeprom at 50 { compatible = "atmel,24c64"; reg = <0x50>; }; + + pca3: pca9552 at 60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c15 {
@@ -2236,6 +2571,96 @@ eeprom at 50 { compatible = "atmel,24c64"; reg = <0x50>; }; + + pca4: pca9552 at 60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &vuart1 {
Signature · 1 line
2.27.0
PATCH 8/22 ARM: dts: aspeed: rainier: Add leds on optional PCI cable cards
In reply to Eddie JamesFrom: Vishwanatha Subbanna <[email protected]>
These are LEDs on the cable cards that plug into PCIE slots. The LEDs are controlled by pca9552 i2c expander
Signed-off-by Vishwanatha Subbanna <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 264 +++++++++++++++++++ 1 file changed, 264 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +264 -0
@@ -789,6 +789,70 @@ nvme23 { gpios = <&pca4 7 GPIO_ACTIVE_LOW>; }; }; + + leds-optional-cablecard0 { + compatible = "gpio-leds"; + + cablecard0-cxp-top { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca5 0 GPIO_ACTIVE_LOW>; + }; + + cablecard0-cxp-bot { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca5 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds-optional-cablecard3 { + compatible = "gpio-leds"; + + cablecard3-cxp-top { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca6 0 GPIO_ACTIVE_LOW>; + }; + + cablecard3-cxp-bot { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca6 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds-optional-cablecard4 { + compatible = "gpio-leds"; + + cablecard4-cxp-top { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca7 0 GPIO_ACTIVE_LOW>; + }; + + cablecard4-cxp-bot { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca7 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds-optional-cablecard10 { + compatible = "gpio-leds"; + + cablecard10-cxp-top { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca8 0 GPIO_ACTIVE_LOW>; + }; + + cablecard10-cxp-bot { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca8 1 GPIO_ACTIVE_LOW>; + }; + }; }; &ehci1 {
@@ -1544,6 +1608,56 @@ eeprom at 52 { compatible = "atmel,24c64"; reg = <0x52>; }; + + pca5: pca9551 at 60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c5 {
@@ -1568,6 +1682,106 @@ eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>; }; + + pca6: pca9551 at 60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + pca7: pca9551 at 61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c6 {
@@ -2360,6 +2574,56 @@ eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>; }; + + pca8: pca9551 at 60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c12 {
Signature · 1 line
2.27.0
PATCH 9/22 ARM: dts: aspeed: rainier: Add presence GPIOs
In reply to Eddie JamesFrom: Alpana Kumari <[email protected]>
This commit adds presence detect GPIO chips for various FRUs on Rainier. Also, correct the I2C address for the tca9554.
Signed-off-by Alpana Kumari <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 169 ++++++++++++++++++- 1 file changed, 160 insertions(+), 9 deletions(-)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +160 -9
@@ -1538,20 +1538,64 @@ eeprom at 51 { reg = <0x51>; }; - tca9554 at 40 { + tca_pres1: tca9554 at 20{ compatible = "ti,tca9554"; - reg = <0x40>; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; #gpio-cells = <2>; - smbus0-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus0"; + gpio-line-names = "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "DASD_BP2_PRESENT_N", + "DASD_BP1_PRESENT_N", + "DASD_BP0_PRESENT_N"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; - }; + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c1 {
@@ -1574,6 +1618,104 @@ power-supply at 69 { compatible = "ibm,cffps"; reg = <0x69>; }; + + pca_pres1: pca9552 at 61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLOT0_PRSNT_EN_RSVD", "SLOT1_PRSNT_EN_RSVD", + "SLOT2_PRSNT_EN_RSVD", "SLOT3_PRSNT_EN_RSVD", + "SLOT4_PRSNT_EN_RSVD", "SLOT0_EXPANDER_PRSNT_N", + "SLOT1_EXPANDER_PRSNT_N", "SLOT2_EXPANDER_PRSNT_N", + "SLOT3_EXPANDER_PRSNT_N", "SLOT4_EXPANDER_PRSNT_N", + "", "", "", "", "", ""; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c4 {
@@ -2423,7 +2565,7 @@ eeprom at 51 { reg = <0x51>; }; - pca1: pca9552 at 61 { + pca_pres3: pca9552 at 61 { compatible = "nxp,pca9552"; reg = <0x61>; #address-cells = <1>;
@@ -2431,6 +2573,15 @@ pca1: pca9552 at 61 { gpio-controller; #gpio-cells = <2>; + gpio-line-names = + "SLOT6_PRSNT_EN_RSVD", "SLOT7_PRSNT_EN_RSVD", + "SLOT8_PRSNT_EN_RSVD", "SLOT9_PRSNT_EN_RSVD", + "SLOT10_PRSNT_EN_RSVD", "SLOT11_PRSNT_EN_RSVD", + "SLOT6_EXPANDER_PRSNT_N", "SLOT7_EXPANDER_PRSNT_N", + "SLOT8_EXPANDER_PRSNT_N", "SLOT9_EXPANDER_PRSNT_N", + "SLOT10_EXPANDER_PRSNT_N", "SLOT11_EXPANDER_PRSNT_N", + "", "", "", ""; + gpio at 0 { reg = <0>; type = <PCA955X_TYPE_GPIO>;
Signature · 1 line
2.27.0
PATCH 10/22 ARM: dts: aspeed: rainier: Enable fan watchdog
In reply to Eddie JamesSet watchdog 1 to pulse the fan watchdog circuit that drives the FAULT pin of the MAX31785, resulting in fans running at full speed, if at any point the BMC stops pulsing it, such as a BMC reboot at runtime. Enable watchdog 2 for BMC reboots.
Signed-off-by Matthew Barth <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +14 -0
@@ -3135,6 +3135,20 @@ flash at 0 { }; }; +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + &xdma { status = "okay"; memory-region = <&vga_memory>;
Signature · 1 line
2.27.0
PATCH 11/22 ARM: dts: aspeed: rainier 4U: Fix fan configuration
In reply to Eddie JamesThe 4U fans didn't have the correct properties since the fan nodes were redefined. Fix this by referencing each fan individually and adding the differences to the 4U fans.
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts +14 -0
@@ -22,16 +22,30 @@ power-supply at 6b { &fan0 { tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; }; &fan1 { tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; }; &fan2 { tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; }; &fan3 { tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; +}; + +&fan4 { + tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; +}; + +&fan5 { + tach-pulses = <4>; + /delete-property/ maxim,fan-dual-tach; };
Signature · 1 line
2.27.0
kernel test robot
build bot[PATCH 11/22] ARM: dts: aspeed: rainier 4U: Fix fan configuration
I love your patch! Yet something to improve:
Hi Eddie,
I love your patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on v5.12-rc5 next-20210329]
[cannot apply to joel-aspeed/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Eddie-James/ARM-dts-aspeed-Updates-for-Rainier-and-Everest-machines/20210329-230220 base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/9c182646738dfcf45429b03a326f2b1bcef985ef
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Eddie-James/ARM-dts-aspeed-Updates-for-Rainier-and-Everest-machines/20210329-230220 git checkout 9c182646738dfcf45429b03a326f2b1bcef985ef
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts:43.1-6 Label or path fan4 not found >> Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts:48.1-6 Label or path fan5 not found
FATAL ERROR: Syntax error parsing input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org
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PATCH 12/22 ARM: dts: aspeed: Everest: Add I2C components
In reply to Eddie JamesFrom: PriyangaRamasamy <[email protected]>
Tested and able to bound the devices with i2c driver.
Signed-off-by PriyangaRamasamy <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 408 +++++++++++++++++++ 1 file changed, 408 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +408 -0
@@ -45,6 +45,25 @@ aliases { i2c416 = &cfam3_i2c16; i2c417 = &cfam3_i2c17; + i2c16 = &i2c4mux0chn0; + i2c17 = &i2c4mux0chn1; + i2c18 = &i2c4mux0chn2; + i2c19 = &i2c5mux0chn0; + i2c20 = &i2c5mux0chn1; + i2c21 = &i2c5mux0chn2; + i2c22 = &i2c5mux0chn3; + i2c23 = &i2c6mux0chn0; + i2c24 = &i2c6mux0chn1; + i2c25 = &i2c6mux0chn2; + i2c26 = &i2c6mux0chn3; + i2c27 = &i2c14mux0chn0; + i2c28 = &i2c14mux0chn1; + i2c29 = &i2c14mux0chn2; + i2c30 = &i2c14mux1chn0; + i2c31 = &i2c14mux1chn1; + i2c32 = &i2c14mux1chn2; + i2c33 = &i2c14mux1chn3; + serial4 = &uart5; spi10 = &cfam0_spi0;
@@ -105,6 +124,395 @@ vga_memory: region at bf000000 { }; }; +&i2c0 { + status = "okay"; + + eeprom at 51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + eeprom at 54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c4 { + status = "okay"; + + i2c-switch at 70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom at 52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + + i2c4mux0chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c4mux0chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom at 51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-switch at 70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c5mux0chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c5mux0chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom at 51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + + i2c5mux0chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom at 52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + + i2c5mux0chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom at 53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + i2c-switch at 70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c6mux0chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c6mux0chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom at 52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + + i2c6mux0chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom at 53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + }; + + i2c6mux0chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom at 51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + eeprom at 51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom at 50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + + eeprom at 50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom at 51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom at 53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom at 52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom at 51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom at 50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom at 53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom at 52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c11 { + status = "okay"; + + eeprom at 51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom at 50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom at 53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom at 52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + + eeprom at 51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom at 50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom at 53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + eeprom at 52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; +}; + +&i2c14 { + status = "okay"; + + i2c-switch at 70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c14mux0chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c14mux0chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom at 51 { + compatible = "atmel,24c32"; + reg = <0x51>; + }; + }; + + i2c14mux0chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom at 50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; + + i2c-switch at 71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c14mux1chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom at 50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom at 50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom at 50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c14mux1chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom at 50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + +&i2c15 { + status = "okay"; +}; + &ehci1 { status = "okay"; };
Signature · 1 line
2.27.0
PATCH 13/22 ARM: dts: Aspeed: Everest: Add max31785 fan controller device
In reply to Eddie JamesFrom: Matthew Barth <[email protected]>
Add the max31785 configuration at address 0x52 on i2c14 behind mux0 channel 3.
Signed-off-by Matthew Barth <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 71 ++++++++++++++++++-- 1 file changed, 67 insertions(+), 4 deletions(-)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +67 -4
@@ -59,10 +59,11 @@ aliases { i2c27 = &i2c14mux0chn0; i2c28 = &i2c14mux0chn1; i2c29 = &i2c14mux0chn2; - i2c30 = &i2c14mux1chn0; - i2c31 = &i2c14mux1chn1; - i2c32 = &i2c14mux1chn2; - i2c33 = &i2c14mux1chn3; + i2c30 = &i2c14mux0chn3; + i2c31 = &i2c14mux1chn0; + i2c32 = &i2c14mux1chn1; + i2c33 = &i2c14mux1chn2; + i2c34 = &i2c14mux1chn3; serial4 = &uart5;
@@ -457,6 +458,68 @@ eeprom at 50 { reg = <0x50>; }; }; + + i2c14mux0chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + max31785 at 52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + + fan at 0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan at 1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan at 2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan at 3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + }; }; i2c-switch at 71 {
Signature · 1 line
2.27.0
PATCH 14/22 ARM: dts: Aspeed: Everest: Add FSI CFAMs and re-number engines
In reply to Eddie JamesAdd additional CFAMs and re-number the existing engines for the extra processors present on the Everest system.
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 648 ++++++++++++++++++- 1 file changed, 644 insertions(+), 4 deletions(-)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +644 -4
@@ -44,6 +44,38 @@ aliases { i2c415 = &cfam3_i2c15; i2c416 = &cfam3_i2c16; i2c417 = &cfam3_i2c17; + i2c500 = &cfam4_i2c0; + i2c501 = &cfam4_i2c1; + i2c510 = &cfam4_i2c10; + i2c511 = &cfam4_i2c11; + i2c512 = &cfam4_i2c12; + i2c513 = &cfam4_i2c13; + i2c514 = &cfam4_i2c14; + i2c515 = &cfam4_i2c15; + i2c602 = &cfam5_i2c2; + i2c603 = &cfam5_i2c3; + i2c610 = &cfam5_i2c10; + i2c611 = &cfam5_i2c11; + i2c614 = &cfam5_i2c14; + i2c615 = &cfam5_i2c15; + i2c616 = &cfam5_i2c16; + i2c617 = &cfam5_i2c17; + i2c700 = &cfam6_i2c0; + i2c701 = &cfam6_i2c1; + i2c710 = &cfam6_i2c10; + i2c711 = &cfam6_i2c11; + i2c712 = &cfam6_i2c12; + i2c713 = &cfam6_i2c13; + i2c714 = &cfam6_i2c14; + i2c715 = &cfam6_i2c15; + i2c802 = &cfam7_i2c2; + i2c803 = &cfam7_i2c3; + i2c810 = &cfam7_i2c10; + i2c811 = &cfam7_i2c11; + i2c814 = &cfam7_i2c14; + i2c815 = &cfam7_i2c15; + i2c816 = &cfam7_i2c16; + i2c817 = &cfam7_i2c17; i2c16 = &i2c4mux0chn0; i2c17 = &i2c4mux0chn1;
@@ -83,6 +115,22 @@ aliases { spi41 = &cfam3_spi1; spi42 = &cfam3_spi2; spi43 = &cfam3_spi3; + spi50 = &cfam4_spi0; + spi51 = &cfam4_spi1; + spi52 = &cfam4_spi2; + spi53 = &cfam4_spi3; + spi60 = &cfam5_spi0; + spi61 = &cfam5_spi1; + spi62 = &cfam5_spi2; + spi63 = &cfam5_spi3; + spi70 = &cfam6_spi0; + spi71 = &cfam6_spi1; + spi72 = &cfam6_spi2; + spi73 = &cfam6_spi3; + spi80 = &cfam7_spi0; + spi81 = &cfam7_spi1; + spi82 = &cfam7_spi2; + spi83 = &cfam7_spi3; }; chosen {
@@ -604,7 +652,7 @@ &fsim0 { */ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - cfam at 0,0 { + cfam at 0,0 { /* DCM0_C0 */ reg = <0 0>; #address-cells = <1>; #size-cells = <1>;
@@ -748,7 +796,7 @@ fsi_hub0: hub at 3400 { }; &fsi_hub0 { - cfam at 1,0 { + cfam at 1,0 { /* DCM0_C1 */ reg = <1 0>; #address-cells = <1>; #size-cells = <1>;
@@ -892,7 +940,7 @@ fsi_hub1: hub at 3400 { }; }; - cfam at 2,0 { + cfam at 2,0 { /* DCM1_C0 */ reg = <2 0>; #address-cells = <1>; #size-cells = <1>;
@@ -1036,7 +1084,7 @@ fsi_hub2: hub at 3400 { }; }; - cfam at 3,0 { + cfam at 3,0 { /* DCM1_C1 */ reg = <3 0>; #address-cells = <1>; #size-cells = <1>;
@@ -1179,6 +1227,582 @@ fsi_hub3: hub at 3400 { no-scan-on-init; }; }; + + cfam at 4,0 { /* DCM2_C0 */ + reg = <4 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <4>; + + scom at 1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam4_i2c0: i2c-bus at 0 { + reg = <0>; /* OM01 */ + }; + + cfam4_i2c1: i2c-bus at 1 { + reg = <1>; /* OM23 */ + }; + + cfam4_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam4_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam4_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + }; + + cfam4_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + }; + + cfam4_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam4_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam4_spi0: spi at 0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi1: spi at 20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi2: spi at 40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam4_spi3: spi at 60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ4: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub4: hub at 3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam at 5,0 { /* DCM2_C1 */ + reg = <5 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <5>; + + scom at 1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam5_i2c2: i2c-bus at 2 { + reg = <2>; /* OM45 */ + }; + + cfam5_i2c3: i2c-bus at 3 { + reg = <3>; /* OM67 */ + }; + + cfam5_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam5_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam5_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam5_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + + cfam5_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + }; + + cfam5_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam5_spi0: spi at 0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi1: spi at 20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi2: spi at 40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam5_spi3: spi at 60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ5: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub5: hub at 3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam at 6,0 { /* DCM3_C0 */ + reg = <6 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <6>; + + scom at 1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam6_i2c0: i2c-bus at 0 { + reg = <0>; /* OM01 */ + }; + + cfam6_i2c1: i2c-bus at 1 { + reg = <1>; /* OM23 */ + }; + + cfam6_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam6_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam6_i2c12: i2c-bus at c { + reg = <12>; /* OP4A */ + }; + + cfam6_i2c13: i2c-bus at d { + reg = <13>; /* OP4B */ + }; + + cfam6_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam6_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam6_spi0: spi at 0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi1: spi at 20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi2: spi at 40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam6_spi3: spi at 60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ6: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub6: hub at 3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam at 7,0 { /* DCM3_C1 */ + reg = <7 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <7>; + + scom at 1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c at 1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam7_i2c2: i2c-bus at 2 { + reg = <2>; /* OM45 */ + }; + + cfam7_i2c3: i2c-bus at 3 { + reg = <3>; /* OM67 */ + }; + + cfam7_i2c10: i2c-bus at a { + reg = <10>; /* OP3A */ + }; + + cfam7_i2c11: i2c-bus at b { + reg = <11>; /* OP3B */ + }; + + cfam7_i2c14: i2c-bus at e { + reg = <14>; /* OP5A */ + }; + + cfam7_i2c15: i2c-bus at f { + reg = <15>; /* OP5B */ + }; + + cfam7_i2c16: i2c-bus at 10 { + reg = <16>; /* OP6A */ + }; + + cfam7_i2c17: i2c-bus at 11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi at 1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam7_spi0: spi at 0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi1: spi at 20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi2: spi at 40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam7_spi3: spi at 60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom at 0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo at 2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ7: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub7: hub at 3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; }; /* Legacy OCC numbering (to get rid of when userspace is fixed) */
@@ -1198,6 +1822,22 @@ &fsi_occ3 { reg = <4>; }; +&fsi_occ4 { + reg = <5>; +}; + +&fsi_occ5 { + reg = <6>; +}; + +&fsi_occ6 { + reg = <7>; +}; + +&fsi_occ7 { + reg = <8>; +}; + &ibt { status = "okay"; };
Signature · 1 line
2.27.0
PATCH 15/22 ARM: dts: Aspeed: Everest: Add pca9552 fan presence
In reply to Eddie JamesFrom: Matthew Barth <[email protected]>
Add the pca9552 at address 0x61 on i2c14 behind mux0 channel 3 with the 4 GPIO fan presence inputs.
Signed-off-by Matthew Barth <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 128 +++++++++++++++++++ 1 file changed, 128 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +128 -0
@@ -171,6 +171,37 @@ vga_memory: region at bf000000 { reg = <0xbf000000 0x01000000>; /* 16M */ }; }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 15 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + }; }; &i2c0 {
@@ -567,6 +598,103 @@ fan at 3 { maxim,fan-fault-pin-mon; }; }; + + pca0: pca9552 at 61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","","", + "","","","", + "","","","", + "presence-fan3", + "presence-fan2", + "presence-fan1", + "presence-fan0"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; };
Signature · 1 line
2.27.0
PATCH 15/22 ARM: dts: Aspeed: Everest: Add pca9552 fan presence
Quoted 7 lines · Eddie James
From: Matthew Barth <[email protected]>
Add the pca9552 at address
0x61on i2c14 behind mux0 channel 3 with the 4 GPIO fan presence inputs.Signed-off-by Matthew Barth <[email protected]>Signed-off-by Eddie James <[email protected]>
Reviewed-by Brandon Wyman <[email protected]>
Quoted 150 lines
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 128 +++++++++++++++++++ 1 file changed, 128 insertions(+)arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +128
-0@@ -171,6 +171,37 @@ vga_memory: region at bf000000 { reg = <0xbf000000 0x01000000>; /* 16M */ }; }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 15 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + }; }; &i2c0 {@@ -567,6 +598,103 @@ fan at 3 { maxim,fan-fault-pin-mon; }; }; + + pca0: pca9552 at 61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","","", + "","","","", + "","","","", + "presence-fan3", + "presence-fan2", + "presence-fan1", + "presence-fan0"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; };
PATCH 16/22 ARM: dts: aspeed: everest: Add power supply i2c devices
In reply to Eddie JamesFrom: Brandon Wyman <[email protected]>
Add the i2c/pmbus power supply devices to the everest device tree.
Signed-off-by Brandon Wyman <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +20 -0
@@ -228,6 +228,26 @@ eeprom at 54 { compatible = "atmel,24c128"; reg = <0x54>; }; + + power-supply at 68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; + + power-supply at 69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply at 6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply at 6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; }; &i2c4 {
Signature · 1 line
2.27.0
PATCH 17/22 ARM: dts: aspeed: everest: Add UCD90320 power sequencer
In reply to Eddie JamesFrom: Jim Wright <[email protected]>
Add UCD90320 chip to Everest device tree.
Signed-off-by Jim Wright <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +5 -0
@@ -406,6 +406,11 @@ &i2c7 { &i2c8 { status = "okay"; + ucd90320 at 11 { + compatible = "ti,ucd90320"; + reg = <0x11>; + }; + eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>;
Signature · 1 line
2.27.0
PATCH 18/22 ARM: dts: aspeed: everest: GPIOs support
In reply to Eddie JamesFrom: Alpana Kumari <[email protected]>
This commit adds support for-
- Presence GPIOs
- I2C control GPIOs
- Op-panel GPIOs (ex PHR)
Signed-off-by Alpana Kumari <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 297 +++++++++++++++++++ 1 file changed, 297 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +297 -0
@@ -204,6 +204,37 @@ fan3-presence { }; }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", + "PIN_HOLE_RESET_OUT_N","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + &i2c0 { status = "okay";
@@ -211,10 +242,276 @@ eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>; }; + + pca1: pca9552 at 62 { + compatible = "nxp,pca9552"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-ps0", + "presence-ps1", + "presence-ps2", + "presence-ps3", + "presence-pdb", + "presence-tpm", + "", "", + "presence-cp0", + "presence-cp1", + "presence-cp2", + "presence-cp3", + "presence-dasd", + "presence-lcd-op", + "presence-base-op", + ""; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 01 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c1 { status = "okay"; + + pca2: pca9552 at 61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card1", + "presence-cable-card2", + "presence-cable-card3", + "presence-cable-card4", + "presence-cable-card5", + "expander-cable-card1", + "expander-cable-card2", + "expander-cable-card3", + "expander-cable-card4", + "expander-cable-card5"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + + pca3: pca9552 at 62 { + compatible = "nxp,pca9552"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card6", + "presence-cable-card7", + "presence-cable-card8", + "presence-cable-card9", + "presence-cable-card10", + "presence-cable-card11", + "expander-cable-card6", + "expander-cable-card7", + "expander-cable-card8", + "expander-cable-card9", + "expander-cable-card10", + "expander-cable-card11"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + }; &i2c2 {
Signature · 1 line
2.27.0
PATCH 18/22 ARM: dts: aspeed: everest: GPIOs support
Quoted 9 lines · Eddie James
From: Alpana Kumari <[email protected]>
This commit adds support for-
- Presence GPIOs
- I2C control GPIOs
- Op-panel GPIOs (ex PHR)Signed-off-by Alpana Kumari <[email protected]>Signed-off-by Eddie James <[email protected]>
Reviewed-by Brandon Wyman <[email protected]>
Quoted 323 lines
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 297 +++++++++++++++++++ 1 file changed, 297 insertions(+)arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +297
-0@@ -204,6 +204,37 @@ fan3-presence { }; }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "USERSPACE_RSTIND_BUFF","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", + "PIN_HOLE_RESET_OUT_N","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + &i2c0 { status = "okay";@@ -211,10 +242,276 @@ eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>; }; + + pca1: pca9552 at 62 { + compatible = "nxp,pca9552"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-ps0", + "presence-ps1", + "presence-ps2", + "presence-ps3", + "presence-pdb", + "presence-tpm", + "", "", + "presence-cp0", + "presence-cp1", + "presence-cp2", + "presence-cp3", + "presence-dasd", + "presence-lcd-op", + "presence-base-op", + ""; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 01 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; &i2c1 { status = "okay"; + + pca2: pca9552 at 61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card1", + "presence-cable-card2", + "presence-cable-card3", + "presence-cable-card4", + "presence-cable-card5", + "expander-cable-card1", + "expander-cable-card2", + "expander-cable-card3", + "expander-cable-card4", + "expander-cable-card5"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + + pca3: pca9552 at 62 { + compatible = "nxp,pca9552"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-cable-card6", + "presence-cable-card7", + "presence-cable-card8", + "presence-cable-card9", + "presence-cable-card10", + "presence-cable-card11", + "expander-cable-card6", + "expander-cable-card7", + "expander-cable-card8", + "expander-cable-card9", + "expander-cable-card10", + "expander-cable-card11"; + + gpio at 0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio at 11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + }; &i2c2 {
PATCH 19/22 ARM: dts: Aspeed: Everest: Add RTC
In reply to Eddie JamesAdd the RTC at the appropriate I2C bus and address.
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +5 -0
@@ -708,6 +708,11 @@ ucd90320 at 11 { reg = <0x11>; }; + rtc at 32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + eeprom at 51 { compatible = "atmel,24c64"; reg = <0x51>;
Signature · 1 line
2.27.0
PATCH 20/22 ARM: dts: aspeed: everest: Enable fan watchdog
In reply to Eddie JamesSet watchdog 1 to pulse the fan watchdog circuit that drives the FAULT pin of the MAX31785, resulting in fans running at full speed, if at any point the BMC stops pulsing it, such as a BMC reboot at runtime. Enable watchdog 2 for BMC reboots.
Signed-off-by Matthew Barth <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +14 -0
@@ -2335,6 +2335,20 @@ &mac3 { use-ncsi; }; +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + &xdma { status = "okay"; memory-region = <&vga_memory>;
Signature · 1 line
2.27.0
PATCH 20/22 ARM: dts: aspeed: everest: Enable fan watchdog
Quoted 7 lines · Eddie James
Set watchdog 1 to pulse the fan watchdog circuit that drives the FAULT pin of the MAX31785, resulting in fans running at full speed, if at any point the BMC stops pulsing it, such as a BMC reboot at runtime. Enable watchdog 2 for BMC reboots.
Signed-off-by Matthew Barth <[email protected]>Signed-off-by Eddie James <[email protected]>
Acked-by Andrew Jeffery <[email protected]>
PATCH 21/22 ARM: dts: aspeed: rainier: Support pass 2 planar
In reply to Eddie JamesFrom: Alpana Kumari <[email protected]>
Add device trees for the second version of the Rainier system planar. Include the original dts and make the necessary changes.
Signed-off-by Alpana Kumari <[email protected]>
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts | 198 ++++++++++++++++++ .../boot/dts/aspeed-bmc-ibm-rainier-v2.dts | 198 ++++++++++++++++++ 3 files changed, 398 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-v2.dts
arch/arm/boot/dts/Makefile +2 -0
@@ -1423,7 +1423,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-v2.dtb \ aspeed-bmc-ibm-rainier-4u.dtb \ + aspeed-bmc-ibm-rainier-4u-v2.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-lenovo-hr630.dtb \
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts new file +198 -0
198 lines not on this page · raw message
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-v2.dts new file +198 -0
198 lines not on this page · raw message
Signature · 1 line
2.27.0
kernel test robot
build bot[PATCH 21/22] ARM: dts: aspeed: rainier: Support pass 2 planar
Thank you for the patch! Yet something to improve:
Hi Eddie,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on v5.12-rc5 next-20210329]
[cannot apply to joel-aspeed/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Eddie-James/ARM-dts-aspeed-Updates-for-Rainier-and-Everest-machines/20210329-230220 base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/e45f3d6d046417dad1c26e949e98c8209b940027
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Eddie-James/ARM-dts-aspeed-Updates-for-Rainier-and-Everest-machines/20210329-230220 git checkout e45f3d6d046417dad1c26e949e98c8209b940027
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-v2.dts:68.1-6 syntax error
FATAL ERROR: Unable to parse input tree
--
Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts:43.1-6 Label or path fan4 not found
Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts:48.1-6 Label or path fan5 not found
>> Error: arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u-v2.dts:68.1-6 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org
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PATCH 22/22 ARM: dts: aspeed: Add Rainier 1S4U machine
In reply to Eddie JamesThe 1S4U version of the Rainier system has only 4 fans. Create a new tree, include the 4U version, and delete the 2 extra fans.
Signed-off-by Eddie James <[email protected]>
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts | 14 ++++++++++++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 2 +- 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -1424,6 +1424,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-ibm-rainier-v2.dtb \ + aspeed-bmc-ibm-rainier-1s4u.dtb \ aspeed-bmc-ibm-rainier-4u.dtb \ aspeed-bmc-ibm-rainier-4u-v2.dtb \ aspeed-bmc-intel-s2600wf.dtb \
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts new file +14 -0
@@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier-4u-v2.dts" + +/ { + model = "Rainier 1S4U"; +}; + +&max { + /delete-node/ fan4; + /delete-node/ fan5; +};
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +1 -1
@@ -1979,7 +1979,7 @@ tmp275 at 48 { reg = <0x48>; }; - max31785 at 52 { + max: max31785 at 52 { compatible = "maxim,max31785a"; reg = <0x52>; #address-cells = <1>;
Signature · 1 line
2.27.0
Joel Stanley
maintainercover ARM: dts: aspeed: Updates for Rainier and Everest machines
In reply to Eddie JamesQuoted 7 lines · Eddie James
This series updates the device trees for the Rainier and Everest system BMCs. For Rainier, the changes have been tested fairly extensively in hardware. Everest has largely been tested in simulation and some basic hardware verification testing.
ARM: dts: aspeed: rainier: Support pass 2 planar
This patch does not build, suggesting it has not been tested. I fixed it by adding the extra fan nodes that rainier was missing.
How about we support only the latest planar in the mainline tree, and support for older versions can be carried in the downstream tree?
Quoted 1 line
ARM: dts: Aspeed: Everest: Add max31785 fan controller device
This has been applied, but without the properties that are not upstream.
Quoted 5 lines
ARM: dts: aspeed: rainier: Add Operator Panel LEDs
ARM: dts: aspeed: rainier: Add leds that are off PCA9552
ARM: dts: aspeed: rainier: Add leds that are off pic16f882
ARM: dts: aspeed: rainier: Add leds on optional DASD cards
ARM: dts: aspeed: rainier: Add leds on optional PCI cable cards
These need to be re-worked to use the PCA driver directly instead of exposing PCA LED devices as GPIO controllers and then attaching gpio-leds to those GPIOs.
Country to previous concerns raised, there was no issue with "holes" in the layout but instead a desire to avoid the "pca955x:" prefix in sysfs. For now userspace will ignore that prefix when matching devices. I also have a proposed patch to remove them:
https://lore.kernel.org/linux-leds/20210325005456.152469-1-joel at jms.id.au/
The changes I have merged have been pushed here. Please double check that I've merged what you expected:
https://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git/log/?h=for-next
Cheers,
Joel