NVIDIA Tegra memory improvements

PATCH Applied Dmitry Osipenko 3 participants 19 messages Mar 30, 2021 – Apr 4, 2021

Subsystems (3)

Device tree bindings Tegra architecture support Memory controller drivers

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Dmitry Osipenko

author

2021-03-30 23:06 UTC #0 lore raw

v2 cover NVIDIA Tegra memory improvements

Hi,

This series replaces the raw voltage regulator with a power domain that will be managing SoC core voltage. The core power domain patches are still under review, but it's clear at this point that this is the way we will implement the DVFS support.

The remaining Tegra20 memory bindings are converted to schema. I also made a small improvement to the memory drivers.

Changelog:

v2: - Fixed typos in the converted schemas.
- Corrected reg entry of tegra20-mc-gart schema to use fixed number of items.
- Made power-domain to use maxItems instead of $ref phandle in schemas.

Dmitry Osipenko (6):
dt-bindings: memory: tegra20: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra30: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra124: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra20: mc: Convert to schema
dt-bindings: memory: tegra20: emc: Convert to schema
memory: tegra: Print out info-level once per driver probe

 .../nvidia,tegra124-emc.yaml                  |   7 +-
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 .../memory-controllers/nvidia,tegra20-mc.txt  |  40 ---
 .../memory-controllers/nvidia,tegra20-mc.yaml |  79 +++++
 .../nvidia,tegra30-emc.yaml                   |   7 +-
 drivers/memory/tegra/tegra124-emc.c           |  12 +-
 drivers/memory/tegra/tegra20-emc.c            |  20 +-
 drivers/memory/tegra/tegra30-emc.c            |  18 +-
 9 files changed, 406 insertions(+), 201 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

Signature · 1 line

2.30.2

Dmitry Osipenko

author

2021-03-30 23:06 UTC #1 lore raw

PATCH v2 1/6 dt-bindings: memory: tegra20: emc: Replace core regulator with power domain

Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/memory-controllers/nvidia,tegra20-emc.txt        | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +2 -2

index cc443fcf4bec..d2250498c36d 100644
@@ -23,7 +23,7 @@ For each opp entry in 'operating-points-v2' table:
 	matches, the OPP gets enabled.
 
 Optional properties:
-- core-supply: Phandle of voltage regulator of the SoC "core" power domain.
+- power-domains: Phandle of the SoC "core" power domain.
 
 Child device nodes describe the memory settings for different configurations and clock rates.

@@ -48,7 +48,7 @@ Example:
 		interrupts = <0 78 0x04>;
 		clocks = <&tegra_car TEGRA20_CLK_EMC>;
 		nvidia,memory-controller = <&mc>;
-		core-supply = <&core_vdd_reg>;
+		power-domains = <&domain>;
 		operating-points-v2 = <&opp_table>;
 	}

Signature · 1 line

2.30.2

Dmitry Osipenko

author

2021-03-30 23:06 UTC #2 lore raw

PATCH v2 2/6 dt-bindings: memory: tegra30: emc: Replace core regulator with power domain

In reply to Dmitry Osipenko

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/memory-controllers/nvidia,tegra30-emc.yaml    | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +4 -3

index 0a2e2c0d0fdd..fb6af14cb49c 100644
@@ -39,9 +39,10 @@ properties:
     description:
       Phandle of the Memory Controller node.
 
-  core-supply:
+  power-domains:
+    maxItems: 1
     description:
-      Phandle of voltage regulator of the SoC "core" power domain.
+      Phandle of the SoC "core" power domain.
 
   operating-points-v2:
     description:

@@ -241,7 +242,7 @@ examples:
 
         nvidia,memory-controller = <&mc>;
         operating-points-v2 = <&dvfs_opp_table>;
-        core-supply = <&vdd_core>;
+        power-domains = <&domain>;
 
         #interconnect-cells = <0>;

Signature · 1 line

2.30.2

Rob Herring

maintainer Reviewed-by on v2 2/6

2021-04-01 17:43 UTC #3 lore raw

Re: [PATCH v2 2/6] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain

Quoted 11 lines · Dmitry Osipenko

Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../bindings/memory-controllers/nvidia,tegra30-emc.yaml    | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Reviewed-by Rob Herring <[email protected]>

Dmitry Osipenko

author

2021-03-30 23:06 UTC #4 lore raw

PATCH v2 3/6 dt-bindings: memory: tegra124: emc: Replace core regulator with power domain

In reply to Dmitry Osipenko

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../bindings/memory-controllers/nvidia,tegra124-emc.yaml   | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +4 -3

index 09bde65e1955..9163c3f12a85 100644
@@ -37,9 +37,10 @@ properties:
     description:
       phandle of the memory controller node
 
-  core-supply:
+  power-domains:
+    maxItems: 1
     description:
-      Phandle of voltage regulator of the SoC "core" power domain.
+      Phandle of the SoC "core" power domain.
 
   operating-points-v2:
     description:

@@ -370,7 +371,7 @@ examples:
 
         nvidia,memory-controller = <&mc>;
         operating-points-v2 = <&dvfs_opp_table>;
-        core-supply = <&vdd_core>;
+        power-domains = <&domain>;
 
         #interconnect-cells = <0>;

Signature · 1 line

2.30.2

Rob Herring

maintainer Reviewed-by on v2 3/6

2021-04-01 18:21 UTC #5 lore raw

Re: [PATCH v2 3/6] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain

Quoted 11 lines · Dmitry Osipenko

Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../bindings/memory-controllers/nvidia,tegra124-emc.yaml   | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Reviewed-by Rob Herring <[email protected]>

Dmitry Osipenko

author

2021-03-30 23:06 UTC #6 lore raw

PATCH v2 4/6 dt-bindings: memory: tegra20: mc: Convert to schema

In reply to Dmitry Osipenko

Convert Tegra20 Memory Controller binding to schema.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../memory-controllers/nvidia,tegra20-mc.txt  | 40 ----------
 .../memory-controllers/nvidia,tegra20-mc.yaml | 79 +++++++++++++++++++
 2 files changed, 79 insertions(+), 40 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted +0 ~~-40~~

deleted file mode 100644
index 739b7c6f2e26..000000000000
@@ -1,40 +0,0 @@
-NVIDIA Tegra20 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra20-mc-gart"
-- reg : Should contain 2 register ranges: physical base address and length of
-  the controller's registers and the GART aperture respectively.
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - mc: the module's clock input
-- interrupts : Should contain MC General interrupt.
-- #reset-cells : Should be 1. This cell represents memory client module ID.
-  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
-  or in the TRM documentation.
-- #iommu-cells: Should be 0. This cell represents the number of cells in an
-  IOMMU specifier needed to encode an address. GART supports only a single
-  address space that is shared by all devices, therefore no additional
-  information needed for the address encoding.
-- #interconnect-cells : Should be 1. This cell represents memory client.
-  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.
-
-Example:
-	mc: memory-controller@7000f000 {
-		compatible = "nvidia,tegra20-mc-gart";
-		reg = <0x7000f000 0x400		/* controller registers */
-		       0x58000000 0x02000000>;	/* GART aperture */
-		clocks = <&tegra_car TEGRA20_CLK_MC>;
-		clock-names = "mc";
-		interrupts = <GIC_SPI 77 0x04>;
-		#reset-cells = <1>;
-		#iommu-cells = <0>;
-		#interconnect-cells = <1>;
-	};
-
-	video-codec@6001a000 {
-		compatible = "nvidia,tegra20-vde";
-		...
-		resets = <&mc TEGRA20_MC_RESET_VDE>;
-		iommus = <&mc>;
-	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml new file +79 -0

79 lines not on this page · raw message

Signature · 1 line

2.30.2

Rob Herring

maintainer Reviewed-by on v2 4/6

2021-04-01 18:12 UTC #7 lore raw

Re: [PATCH v2 4/6] dt-bindings: memory: tegra20: mc: Convert to schema

Quoted 10 lines · Dmitry Osipenko

Convert Tegra20 Memory Controller binding to schema.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../memory-controllers/nvidia,tegra20-mc.txt  | 40 ----------
 .../memory-controllers/nvidia,tegra20-mc.yaml | 79 +++++++++++++++++++
 2 files changed, 79 insertions(+), 40 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

Reviewed-by Rob Herring <[email protected]>

Dmitry Osipenko

author

2021-03-30 23:06 UTC #8 lore raw

PATCH v2 5/6 dt-bindings: memory: tegra20: emc: Convert to schema

In reply to Dmitry Osipenko

Convert Tegra20 External Memory Controller binding to schema.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt deleted +0 ~~-130~~

deleted file mode 100644
index d2250498c36d..000000000000
@@ -1,130 +0,0 @@
-Embedded Memory Controller
-
-Properties:
-- name : Should be emc
-- #address-cells : Should be 1
-- #size-cells : Should be 0
-- compatible : Should contain "nvidia,tegra20-emc".
-- reg : Offset and length of the register set for the device
-- nvidia,use-ram-code : If present, the sub-nodes will be addressed
-  and chosen using the ramcode board selector. If omitted, only one
-  set of tables can be present and said tables will be used
-  irrespective of ram-code configuration.
-- interrupts : Should contain EMC General interrupt.
-- clocks : Should contain EMC clock.
-- nvidia,memory-controller : Phandle of the Memory Controller node.
-- #interconnect-cells : Should be 0.
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-For each opp entry in 'operating-points-v2' table:
-- opp-supported-hw: One bitfield indicating SoC process ID mask
-
-	A bitwise AND is performed against this value and if any bit
-	matches, the OPP gets enabled.
-
-Optional properties:
-- power-domains: Phandle of the SoC "core" power domain.
-
-Child device nodes describe the memory settings for different configurations and clock rates.
-
-Example:
-
-	opp_table: opp-table {
-		compatible = "operating-points-v2";
-
-		opp@36000000 {
-			opp-microvolt = <950000 950000 1300000>;
-			opp-hz = /bits/ 64 <36000000>;
-		};
-		...
-	};
-
-	memory-controller@7000f400 {
-		#address-cells = < 1 >;
-		#size-cells = < 0 >;
-		#interconnect-cells = <0>;
-		compatible = "nvidia,tegra20-emc";
-		reg = <0x7000f400 0x400>;
-		interrupts = <0 78 0x04>;
-		clocks = <&tegra_car TEGRA20_CLK_EMC>;
-		nvidia,memory-controller = <&mc>;
-		power-domains = <&domain>;
-		operating-points-v2 = <&opp_table>;
-	}
-
-
-Embedded Memory Controller ram-code table
-
-If the emc node has the nvidia,use-ram-code property present, then the
-next level of nodes below the emc table are used to specify which settings
-apply for which ram-code settings.
-
-If the emc node lacks the nvidia,use-ram-code property, this level is omitted
-and the tables are stored directly under the emc node (see below).
-
-Properties:
-
-- name : Should be emc-tables
-- nvidia,ram-code : the binary representation of the ram-code board strappings
-  for which this node (and children) are valid.
-
-
-
-Embedded Memory Controller configuration table
-
-This is a table containing the EMC register settings for the various
-operating speeds of the memory controller. They are always located as
-subnodes of the emc controller node.
-
-There are two ways of specifying which tables to use:
-
-* The simplest is if there is just one set of tables in the device tree,
-  and they will always be used (based on which frequency is used).
-  This is the preferred method, especially when firmware can fill in
-  this information based on the specific system information and just
-  pass it on to the kernel.
-
-* The slightly more complex one is when more than one memory configuration
-  might exist on the system.  The Tegra20 platform handles this during
-  early boot by selecting one out of possible 4 memory settings based
-  on a 2-pin "ram code" bootstrap setting on the board. The values of
-  these strappings can be read through a register in the SoC, and thus
-  used to select which tables to use.
-
-Properties:
-- name : Should be emc-table
-- compatible : Should contain "nvidia,tegra20-emc-table".
-- reg : either an opaque enumerator to tell different tables apart, or
-  the valid frequency for which the table should be used (in kHz).
-- clock-frequency : the clock frequency for the EMC at which this
-  table should be used (in kHz).
-- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
-  for operation at the 'clock-frequency' setting.
-  The order and contents of the registers are:
-    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
-    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
-    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
-    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
-    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
-    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
-    CFG_CLKTRIM_1, CFG_CLKTRIM_2
-
-		emc-table@166000 {
-			reg = <166000>;
-			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 166000 >;
-			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 >;
-		};
-
-		emc-table@333000 {
-			reg = <333000>;
-			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 333000 >;
-			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-						 0 0 0 0 >;
-		};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml new file +294 -0

294 lines not on this page · raw message

Signature · 1 line

2.30.2

Rob Herring

maintainer

2021-03-31 13:42 UTC #9 lore raw

Re: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema

Quoted 10 lines · Dmitry Osipenko

Convert Tegra20 External Memory Controller binding to schema.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.example.dts:33.26-55.15: Warning (unit_address_vs_reg): /example-0/external-memory-controller@7000f400/emc-tables@0: node has a unit name, but no reg or ranges property

See https://patchwork.ozlabs.org/patch/1460288

This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:

pip3 install dtschema --upgrade

Please check and re-submit.

Dmitry Osipenko

author

2021-03-31 15:00 UTC #10 lore raw

Re: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema

31.03.2021 16:40, Rob Herring пишет:

Quoted 24 lines · Dmitry Osipenko

Quoted 10 lines
Convert Tegra20 External Memory Controller binding to schema.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.example.dts:33.26-55.15: Warning (unit_address_vs_reg): /example-0/external-memory-controller@7000f400/emc-tables@0: node has a unit name, but no reg or ranges property
See https://patchwork.ozlabs.org/patch/1460288
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.

Quoted 8 lines

If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.

FYI, I'm aware about this warning and I think it's fine to skip it in the case of this binding. The dtbs_check doesn't bother with that warning.

Rob Herring

maintainer

2021-04-01 17:43 UTC #11 lore raw

Re: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema

Quoted 29 lines · Dmitry Osipenko

31.03.2021 16:40, Rob Herring пишет:
Quoted 28 lines · Dmitry Osipenko
Quoted 10 lines
Convert Tegra20 External Memory Controller binding to schema.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.example.dts:33.26-55.15: Warning (unit_address_vs_reg): /example-0/external-memory-controller@7000f400/emc-tables@0: node has a unit name, but no reg or ranges property
See https://patchwork.ozlabs.org/patch/1460288
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:

Quoted 7 lines

Quoted 4 lines
pip3 install dtschema --upgrade
Please check and re-submit.
FYI, I'm aware about this warning and I think it's fine to skip it in the case of this binding.

It's not because dt_binding_check should be warning free.

Quoted 1 line

The dtbs_check doesn't bother with that warning.

With W=1 it will. It's off by default because there are too many of these warnings. Patches welcome.

Rob

Dmitry Osipenko

author

2021-04-02 14:45 UTC #12 lore raw

Re: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema

01.04.2021 18:55, Rob Herring пишет:

Quoted 38 lines · Dmitry Osipenko

Quoted 29 lines
31.03.2021 16:40, Rob Herring пишет:
Quoted 28 lines · Dmitry Osipenko
Quoted 10 lines
Convert Tegra20 External Memory Controller binding to schema.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.example.dts:33.26-55.15: Warning (unit_address_vs_reg): /example-0/external-memory-controller@7000f400/emc-tables@0: node has a unit name, but no reg or ranges property
See https://patchwork.ozlabs.org/patch/1460288
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
Quoted 7 lines
Quoted 4 lines
pip3 install dtschema --upgrade
Please check and re-submit.
FYI, I'm aware about this warning and I think it's fine to skip it in the case of this binding.

Quoted 6 lines

It's not because dt_binding_check should be warning free.
Quoted 1 line
The dtbs_check doesn't bother with that warning.
With W=1 it will. It's off by default because there are too many of these warnings. Patches welcome.

Such warning could be silenced with some kind of a new pragma option in schema which will tell what warnings are inappropriate.

But since there is no such option today, perhaps indeed should be better to just add a dummy reg property and fix the device-trees.

Dmitry Osipenko

author

2021-04-04 13:18 UTC #13 lore raw

Re: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema

02.04.2021 17:45, Dmitry Osipenko пишет:

Quoted 43 lines

01.04.2021 18:55, Rob Herring пишет:
Quoted 42 lines · Dmitry Osipenko
Quoted 29 lines
31.03.2021 16:40, Rob Herring пишет:
Quoted 28 lines · Dmitry Osipenko
Quoted 10 lines
Convert Tegra20 External Memory Controller binding to schema.
Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 2 files changed, 294 insertions(+), 130 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.example.dts:33.26-55.15: Warning (unit_address_vs_reg): /example-0/external-memory-controller@7000f400/emc-tables@0: node has a unit name, but no reg or ranges property
See https://patchwork.ozlabs.org/patch/1460288
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
Quoted 7 lines
Quoted 4 lines
pip3 install dtschema --upgrade
Please check and re-submit.
FYI, I'm aware about this warning and I think it's fine to skip it in the case of this binding.
It's not because dt_binding_check should be warning free.
Quoted 1 line
The dtbs_check doesn't bother with that warning.

Quoted 9 lines

Quoted 2 lines
With W=1 it will. It's off by default because there are too many of these warnings. Patches welcome.
Such warning could be silenced with some kind of a new pragma option in schema which will tell what warnings are inappropriate.
But since there is no such option today, perhaps indeed should be better to just add a dummy reg property and fix the device-trees.

This actually was my bad, the reg property is already specified in this version of binding as required. Apparently I got confused while was looking at some device-tree that doesn't have the reg property and it should be corrected.

Dmitry Osipenko

author

2021-03-30 23:06 UTC #14 lore raw

PATCH v2 6/6 memory: tegra: Print out info-level once per driver probe

In reply to Dmitry Osipenko

Probing of EMC drivers may be deferred and in this case we get duplicated info messages during kernel boot. Use dev_info_once() helper to silence the duplicated messages.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/memory/tegra/tegra124-emc.c | 12 ++++++------
 drivers/memory/tegra/tegra20-emc.c  | 20 ++++++++++----------
 drivers/memory/tegra/tegra30-emc.c  | 18 +++++++++---------
 3 files changed, 25 insertions(+), 25 deletions(-)

drivers/memory/tegra/tegra124-emc.c +6 -6

index 874e1a0f23cd..5699d909abc2 100644
@@ -905,7 +905,7 @@ static int emc_init(struct tegra_emc *emc)
 	else
 		emc->dram_bus_width = 32;
 
-	dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
+	dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 
 	emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
 	emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;

@@ -1419,8 +1419,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 		goto put_hw_table;
 	}
 
-	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-		 hw_version, clk_get_rate(emc->clk) / 1000000);
+	dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+		      hw_version, clk_get_rate(emc->clk) / 1000000);
 
 	/* first dummy rate-set initializes voltage state */
 	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));

@@ -1475,9 +1475,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
 		if (err)
 			return err;
 	} else {
-		dev_info(&pdev->dev,
-			 "no memory timings for RAM code %u found in DT\n",
-			 ram_code);
+		dev_info_once(&pdev->dev,
+			      "no memory timings for RAM code %u found in DT\n",
+			      ram_code);
 	}
 
 	err = emc_init(emc);

drivers/memory/tegra/tegra20-emc.c +10 ~~-10~~

index d653a6be8d7f..da8a0da8da79 100644
@@ -411,12 +411,12 @@ static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
 	sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
 	     NULL);
 
-	dev_info(emc->dev,
-		 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
-		 emc->num_timings,
-		 tegra_read_ram_code(),
-		 emc->timings[0].rate / 1000000,
-		 emc->timings[emc->num_timings - 1].rate / 1000000);
+	dev_info_once(emc->dev,
+		      "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
+		      emc->num_timings,
+		      tegra_read_ram_code(),
+		      emc->timings[0].rate / 1000000,
+		      emc->timings[emc->num_timings - 1].rate / 1000000);
 
 	return 0;
 }

@@ -429,7 +429,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)
 	int err;
 
 	if (of_get_child_count(dev->of_node) == 0) {
-		dev_info(dev, "device-tree doesn't have memory timings\n");
+		dev_info_once(dev, "device-tree doesn't have memory timings\n");
 		return NULL;
 	}

@@ -496,7 +496,7 @@ static int emc_setup_hw(struct tegra_emc *emc)
 	else
 		emc->dram_bus_width = 32;
 
-	dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
+	dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
 
 	return 0;
 }

@@ -931,8 +931,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 		goto put_hw_table;
 	}
 
-	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-		 hw_version, clk_get_rate(emc->clk) / 1000000);
+	dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+		      hw_version, clk_get_rate(emc->clk) / 1000000);
 
 	/* first dummy rate-set initializes voltage state */
 	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));

drivers/memory/tegra/tegra30-emc.c +9 -9

index 6985da0ffb35..829f6d673c96 100644
@@ -998,12 +998,12 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc,
 	if (err)
 		return err;
 
-	dev_info(emc->dev,
-		 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
-		 emc->num_timings,
-		 tegra_read_ram_code(),
-		 emc->timings[0].rate / 1000000,
-		 emc->timings[emc->num_timings - 1].rate / 1000000);
+	dev_info_once(emc->dev,
+		      "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
+		      emc->num_timings,
+		      tegra_read_ram_code(),
+		      emc->timings[0].rate / 1000000,
+		      emc->timings[emc->num_timings - 1].rate / 1000000);
 
 	return 0;
 }

@@ -1015,7 +1015,7 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev)
 	int err;
 
 	if (of_get_child_count(dev->of_node) == 0) {
-		dev_info(dev, "device-tree doesn't have memory timings\n");
+		dev_info_once(dev, "device-tree doesn't have memory timings\n");
 		return NULL;
 	}

@@ -1503,8 +1503,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
 		goto put_hw_table;
 	}
 
-	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
-		 hw_version, clk_get_rate(emc->clk) / 1000000);
+	dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
+		      hw_version, clk_get_rate(emc->clk) / 1000000);
 
 	/* first dummy rate-set initializes voltage state */
 	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));

Signature · 1 line

2.30.2

Krzysztof Kozlowski

Applied

2021-04-01 20:03 UTC #15 lore raw

Re: (subset) [PATCH v2 0/6] NVIDIA Tegra memory improvements

In reply to Dmitry Osipenko

Quoted 9 lines · Dmitry Osipenko

This series replaces the raw voltage regulator with a power domain that will be managing SoC core voltage. The core power domain patches are still under review, but it's clear at this point that this is the way we will implement the DVFS support.
The remaining Tegra20 memory bindings are converted to schema. I also made a small improvement to the memory drivers.
[...]

Applied, thanks!

[4/6] dt-bindings: memory: tegra20: mc: Convert to schema

      commit: 6553fa57cb1707396ad3a27dc78fa61e1750ab31

Best regards,

Signature · 1 line

Krzysztof Kozlowski <[email protected]>

Krzysztof Kozlowski

Applied

2021-04-01 20:03 UTC #16 lore raw

In reply to Dmitry Osipenko

Quoted 16 lines · Dmitry Osipenko

Hi,
This series replaces the raw voltage regulator with a power domain that will be managing SoC core voltage. The core power domain patches are still under review, but it's clear at this point that this is the way we will implement the DVFS support.
The remaining Tegra20 memory bindings are converted to schema. I also made a small improvement to the memory drivers.
Changelog:
v2: - Fixed typos in the converted schemas.
- Corrected reg entry of tegra20-mc-gart schema to use fixed number of items.
- Made power-domain to use maxItems instead of $ref phandle in schemas.

Quoted 10 lines

Dmitry Osipenko (6):
dt-bindings: memory: tegra20: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra30: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra124: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra20: mc: Convert to schema
dt-bindings: memory: tegra20: emc: Convert to schema
memory: tegra: Print out info-level once per driver probe

Thanks, applied subset - 1-4 and 6. For patch 5/6 I expect v3.

Best regards,
Krzysztof

Quoted 16 lines

 .../nvidia,tegra124-emc.yaml                  |   7 +-
 .../memory-controllers/nvidia,tegra20-emc.txt | 130 --------
 .../nvidia,tegra20-emc.yaml                   | 294 ++++++++++++++++++
 .../memory-controllers/nvidia,tegra20-mc.txt  |  40 ---
 .../memory-controllers/nvidia,tegra20-mc.yaml |  79 +++++
 .../nvidia,tegra30-emc.yaml                   |   7 +-
 drivers/memory/tegra/tegra124-emc.c           |  12 +-
 drivers/memory/tegra/tegra20-emc.c            |  20 +-
 drivers/memory/tegra/tegra30-emc.c            |  18 +-
 9 files changed, 406 insertions(+), 201 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
 delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

Best regards,
Krzysztof

Dmitry Osipenko

author

2021-04-02 14:48 UTC #17 lore raw

01.04.2021 20:54, Krzysztof Kozlowski пишет:

Quoted 28 lines · Dmitry Osipenko

Quoted 16 lines
Hi,
This series replaces the raw voltage regulator with a power domain that will be managing SoC core voltage. The core power domain patches are still under review, but it's clear at this point that this is the way we will implement the DVFS support.
The remaining Tegra20 memory bindings are converted to schema. I also made a small improvement to the memory drivers.
Changelog:
v2: - Fixed typos in the converted schemas.
- Corrected reg entry of tegra20-mc-gart schema to use fixed number of items.
- Made power-domain to use maxItems instead of $ref phandle in schemas.
Quoted 10 lines
Dmitry Osipenko (6):
dt-bindings: memory: tegra20: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra30: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra124: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra20: mc: Convert to schema
dt-bindings: memory: tegra20: emc: Convert to schema
memory: tegra: Print out info-level once per driver probe

Quoted 1 line

Thanks, applied subset - 1-4 and 6. For patch 5/6 I expect v3.

I'll make a v3, thank you.

Krzysztof Kozlowski

Applied

2021-04-01 20:03 UTC #18 lore raw

In reply to Dmitry Osipenko

Quoted 9 lines · Dmitry Osipenko

This series replaces the raw voltage regulator with a power domain that will be managing SoC core voltage. The core power domain patches are still under review, but it's clear at this point that this is the way we will implement the DVFS support.
The remaining Tegra20 memory bindings are converted to schema. I also made a small improvement to the memory drivers.
[...]

Applied, thanks!

[1/6] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain

      commit: d46cf7106c4979117e108336dfadcaf57d23f9ed
[2/6] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
      commit: c19137a97e39a9cdf24c9feb580af4564997c1f9
[3/6] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain
      commit: 749d01cd0b796adb69d68e9079520f4f95b17cd2
[6/6] memory: tegra: Print out info-level once per driver probe
      commit: 06949d1d9accbc7d3a029536650162bbca30151b

Best regards,

Signature · 1 line

Krzysztof Kozlowski <[email protected]>