Add Synopsys DesignWare HDMI RX Controller and PHY drivers
Subsystems (4)
cover Add Synopsys DesignWare HDMI RX Controller and PHY drivers
This series implements support for the Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 drivers, being compliant with standard HDMI 1.4 and HDMI 2.0.
The Controller + PHY pipeline can be integrated into a fully featured system that can be able to receive video up to 4k@60Hz with basic audio.
This solution is mainly composed by two modules: phy-dw-hdmi-e40x and dw-hdmi-rx.
phy-dw-hdmi-e40x: it's the PHY (Physical Layer) driver that implements support for Synopsys DesignWare e405 and e406 PHYs. It is responsible to configure the PHY and equalize it for the best settings, in order to receive and decode video to be delivered to the Controller. This driver is integrated in the PHY subsystem.
The main features of this module are:
- Equalizer algorithm that chooses the phy best settings according to the detected HDMI cable characteristics
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz).
dw-hdmi-rx: it's the Controller driver that implements support for Synopsys DesignWare HDMI RX Controller. It is responsible to manage and handle the PHY (through the PHY API) and the Controller configurations in order to configure the video and audio pipeline.
This driver is implemented as a standard V4L2 subdevice.
The main features of this module are:
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz)
- Support for RGB, YCC444, YCC422 and YCC420
- Support for basic audio (LPCM 2ch, 32KHz/44.1KHz/48KHz, 16bit)
- Support for Aspect Ratio
- Support for CEC
- Internal state machine that reconfigures phy and controller
- JTAG communication with phy
- Inter-module communication with phy driver:
* through the PHY API using the phy reference "hdmi-phy"
* through the callbacks that phy dwc driver needs.
- Debug write/read ioctls
NOTES: This patch series has two specific patches (Patch [3/8] and [6/8]) one for the PHY API and the other for v4l2-dv-timings.
Patch [3/8] adds phy standard HDMI opts to the phy API that contributes for the PHY subsystem, which allows to integrate the PHY driver in the PHY subsystem using this new HDMI opts structure, because there are hdmi options that are needed to pass between the Controller and PHY drivers using the standard API.
Patch [6/8] adds more CEA/CTA-861 video format timings that contributes to the v4l2 media subsystem, which in our case is needed to provide information about the Aspect Ratio.
Nelson Costa (8):
dt-bindings: media: Document Synopsys DesignWare HDMI RX
MAINTAINERS: Add entry for Synopsys DesignWare HDMI drivers
phy: Add PHY standard HDMI opts to the PHY API
phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver
media: platform: Add Synopsys DesignWare HDMI RX Controller Driver
media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
media: dwc: dw-hdmi-rx: Add support for Aspect Ratio
media: dwc: dw-hdmi-rx: Add support for CEC
.../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 149 + MAINTAINERS | 11 + drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 1 + drivers/media/platform/dwc/Kconfig | 20 + drivers/media/platform/dwc/Makefile | 3 + drivers/media/platform/dwc/dw-hdmi-rx.c | 3544 ++++++++++++++++++++ drivers/media/platform/dwc/dw-hdmi-rx.h | 533 +++ drivers/media/v4l2-core/v4l2-dv-timings.c | 139 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/dwc/Kconfig | 20 + drivers/phy/dwc/Makefile | 9 + drivers/phy/dwc/phy-dw-hdmi-e405.c | 497 +++ drivers/phy/dwc/phy-dw-hdmi-e406.c | 475 +++ drivers/phy/dwc/phy-dw-hdmi-e40x-core.c | 514 +++ drivers/phy/dwc/phy-dw-hdmi-e40x.h | 219 ++ include/linux/phy/dwc/dw-hdmi-phy-pdata.h | 73 + include/linux/phy/phy-hdmi.h | 102 + include/linux/phy/phy.h | 7 +- include/media/dwc/dw-hdmi-rx-pdata.h | 126 + include/uapi/linux/v4l2-dv-timings.h | 1595 ++++++++- 22 files changed, 8039 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml create mode 100644 drivers/media/platform/dwc/Kconfig create mode 100644 drivers/media/platform/dwc/Makefile create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.c create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.h create mode 100644 drivers/phy/dwc/Kconfig create mode 100644 drivers/phy/dwc/Makefile create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e405.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e406.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x.h create mode 100644 include/linux/phy/dwc/dw-hdmi-phy-pdata.h create mode 100644 include/linux/phy/phy-hdmi.h create mode 100644 include/media/dwc/dw-hdmi-rx-pdata.h
Signature · 1 line
2.7.4
RFC 1/8 dt-bindings: media: Document Synopsys DesignWare HDMI RX
Document the bindings for the Synopsys DesignWare HDMI RX.
--- .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 149 +++++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +149 -0
@@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 Device Tree Bindings + +maintainers: + - Jose Abreu <[email protected]> + - Nelson Costa <[email protected]> + +description: | + The Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 is an HDMI 2.0 + Receiver solution that is able to decode video and audio. + +properties: + compatible: + const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + phys: + maxItems: 1 + description: phandle for the HDMI RX PHY + + phy-names: + const: hdmi-phy + + hdmi-phy@fc: + type: object + description: connection point for HDMI PHY + additionalProperties: false + + properties: + compatible: + oneOf: + - const: snps,dw-hdmi-phy-e405 + - const: snps,dw-hdmi-phy-e406 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#phy-cells": + const: 0 + + input-count: + description: Number of PHY input ports + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + + required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - input-count + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - phys + - phy-names + +additionalProperties: false + +examples: + - | + hdmi_rx0: hdmi-rx@0 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e405_phy>; + phy-names = "hdmi-phy"; + + hdmi_e405_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e405"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + }; + - | + hdmi_rx1: hdmi-rx@1 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e406_phy>; + phy-names = "hdmi-phy"; + + hdmi_e406_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e406"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + };
Signature · 1 line
2.7.4
Re: [RFC 1/8] dt-bindings: media: Document Synopsys DesignWare HDMI RX
Hi Nelson and Jose,
Thank you for the patch.
Quoted 98 lines · Nelson Costa
Document the bindings for the Synopsys DesignWare HDMI RX.
Signed-off-by Jose Abreu <[email protected]>Signed-off-by Nelson Costa <[email protected]>--- .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 149 +++++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yamlDocumentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +83
-0@@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 Device Tree Bindings + +maintainers: + - Jose Abreu <[email protected]> + - Nelson Costa <[email protected]> + +description: | + The Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 is an HDMI 2.0 + Receiver solution that is able to decode video and audio. + +properties: + compatible: + const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + phys: + maxItems: 1 + description: phandle for the HDMI RX PHY + + phy-names: + const: hdmi-phy + + hdmi-phy@fc: + type: object + description: connection point for HDMI PHY + additionalProperties: false + + properties: + compatible: + oneOf: + - const: snps,dw-hdmi-phy-e405 + - const: snps,dw-hdmi-phy-e406 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#phy-cells": + const: 0 + + input-count: + description: Number of PHY input ports + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + + required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - input-count +
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml line 93
Quoted 10 lines
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +10
-0+required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - phys + - phy-names
THe bindings should be using OF graph (ports) to model the connection between the HDMI source (usually a connector) and the HDMI RX, and between the HDMI RX and the downstream IP core in the pipeline.
Quoted 56 lines
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +56
-0+ +additionalProperties: false + +examples: + - | + hdmi_rx0: hdmi-rx@0 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e405_phy>; + phy-names = "hdmi-phy"; + + hdmi_e405_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e405"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + }; + - | + hdmi_rx1: hdmi-rx@1 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e406_phy>; + phy-names = "hdmi-phy"; + + hdmi_e406_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e406"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + };
Signature · 3 lines
Regards, Laurent Pinchart
RE: [RFC 1/8] dt-bindings: media: Document Synopsys DesignWare HDMI RX
Hi Laurent,
Thanks for the feedback!
From: Laurent Pinchart <[email protected]>
Date: qua, abr 28, 2021 at 23:01:41
Quoted 109 lines
Hi Nelson and Jose,
Thank you for the patch.
Quoted 104 lines · Nelson Costa
Document the bindings for the Synopsys DesignWare HDMI RX.
Signed-off-by Jose Abreu <[email protected]>Signed-off-by Nelson Costa <[email protected]>--- .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 149 +++++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yamlDocumentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +89
-0@@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml*__;Iw!!A4F2R9G_pg!KZ4lOoXlRjAtJ4GvM28AiL2SL8KFjt9Qsy2J0a1BQDnAujAAZD0vPA_7DJzM0XR8J54$ +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!A4F2R9G_pg!KZ4lOoXlRjAtJ4GvM28AiL2SL8KFjt9Qsy2J0a1BQDnAujAAZD0vPA_7DJzME7h7a-A$ + +title: Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 Device Tree Bindings + +maintainers: + - Jose Abreu <[email protected]> + - Nelson Costa <[email protected]> + +description: | + The Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 is an HDMI 2.0 + Receiver solution that is able to decode video and audio. + +properties: + compatible: + const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + phys: + maxItems: 1 + description: phandle for the HDMI RX PHY + + phy-names: + const: hdmi-phy + + hdmi-phy@fc: + type: object + description: connection point for HDMI PHY + additionalProperties: false + + properties: + compatible: + oneOf: + - const: snps,dw-hdmi-phy-e405 + - const: snps,dw-hdmi-phy-e406 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the configuration clock + + clock-names: + const: cfg + + "#phy-cells": + const: 0 + + input-count: + description: Number of PHY input ports + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + + required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - input-count + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names
Quoted 9 lines
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml line 93
Quoted 4 lines
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +4
-0+ - "#address-cells" + - "#size-cells" + - phys + - phy-namesTHe bindings should be using OF graph (ports) to model the connection between the HDMI source (usually a connector) and the HDMI RX, and between the HDMI RX and the downstream IP core in the pipeline.
This will be addressed in the next patch series.
BTW, do you have any suggestion regarding an eventual good driver & dt example/implementation that we could follow?
in order to try to apply the same logic here...
Thanks!
BR,
Nelson
Quoted 61 lines
Quoted 56 lines
Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +56
-0+ +additionalProperties: false + +examples: + - | + hdmi_rx0: hdmi-rx@0 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e405_phy>; + phy-names = "hdmi-phy"; + + hdmi_e405_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e405"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + }; + - | + hdmi_rx1: hdmi-rx@1 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + phys = <&hdmi_e406_phy>; + phy-names = "hdmi-phy"; + + hdmi_e406_phy: hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e406"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #phy-cells = <0>; + input-count = <4>; + }; + };Signature · 3 lines
Regards, Laurent Pinchart
RFC 2/8 MAINTAINERS: Add entry for Synopsys DesignWare HDMI drivers
In reply to Nelson CostaAdd an entry for Synopsys DesignWare HDMI Receivers drivers and PHYs.
--- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+)
MAINTAINERS +11 -0
@@ -17304,6 +17304,17 @@ S: Supported F: drivers/net/pcs/pcs-xpcs.c F: include/linux/pcs/pcs-xpcs.h +SYNOPSYS DESIGNWARE HDMI RECEIVERS AND PHY DRIVERS +M: Jose Abreu <[email protected]> +M: Nelson Costa <[email protected]> +L: [email protected] +S: Odd Fixes +F: Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml +F: drivers/media/platform/dwc/* +F: drivers/phy/dwc/* +F: include/linux/phy/dwc/* +F: include/media/dwc/* + SYNOPSYS DESIGNWARE I2C DRIVER M: Jarkko Nikula <[email protected]> R: Andy Shevchenko <[email protected]>
Signature · 1 line
2.7.4
RFC 3/8 phy: Add PHY standard HDMI opts to the PHY API
In reply to Nelson CostaThis adds the new options to give support for HDMI PHYs in a standard way. This is mainly useful when the HDMI PHY requires parameters to be passed by "phy_configure" function.
For this, the new struct phy_configure_opts_hdmi
was added with the required generic and standard
parameters.
--- include/linux/phy/phy-hdmi.h | 102 +++++++++++++++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 7 ++- 2 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 include/linux/phy/phy-hdmi.h
include/linux/phy/phy-hdmi.h new file +102 -0
@@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2021 - present Synopsys, Inc. and/or its affiliates. +* HDMI generic PHY options. +* +* Author: Nelson Costa <[email protected]> +*/ +#ifndef __PHY_HDMI_H_ +#define __PHY_HDMI_H_ + +#include <linux/types.h> + +/** +* struct phy_configure_opts_hdmi - HDMI PHY configuration set +* +* This structure is used to represent the configuration state of an +* HDMI PHY. +*/ +struct phy_configure_opts_hdmi { +/** +* @color_depth: +* +* Color depth, as specified by HDMI specification, represents the +* number of bits per pixel. +* +* Allowed values: 24, 30, 36, 48 +* +*/ +u8 color_depth; + +/** +* @tmds_bit_clock_ratio: +* +* Flag indicating, as specified by HDMI specification, the relation +* between TMDS Clock Rate and TMDS Character Rate. +* +* As specified by HDMI specification: +* +* tmds_bit_clock_ratio = 0, for TMDS Character Rates <= 340 Mcsc +* (TMDS Clock Rate = TMDS Character Rate) +* +* tmds_bit_clock_ratio = 1, for TMDS Character Rates > 340 Mcsc +* (TMDS Clock Rate = TMDS Character Rate / 4) +* +*/ +u8 tmds_bit_clock_ratio; + +/** +* @scrambling: +* +* Scrambling, as specified by HDMI specification, enables the technique +* to reduce the EMI/RFI. +* +*/ +u8 scrambling; + +/** +* @calibration_acq: +* +* Calibration acquisitions number for the calibration algorithm. +* +*/ +unsigned int calibration_acq; + +/** +* @calibration_force: +* +* Flag indicating, to force calibration algorithm even if the MPLL +* status didn't change from previous run calibration. +* +*/ +u8 calibration_force; + +/** +* @set_color_depth: +* +* Flag indicating, whether or not reconfigure deep_color +* to requested values. +* +*/ +u8 set_color_depth :1 ; + +/** +* @set_tmds_bit_clock_ratio: +* +* Flag indicating, whether or not reconfigure tmds_bit_clock_ratio +* to requested values. +* +*/ +u8 set_tmds_bit_clock_ratio :1 ; + +/** +* @set_scrambling: +* +* Flag indicating, whether or not reconfigure scrambling +* to requested values. +* +*/ +u8 set_scrambling :1 ; +}; + +#endif /* __PHY_HDMI_H_ */
include/linux/phy/phy.h +6 -1
@@ -18,6 +18,7 @@#include <linux/phy/phy-dp.h> #include <linux/phy/phy-mipi-dphy.h> +#include <linux/phy/phy-hdmi.h> struct phy ;
@@ -41,7 +42,8 @@ enum phy_mode {PHY_MODE_MIPI_DPHY ,PHY_MODE_SATA ,PHY_MODE_LVDS , - PHY_MODE_DP +PHY_MODE_DP , + PHY_MODE_HDMI };/**
@@ -51,10 +53,13 @@ enum phy_mode {* the MIPI_DPHY phy mode. * @dp: Configuration set applicable for phys supporting * the DisplayPort protocol. +* @hdmi Configuration set applicable for phys supporting +* the HDMI protocol. */ union phy_configure_opts {struct phy_configure_opts_mipi_dphy mipi_dphy;struct phy_configure_opts_dp dp; +struct phy_configure_opts_hdmi hdmi; };/**
Signature · 1 line
2.7.4
RFC 4/8 phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver
In reply to Nelson CostaThis adds support for the Synopsys DesignWare HDMI RX PHYs e405 and e406. The PHY receives and decodes HDMI video that is delivered to a controller.
Main features included in this driver are:
- Equalizer algorithm that chooses the PHY best settings according to the detected HDMI cable characteristics.
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz).
The driver was implemented using the standard PHY API in order to provide a standard access to the required callbacks to be handled by the controller through the phy_ops.
There is a bidirectional communication between controller and PHY:
- controller -> PHY : communication is done using the PHY API
- controller <- PHY : communication is done using the callbacks, provided by the controller, which are required to handle the PHY such as: read/write, pddq, reset, etc.
This callback functions are specified in struct dw_phy_pdata from 'include/linux/phy/dwc/dw-hdmi-phy-pdata.h'.
--- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/dwc/Kconfig | 20 ++ drivers/phy/dwc/Makefile | 9 + drivers/phy/dwc/phy-dw-hdmi-e405.c | 497 +++++++++++++++++++++++++++++ drivers/phy/dwc/phy-dw-hdmi-e406.c | 475 +++++++++++++++++++++++++++ drivers/phy/dwc/phy-dw-hdmi-e40x-core.c | 514 ++++++++++++++++++++++++++++++ drivers/phy/dwc/phy-dw-hdmi-e40x.h | 219 +++++++++++++ include/linux/phy/dwc/dw-hdmi-phy-pdata.h | 73 +++++ 9 files changed, 1809 insertions(+) create mode 100644 drivers/phy/dwc/Kconfig create mode 100644 drivers/phy/dwc/Makefile create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e405.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e406.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x.h create mode 100644 include/linux/phy/dwc/dw-hdmi-phy-pdata.h
drivers/phy/Kconfig +1 -0
@@ -65,6 +65,7 @@ source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" +source "drivers/phy/dwc/Kconfig" source "drivers/phy/freescale/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/ingenic/Kconfig"
drivers/phy/Makefile +1 -0
@@ -13,6 +13,7 @@ obj-y += allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ + dwc/ \ freescale/ \ hisilicon/ \ ingenic/ \
drivers/phy/dwc/Kconfig new file +20 -0
@@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +config VIDEO_DWC_HDMI_PHY_E40X + tristate "Synopsys DesignWare HDMI RX PHYs e405 and e406 driver" + select GENERIC_PHY + help + Support for Synopsys DesignWare HDMI RX PHYs versions + e405 and e406. + + To compile this driver as a module, choose M here. The module + will be called phy-dw-hdmi-e40x. + +config VIDEO_DWC_HDMI_PHY_E40X_SUPPORT_TESTCHIP + bool "Synopsys DesignWare HDMI RX PHYs e405/e406 Test Chip Support" + depends on VIDEO_DWC_HDMI_PHY_E40X + help + Support for Synopsys DesignWare HDMI RX PHYs e405/e406 with Test Chip. + + To have support for HDMI RX PHYs e405/e406 Test Chip, choose Y here. + It will enable Test Chip additional requirements, for example enable + the z calibration requirement during the PHY configuration.
drivers/phy/dwc/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the PHY drivers. +# + +phy-dw-hdmi-e40x-y := phy-dw-hdmi-e40x-core.o +phy-dw-hdmi-e40x-y += phy-dw-hdmi-e405.o +phy-dw-hdmi-e40x-y += phy-dw-hdmi-e406.o +obj-$(CONFIG_VIDEO_DWC_HDMI_PHY_E40X) += phy-dw-hdmi-e40x.o
drivers/phy/dwc/phy-dw-hdmi-e405.c new file +497 -0
497 lines not on this page · raw message
drivers/phy/dwc/phy-dw-hdmi-e406.c new file +475 -0
475 lines not on this page · raw message
drivers/phy/dwc/phy-dw-hdmi-e40x-core.c new file +514 -0
514 lines not on this page · raw message
drivers/phy/dwc/phy-dw-hdmi-e40x.h new file +219 -0
219 lines not on this page · raw message
include/linux/phy/dwc/dw-hdmi-phy-pdata.h new file +73 -0
73 lines not on this page · raw message
Signature · 1 line
2.7.4
kernel test robot
build botRe: [RFC 4/8] phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 base: git://linuxtv.org/media_tree.git master config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/616184ab2857513c2a560411bc86d51aeda69c92
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 git checkout 616184ab2857513c2a560411bc86d51aeda69c92
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=ia64
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/phy/dwc/phy-dw-hdmi-e406.c:139:6: warning: no previous prototype for 'dw_phy_eq_settings' [-Wmissing-prototypes]
139 | void dw_phy_eq_settings(struct dw_phy_dev *dw_dev, u16 ch0_setting,
| ^~~~~~~~~~~~~~~~~~
vim +/dw_phy_eq_settings +139 drivers/phy/dwc/phy-dw-hdmi-e406.c
138
> 139 void dw_phy_eq_settings(struct dw_phy_dev *dw_dev, u16 ch0_setting,
140 u16 ch1_setting, u16 ch2_setting)
141 {
142 dw_phy_write(dw_dev,
143 (DW_CHX_EQ_CTRL3_MASK |
144 (ch0_setting & DW_PHY_CH0_EXT_EQ_SET_MASK)),
145 DW_PHY_CH0_EQ_CTRL3);
146 dw_phy_write(dw_dev,
147 (DW_CHX_EQ_CTRL3_MASK |
148 (ch1_setting & DW_PHY_CH1_EXT_EQ_SET_MASK)),
149 DW_PHY_CH1_EQ_CTRL3);
150 dw_phy_write(dw_dev,
151 (DW_CHX_EQ_CTRL3_MASK |
152 (ch2_setting & DW_PHY_CH2_EXT_EQ_SET_MASK)),
153 DW_PHY_CH2_EQ_CTRL3);
154 dw_phy_write(dw_dev, DW_PHY_EQ_EN_OVR_EN, DW_PHY_MAINFSM_OVR2);
155
156 dw_phy_eq_auto_calib(dw_dev);
157 }
158
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC 5/8 media: platform: Add Synopsys DesignWare HDMI RX Controller Driver
In reply to Nelson CostaThis is an initial submission for the Synopsys DesignWare HDMI RX Controller Driver. It is responsible to manage and handle the PHY (through the PHY API) and the Controller configurations in order to configure the video and audio pipeline.
This driver is implemented as a standard V4L2 subdevice. The main features of this module are:
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz)
- Support for RGB, YCC444, YCC422 and YCC420
- Support for basic audio (LPCM 2ch, 32KHz/44.1KHz/48KHz, 16bit)
- Support for Aspect Ratio
- Support for CEC
- Internal state machine that reconfigures PHY and controller
- JTAG communication with PHY
- Inter-module communication with PHY driver:
* through the PHY API using the PHY reference "hdmi-phy"
* through the callbacks that PHY DWC driver needs.
- Debug write/read ioctls.
--- drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 1 + drivers/media/platform/dwc/Kconfig | 10 + drivers/media/platform/dwc/Makefile | 3 + drivers/media/platform/dwc/dw-hdmi-rx.c | 3239 +++++++++++++++++++++++++++++++ drivers/media/platform/dwc/dw-hdmi-rx.h | 476 +++++ include/media/dwc/dw-hdmi-rx-pdata.h | 126 ++ 7 files changed, 3857 insertions(+) create mode 100644 drivers/media/platform/dwc/Kconfig create mode 100644 drivers/media/platform/dwc/Makefile create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.c create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.h create mode 100644 include/media/dwc/dw-hdmi-rx-pdata.h
drivers/media/platform/Kconfig +2 -0
@@ -29,6 +29,8 @@ source "drivers/media/platform/cadence/Kconfig" source "drivers/media/platform/davinci/Kconfig" +source "drivers/media/platform/dwc/Kconfig" + source "drivers/media/platform/omap/Kconfig" config VIDEO_ASPEED
drivers/media/platform/Makefile +1 -0
@@ -6,6 +6,7 @@ obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro-dvt/ obj-$(CONFIG_VIDEO_ASPEED) += aspeed-video.o obj-$(CONFIG_VIDEO_CADENCE) += cadence/ +obj-y += dwc/ obj-$(CONFIG_VIDEO_VIA_CAMERA) += via-camera.o obj-$(CONFIG_VIDEO_CAFE_CCIC) += marvell-ccic/ obj-$(CONFIG_VIDEO_MMP_CAMERA) += marvell-ccic/
drivers/media/platform/dwc/Kconfig new file +10 -0
@@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +config VIDEO_DWC_HDMI_RX + tristate "Synopsys DesignWare HDMI Receiver driver" + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + help + Support for Synopsys DesignWare HDMI RX Controller. + This driver supports HDMI 2.0 version. + + To compile this driver as a module, choose M here. The module + will be called dw-hdmi-rx.
drivers/media/platform/dwc/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_VIDEO_DWC_HDMI_RX) += dw-hdmi-rx.o
drivers/media/platform/dwc/dw-hdmi-rx.c new file +3239 -0
2,972 lines not on this page · raw message
drivers/media/platform/dwc/dw-hdmi-rx.h new file +476 -0
476 lines not on this page · raw message
include/media/dwc/dw-hdmi-rx-pdata.h new file +126 -0
126 lines not on this page · raw message
The rest of this diff is not shown. View the raw message.
Signature · 1 line
2.7.4
Part of the diff is not shown here. View the raw message.
RFC 6/8 media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
In reply to Nelson CostaThis extends the support for more video format timings based on SPECs CEA-861-F and CTA-861-G.
NOTE: For the newer SPECs the CEA was unified to the CTA. The CTA-861-G then includes the CEA-861-F timings besides the new timings that are specified.
CEA-861-F: Specifies the Video timings for VICs 1-107.
CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219.
With this patch, the array v4l2_dv_timings_presets has support for all video timings specified in CTA-861-G.
--- drivers/media/v4l2-core/v4l2-dv-timings.c | 139 +++ include/uapi/linux/v4l2-dv-timings.h | 1595 ++++++++++++++++++++++++++++- 2 files changed, 1733 insertions(+), 1 deletion(-)
drivers/media/v4l2-core/v4l2-dv-timings.c +139 -0
@@ -133,6 +133,145 @@ const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {V4L2_DV_BT_CEA_4096X2160P50 ,V4L2_DV_BT_DMT_4096X2160P59_94_RB ,V4L2_DV_BT_CEA_4096X2160P60 , +V4L2_DV_BT_CEA_720X480P60_PA16_9 , +V4L2_DV_BT_CEA_720X480I60_PA16_9 , +V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3 , +V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3 , +V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9 , +V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9 , +V4L2_DV_BT_CEA_2880X480I60_PA4_3 , +V4L2_DV_BT_CEA_2880X480I60_PA16_9 , +V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3 , +V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3 , +V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9 , +V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9 , +V4L2_DV_BT_CEA_1440X480P60_PA4_3 , +V4L2_DV_BT_CEA_1440X480P60_PA16_9 , +V4L2_DV_BT_CEA_720X576P50_PA16_9 , +V4L2_DV_BT_CEA_1920X1080I50_PA16_9 , +V4L2_DV_BT_CEA_720X576I50_PA16_9 , +V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3 , +V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3 , +V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3 , +V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9 , +V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9 , +V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9 , +V4L2_DV_BT_CEA_2880X576I50_PA4_3 , +V4L2_DV_BT_CEA_2880X576I50_PA16_9 , +V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3 , +V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3 , +V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3 , +V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9 , +V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9 , +V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9 , +V4L2_DV_BT_CEA_1440X576P50_PA4_3 , +V4L2_DV_BT_CEA_1440X576P50_PA16_9 , +V4L2_DV_BT_CEA_2880X480P60_PA4_3 , +V4L2_DV_BT_CEA_2880X480P60_PA16_9 , +V4L2_DV_BT_CEA_2880X576P50_PA4_3 , +V4L2_DV_BT_CEA_2880X576P50_PA16_9 , +V4L2_DV_BT_CEA_1920X1080I50_PA16_9 , +V4L2_DV_BT_CEA_1920X1080I100_PA16_9 , +V4L2_DV_BT_CEA_1280X720P100_PA16_9 , +V4L2_DV_BT_CEA_720X576P100_PA4_3 , +V4L2_DV_BT_CEA_720X576P100_PA16_9 , +V4L2_DV_BT_CEA_1440X576I100_PA4_3 , +V4L2_DV_BT_CEA_1440X576I100_PA16_9 , +V4L2_DV_BT_CEA_1920X1080I120_PA16_9 , +V4L2_DV_BT_CEA_1280X720P120_PA16_9 , +V4L2_DV_BT_CEA_720X480P120_PA4_3 , +V4L2_DV_BT_CEA_720X480P120_PA16_9 , +V4L2_DV_BT_CEA_1440X480I120_PA4_3 , +V4L2_DV_BT_CEA_1440X480I120_PA16_9 , +V4L2_DV_BT_CEA_720X576P200_PA4_3 , +V4L2_DV_BT_CEA_720X576P200_PA16_9 , +V4L2_DV_BT_CEA_1440X576I200_PA4_3 , +V4L2_DV_BT_CEA_1440X576I200_PA16_9 , +V4L2_DV_BT_CEA_720X480P240_PA4_3 , +V4L2_DV_BT_CEA_720X480P240_PA16_9 , +V4L2_DV_BT_CEA_1440X480I240_PA4_3 , +V4L2_DV_BT_CEA_1440X480I240_PA16_9 , +V4L2_DV_BT_CEA_1920X1080P120_PA16_9 , +V4L2_DV_BT_CEA_1920X1080P100_PA16_9 , +V4L2_DV_BT_CEA_1280X720P24_PA64_27 , +V4L2_DV_BT_CEA_1280X720P25_PA64_27 , +V4L2_DV_BT_CEA_1280X720P30_PA64_27 , +V4L2_DV_BT_CEA_1280X720P50_PA64_27 , +V4L2_DV_BT_CEA_1280X720P60_PA64_27 , +V4L2_DV_BT_CEA_1280X720P100_PA64_27 , +V4L2_DV_BT_CEA_1280X720P120_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P24_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P25_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P30_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P50_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P60_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P100_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P120_PA64_27 , +V4L2_DV_BT_CEA_1680X720P24_PA64_27 , +V4L2_DV_BT_CEA_1680X720P25_PA64_27 , +V4L2_DV_BT_CEA_1680X720P30_PA64_27 , +V4L2_DV_BT_CEA_1680X720P50_PA64_27 , +V4L2_DV_BT_CEA_1680X720P60_PA64_27 , +V4L2_DV_BT_CEA_1680X720P100_PA64_27 , +V4L2_DV_BT_CEA_1680X720P120_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P24_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P25_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P30_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P50_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P60_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P100_PA64_27 , +V4L2_DV_BT_CEA_2560X1080P120_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P24_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P25_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P30_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P50_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P60_PA64_27 , +V4L2_DV_BT_CEA_1280X720P48_PA16_9 , +V4L2_DV_BT_CEA_1280X720P48_PA64_27 , +V4L2_DV_BT_CEA_1680X720P48_PA64_27 , +V4L2_DV_BT_CEA_1920X1080P48_PA16_9 , +V4L2_DV_BT_CEA_1920X1080P48_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P48_PA16_9 , +V4L2_DV_BT_CEA_4096X2160P48_PA256_135 , +V4L2_DV_BT_CEA_3840X2160P48_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P100_PA16_9 , +V4L2_DV_BT_CEA_3840X2160P120_PA16_9 , +V4L2_DV_BT_CEA_3840X2160P100_PA64_27 , +V4L2_DV_BT_CEA_3840X2160P120_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P24_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P25_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P30_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P48_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P50_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P60_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P100_PA64_27 , +V4L2_DV_BT_CEA_5120X2160P120_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P24_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P25_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P30_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P48_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P50_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P60_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P100_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P120_PA16_9 , +V4L2_DV_BT_CEA_7680X4320P24_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P25_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P30_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P48_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P50_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P60_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P100_PA64_27 , +V4L2_DV_BT_CEA_7680X4320P120_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P24_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P25_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P30_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P48_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P50_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P60_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P100_PA64_27 , +V4L2_DV_BT_CEA_10240X4320P120_PA64_27 , +V4L2_DV_BT_CEA_4096X2160P100_PA256_135 , + V4L2_DV_BT_CEA_4096X2160P120_PA256_135, { } };EXPORT_SYMBOL_GPL (v4l2_dv_timings_presets);
include/uapi/linux/v4l2-dv-timings.h +1594 -1
1,607 lines not on this page · raw message
Signature · 1 line
2.7.4
kernel test robot
build botRe: [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 base: git://linuxtv.org/media_tree.git master config: powerpc64-randconfig-r034-20210428 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 87fc97169e7901dfe56ca0da0d92da0c02d2ef48)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# install powerpc64 cross compiling tool for clang build
# apt-get install binutils-powerpc64-linux-gnu
# https://github.com/0day-ci/linux/commit/a0e7878053f9c2570d83cc3165c2ec58b8aa6526
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 git checkout a0e7878053f9c2570d83cc3165c2ec58b8aa6526
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/media/v4l2-core/v4l2-dv-timings.c:252:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1632:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P48_PA16_9'
2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:253:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1644:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P50_PA16_9'
2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:254:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1655:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P60_PA16_9'
2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:260:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1725:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P48_PA64_27'
2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:261:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1737:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P50_PA64_27'
2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:262:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1748:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P60_PA64_27'
2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:268:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1818:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P48_PA64_27'
2970000000, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:269:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1830:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P50_PA64_27'
2970000000, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:270:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1841:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P60_PA64_27'
2970000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \
^9 warnings generated.
vim +252 drivers/media/v4l2-core/v4l2-dv-timings.c
23
24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
25 V4L2_DV_BT_CEA_640X480P59_94,
26 V4L2_DV_BT_CEA_720X480I59_94,
27 V4L2_DV_BT_CEA_720X480P59_94,
28 V4L2_DV_BT_CEA_720X576I50,
29 V4L2_DV_BT_CEA_720X576P50,
30 V4L2_DV_BT_CEA_1280X720P24,
31 V4L2_DV_BT_CEA_1280X720P25,
32 V4L2_DV_BT_CEA_1280X720P30,
33 V4L2_DV_BT_CEA_1280X720P50,
34 V4L2_DV_BT_CEA_1280X720P60,
35 V4L2_DV_BT_CEA_1920X1080P24,
36 V4L2_DV_BT_CEA_1920X1080P25,
37 V4L2_DV_BT_CEA_1920X1080P30,
38 V4L2_DV_BT_CEA_1920X1080I50,
39 V4L2_DV_BT_CEA_1920X1080P50,
40 V4L2_DV_BT_CEA_1920X1080I60,
41 V4L2_DV_BT_CEA_1920X1080P60,
42 V4L2_DV_BT_DMT_640X350P85,
43 V4L2_DV_BT_DMT_640X400P85,
44 V4L2_DV_BT_DMT_720X400P85,
45 V4L2_DV_BT_DMT_640X480P72,
46 V4L2_DV_BT_DMT_640X480P75,
47 V4L2_DV_BT_DMT_640X480P85,
48 V4L2_DV_BT_DMT_800X600P56,
49 V4L2_DV_BT_DMT_800X600P60,
50 V4L2_DV_BT_DMT_800X600P72,
51 V4L2_DV_BT_DMT_800X600P75,
52 V4L2_DV_BT_DMT_800X600P85,
53 V4L2_DV_BT_DMT_800X600P120_RB,
54 V4L2_DV_BT_DMT_848X480P60,
55 V4L2_DV_BT_DMT_1024X768I43,
56 V4L2_DV_BT_DMT_1024X768P60,
57 V4L2_DV_BT_DMT_1024X768P70,
58 V4L2_DV_BT_DMT_1024X768P75,
59 V4L2_DV_BT_DMT_1024X768P85,
60 V4L2_DV_BT_DMT_1024X768P120_RB,
61 V4L2_DV_BT_DMT_1152X864P75,
62 V4L2_DV_BT_DMT_1280X768P60_RB,
63 V4L2_DV_BT_DMT_1280X768P60,
64 V4L2_DV_BT_DMT_1280X768P75,
65 V4L2_DV_BT_DMT_1280X768P85,
66 V4L2_DV_BT_DMT_1280X768P120_RB,
67 V4L2_DV_BT_DMT_1280X800P60_RB,
68 V4L2_DV_BT_DMT_1280X800P60,
69 V4L2_DV_BT_DMT_1280X800P75,
70 V4L2_DV_BT_DMT_1280X800P85,
71 V4L2_DV_BT_DMT_1280X800P120_RB,
72 V4L2_DV_BT_DMT_1280X960P60,
73 V4L2_DV_BT_DMT_1280X960P85,
74 V4L2_DV_BT_DMT_1280X960P120_RB,
75 V4L2_DV_BT_DMT_1280X1024P60,
76 V4L2_DV_BT_DMT_1280X1024P75,
77 V4L2_DV_BT_DMT_1280X1024P85,
78 V4L2_DV_BT_DMT_1280X1024P120_RB,
79 V4L2_DV_BT_DMT_1360X768P60,
80 V4L2_DV_BT_DMT_1360X768P120_RB,
81 V4L2_DV_BT_DMT_1366X768P60,
82 V4L2_DV_BT_DMT_1366X768P60_RB,
83 V4L2_DV_BT_DMT_1400X1050P60_RB,
84 V4L2_DV_BT_DMT_1400X1050P60,
85 V4L2_DV_BT_DMT_1400X1050P75,
86 V4L2_DV_BT_DMT_1400X1050P85,
87 V4L2_DV_BT_DMT_1400X1050P120_RB,
88 V4L2_DV_BT_DMT_1440X900P60_RB,
89 V4L2_DV_BT_DMT_1440X900P60,
90 V4L2_DV_BT_DMT_1440X900P75,
91 V4L2_DV_BT_DMT_1440X900P85,
92 V4L2_DV_BT_DMT_1440X900P120_RB,
93 V4L2_DV_BT_DMT_1600X900P60_RB,
94 V4L2_DV_BT_DMT_1600X1200P60,
95 V4L2_DV_BT_DMT_1600X1200P65,
96 V4L2_DV_BT_DMT_1600X1200P70,
97 V4L2_DV_BT_DMT_1600X1200P75,
98 V4L2_DV_BT_DMT_1600X1200P85,
99 V4L2_DV_BT_DMT_1600X1200P120_RB,
100 V4L2_DV_BT_DMT_1680X1050P60_RB,
101 V4L2_DV_BT_DMT_1680X1050P60,
102 V4L2_DV_BT_DMT_1680X1050P75,
103 V4L2_DV_BT_DMT_1680X1050P85,
104 V4L2_DV_BT_DMT_1680X1050P120_RB,
105 V4L2_DV_BT_DMT_1792X1344P60,
106 V4L2_DV_BT_DMT_1792X1344P75,
107 V4L2_DV_BT_DMT_1792X1344P120_RB,
108 V4L2_DV_BT_DMT_1856X1392P60,
109 V4L2_DV_BT_DMT_1856X1392P75,
110 V4L2_DV_BT_DMT_1856X1392P120_RB,
111 V4L2_DV_BT_DMT_1920X1200P60_RB,
112 V4L2_DV_BT_DMT_1920X1200P60,
113 V4L2_DV_BT_DMT_1920X1200P75,
114 V4L2_DV_BT_DMT_1920X1200P85,
115 V4L2_DV_BT_DMT_1920X1200P120_RB,
116 V4L2_DV_BT_DMT_1920X1440P60,
117 V4L2_DV_BT_DMT_1920X1440P75,
118 V4L2_DV_BT_DMT_1920X1440P120_RB,
119 V4L2_DV_BT_DMT_2048X1152P60_RB,
120 V4L2_DV_BT_DMT_2560X1600P60_RB,
121 V4L2_DV_BT_DMT_2560X1600P60,
122 V4L2_DV_BT_DMT_2560X1600P75,
123 V4L2_DV_BT_DMT_2560X1600P85,
124 V4L2_DV_BT_DMT_2560X1600P120_RB,
125 V4L2_DV_BT_CEA_3840X2160P24,
126 V4L2_DV_BT_CEA_3840X2160P25,
127 V4L2_DV_BT_CEA_3840X2160P30,
128 V4L2_DV_BT_CEA_3840X2160P50,
129 V4L2_DV_BT_CEA_3840X2160P60,
130 V4L2_DV_BT_CEA_4096X2160P24,
131 V4L2_DV_BT_CEA_4096X2160P25,
132 V4L2_DV_BT_CEA_4096X2160P30,
133 V4L2_DV_BT_CEA_4096X2160P50,
134 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
135 V4L2_DV_BT_CEA_4096X2160P60,
136 V4L2_DV_BT_CEA_720X480P60_PA16_9,
137 V4L2_DV_BT_CEA_720X480I60_PA16_9,
138 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
139 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
140 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
141 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
142 V4L2_DV_BT_CEA_2880X480I60_PA4_3,
143 V4L2_DV_BT_CEA_2880X480I60_PA16_9,
144 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
145 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
146 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
147 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
148 V4L2_DV_BT_CEA_1440X480P60_PA4_3,
149 V4L2_DV_BT_CEA_1440X480P60_PA16_9,
150 V4L2_DV_BT_CEA_720X576P50_PA16_9,
151 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
152 V4L2_DV_BT_CEA_720X576I50_PA16_9,
153 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
154 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
155 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
156 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
157 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
158 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
159 V4L2_DV_BT_CEA_2880X576I50_PA4_3,
160 V4L2_DV_BT_CEA_2880X576I50_PA16_9,
161 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
162 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
163 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
164 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
165 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
166 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
167 V4L2_DV_BT_CEA_1440X576P50_PA4_3,
168 V4L2_DV_BT_CEA_1440X576P50_PA16_9,
169 V4L2_DV_BT_CEA_2880X480P60_PA4_3,
170 V4L2_DV_BT_CEA_2880X480P60_PA16_9,
171 V4L2_DV_BT_CEA_2880X576P50_PA4_3,
172 V4L2_DV_BT_CEA_2880X576P50_PA16_9,
173 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
174 V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
175 V4L2_DV_BT_CEA_1280X720P100_PA16_9,
176 V4L2_DV_BT_CEA_720X576P100_PA4_3,
177 V4L2_DV_BT_CEA_720X576P100_PA16_9,
178 V4L2_DV_BT_CEA_1440X576I100_PA4_3,
179 V4L2_DV_BT_CEA_1440X576I100_PA16_9,
180 V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
181 V4L2_DV_BT_CEA_1280X720P120_PA16_9,
182 V4L2_DV_BT_CEA_720X480P120_PA4_3,
183 V4L2_DV_BT_CEA_720X480P120_PA16_9,
184 V4L2_DV_BT_CEA_1440X480I120_PA4_3,
185 V4L2_DV_BT_CEA_1440X480I120_PA16_9,
186 V4L2_DV_BT_CEA_720X576P200_PA4_3,
187 V4L2_DV_BT_CEA_720X576P200_PA16_9,
188 V4L2_DV_BT_CEA_1440X576I200_PA4_3,
189 V4L2_DV_BT_CEA_1440X576I200_PA16_9,
190 V4L2_DV_BT_CEA_720X480P240_PA4_3,
191 V4L2_DV_BT_CEA_720X480P240_PA16_9,
192 V4L2_DV_BT_CEA_1440X480I240_PA4_3,
193 V4L2_DV_BT_CEA_1440X480I240_PA16_9,
194 V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
195 V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
196 V4L2_DV_BT_CEA_1280X720P24_PA64_27,
197 V4L2_DV_BT_CEA_1280X720P25_PA64_27,
198 V4L2_DV_BT_CEA_1280X720P30_PA64_27,
199 V4L2_DV_BT_CEA_1280X720P50_PA64_27,
200 V4L2_DV_BT_CEA_1280X720P60_PA64_27,
201 V4L2_DV_BT_CEA_1280X720P100_PA64_27,
202 V4L2_DV_BT_CEA_1280X720P120_PA64_27,
203 V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
204 V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
205 V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
206 V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
207 V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
208 V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
209 V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
210 V4L2_DV_BT_CEA_1680X720P24_PA64_27,
211 V4L2_DV_BT_CEA_1680X720P25_PA64_27,
212 V4L2_DV_BT_CEA_1680X720P30_PA64_27,
213 V4L2_DV_BT_CEA_1680X720P50_PA64_27,
214 V4L2_DV_BT_CEA_1680X720P60_PA64_27,
215 V4L2_DV_BT_CEA_1680X720P100_PA64_27,
216 V4L2_DV_BT_CEA_1680X720P120_PA64_27,
217 V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
218 V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
219 V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
220 V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
221 V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
222 V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
223 V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
224 V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
225 V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
226 V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
227 V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
228 V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
229 V4L2_DV_BT_CEA_1280X720P48_PA16_9,
230 V4L2_DV_BT_CEA_1280X720P48_PA64_27,
231 V4L2_DV_BT_CEA_1680X720P48_PA64_27,
232 V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
233 V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
234 V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
235 V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
236 V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
237 V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
238 V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
239 V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
240 V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
241 V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
242 V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
243 V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
244 V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
245 V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
246 V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
247 V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
248 V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
249 V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
250 V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
251 V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
> 252 V4L2_DV_BT_CEA_7680X4320P48_PA16_9, 253 V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
254 V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
255 V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
256 V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
257 V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
258 V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
259 V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
260 V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
261 V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
262 V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
263 V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
264 V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
265 V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
266 V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
267 V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
268 V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
269 V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
270 V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
271 V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
272 V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
273 V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
274 V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
275 { }
276 };
277 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
kernel test robot
build botRe: [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
In reply to Nelson Costa[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 base: git://linuxtv.org/media_tree.git master config: i386-randconfig-p001-20210428 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/a0e7878053f9c2570d83cc3165c2ec58b8aa6526 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828 git checkout a0e7878053f9c2570d83cc3165c2ec58b8aa6526 # save the attached .config to linux build tree make W=1 W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/media/v4l2-core/v4l2-dv-timings.c:252:2: warning: this decimal constant is unsigned only in ISO C90
252 | V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:253:2: warning: this decimal constant is unsigned only in ISO C90
253 | V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:254:2: warning: this decimal constant is unsigned only in ISO C90
254 | V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:260:2: warning: this decimal constant is unsigned only in ISO C90
260 | V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:261:2: warning: this decimal constant is unsigned only in ISO C90
261 | V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:262:2: warning: this decimal constant is unsigned only in ISO C90
262 | V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:268:2: warning: this decimal constant is unsigned only in ISO C90
268 | V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:269:2: warning: this decimal constant is unsigned only in ISO C90
269 | V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:270:2: warning: this decimal constant is unsigned only in ISO C90
270 | V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~vim +252 drivers/media/v4l2-core/v4l2-dv-timings.c
23
24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
25 V4L2_DV_BT_CEA_640X480P59_94,
26 V4L2_DV_BT_CEA_720X480I59_94,
27 V4L2_DV_BT_CEA_720X480P59_94,
28 V4L2_DV_BT_CEA_720X576I50,
29 V4L2_DV_BT_CEA_720X576P50,
30 V4L2_DV_BT_CEA_1280X720P24,
31 V4L2_DV_BT_CEA_1280X720P25,
32 V4L2_DV_BT_CEA_1280X720P30,
33 V4L2_DV_BT_CEA_1280X720P50,
34 V4L2_DV_BT_CEA_1280X720P60,
35 V4L2_DV_BT_CEA_1920X1080P24,
36 V4L2_DV_BT_CEA_1920X1080P25,
37 V4L2_DV_BT_CEA_1920X1080P30,
38 V4L2_DV_BT_CEA_1920X1080I50,
39 V4L2_DV_BT_CEA_1920X1080P50,
40 V4L2_DV_BT_CEA_1920X1080I60,
41 V4L2_DV_BT_CEA_1920X1080P60,
42 V4L2_DV_BT_DMT_640X350P85,
43 V4L2_DV_BT_DMT_640X400P85,
44 V4L2_DV_BT_DMT_720X400P85,
45 V4L2_DV_BT_DMT_640X480P72,
46 V4L2_DV_BT_DMT_640X480P75,
47 V4L2_DV_BT_DMT_640X480P85,
48 V4L2_DV_BT_DMT_800X600P56,
49 V4L2_DV_BT_DMT_800X600P60,
50 V4L2_DV_BT_DMT_800X600P72,
51 V4L2_DV_BT_DMT_800X600P75,
52 V4L2_DV_BT_DMT_800X600P85,
53 V4L2_DV_BT_DMT_800X600P120_RB,
54 V4L2_DV_BT_DMT_848X480P60,
55 V4L2_DV_BT_DMT_1024X768I43,
56 V4L2_DV_BT_DMT_1024X768P60,
57 V4L2_DV_BT_DMT_1024X768P70,
58 V4L2_DV_BT_DMT_1024X768P75,
59 V4L2_DV_BT_DMT_1024X768P85,
60 V4L2_DV_BT_DMT_1024X768P120_RB,
61 V4L2_DV_BT_DMT_1152X864P75,
62 V4L2_DV_BT_DMT_1280X768P60_RB,
63 V4L2_DV_BT_DMT_1280X768P60,
64 V4L2_DV_BT_DMT_1280X768P75,
65 V4L2_DV_BT_DMT_1280X768P85,
66 V4L2_DV_BT_DMT_1280X768P120_RB,
67 V4L2_DV_BT_DMT_1280X800P60_RB,
68 V4L2_DV_BT_DMT_1280X800P60,
69 V4L2_DV_BT_DMT_1280X800P75,
70 V4L2_DV_BT_DMT_1280X800P85,
71 V4L2_DV_BT_DMT_1280X800P120_RB,
72 V4L2_DV_BT_DMT_1280X960P60,
73 V4L2_DV_BT_DMT_1280X960P85,
74 V4L2_DV_BT_DMT_1280X960P120_RB,
75 V4L2_DV_BT_DMT_1280X1024P60,
76 V4L2_DV_BT_DMT_1280X1024P75,
77 V4L2_DV_BT_DMT_1280X1024P85,
78 V4L2_DV_BT_DMT_1280X1024P120_RB,
79 V4L2_DV_BT_DMT_1360X768P60,
80 V4L2_DV_BT_DMT_1360X768P120_RB,
81 V4L2_DV_BT_DMT_1366X768P60,
82 V4L2_DV_BT_DMT_1366X768P60_RB,
83 V4L2_DV_BT_DMT_1400X1050P60_RB,
84 V4L2_DV_BT_DMT_1400X1050P60,
85 V4L2_DV_BT_DMT_1400X1050P75,
86 V4L2_DV_BT_DMT_1400X1050P85,
87 V4L2_DV_BT_DMT_1400X1050P120_RB,
88 V4L2_DV_BT_DMT_1440X900P60_RB,
89 V4L2_DV_BT_DMT_1440X900P60,
90 V4L2_DV_BT_DMT_1440X900P75,
91 V4L2_DV_BT_DMT_1440X900P85,
92 V4L2_DV_BT_DMT_1440X900P120_RB,
93 V4L2_DV_BT_DMT_1600X900P60_RB,
94 V4L2_DV_BT_DMT_1600X1200P60,
95 V4L2_DV_BT_DMT_1600X1200P65,
96 V4L2_DV_BT_DMT_1600X1200P70,
97 V4L2_DV_BT_DMT_1600X1200P75,
98 V4L2_DV_BT_DMT_1600X1200P85,
99 V4L2_DV_BT_DMT_1600X1200P120_RB,
100 V4L2_DV_BT_DMT_1680X1050P60_RB,
101 V4L2_DV_BT_DMT_1680X1050P60,
102 V4L2_DV_BT_DMT_1680X1050P75,
103 V4L2_DV_BT_DMT_1680X1050P85,
104 V4L2_DV_BT_DMT_1680X1050P120_RB,
105 V4L2_DV_BT_DMT_1792X1344P60,
106 V4L2_DV_BT_DMT_1792X1344P75,
107 V4L2_DV_BT_DMT_1792X1344P120_RB,
108 V4L2_DV_BT_DMT_1856X1392P60,
109 V4L2_DV_BT_DMT_1856X1392P75,
110 V4L2_DV_BT_DMT_1856X1392P120_RB,
111 V4L2_DV_BT_DMT_1920X1200P60_RB,
112 V4L2_DV_BT_DMT_1920X1200P60,
113 V4L2_DV_BT_DMT_1920X1200P75,
114 V4L2_DV_BT_DMT_1920X1200P85,
115 V4L2_DV_BT_DMT_1920X1200P120_RB,
116 V4L2_DV_BT_DMT_1920X1440P60,
117 V4L2_DV_BT_DMT_1920X1440P75,
118 V4L2_DV_BT_DMT_1920X1440P120_RB,
119 V4L2_DV_BT_DMT_2048X1152P60_RB,
120 V4L2_DV_BT_DMT_2560X1600P60_RB,
121 V4L2_DV_BT_DMT_2560X1600P60,
122 V4L2_DV_BT_DMT_2560X1600P75,
123 V4L2_DV_BT_DMT_2560X1600P85,
124 V4L2_DV_BT_DMT_2560X1600P120_RB,
125 V4L2_DV_BT_CEA_3840X2160P24,
126 V4L2_DV_BT_CEA_3840X2160P25,
127 V4L2_DV_BT_CEA_3840X2160P30,
128 V4L2_DV_BT_CEA_3840X2160P50,
129 V4L2_DV_BT_CEA_3840X2160P60,
130 V4L2_DV_BT_CEA_4096X2160P24,
131 V4L2_DV_BT_CEA_4096X2160P25,
132 V4L2_DV_BT_CEA_4096X2160P30,
133 V4L2_DV_BT_CEA_4096X2160P50,
134 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
135 V4L2_DV_BT_CEA_4096X2160P60,
136 V4L2_DV_BT_CEA_720X480P60_PA16_9,
137 V4L2_DV_BT_CEA_720X480I60_PA16_9,
138 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
139 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
140 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
141 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
142 V4L2_DV_BT_CEA_2880X480I60_PA4_3,
143 V4L2_DV_BT_CEA_2880X480I60_PA16_9,
144 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
145 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
146 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
147 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
148 V4L2_DV_BT_CEA_1440X480P60_PA4_3,
149 V4L2_DV_BT_CEA_1440X480P60_PA16_9,
150 V4L2_DV_BT_CEA_720X576P50_PA16_9,
151 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
152 V4L2_DV_BT_CEA_720X576I50_PA16_9,
153 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
154 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
155 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
156 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
157 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
158 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
159 V4L2_DV_BT_CEA_2880X576I50_PA4_3,
160 V4L2_DV_BT_CEA_2880X576I50_PA16_9,
161 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
162 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
163 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
164 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
165 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
166 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
167 V4L2_DV_BT_CEA_1440X576P50_PA4_3,
168 V4L2_DV_BT_CEA_1440X576P50_PA16_9,
169 V4L2_DV_BT_CEA_2880X480P60_PA4_3,
170 V4L2_DV_BT_CEA_2880X480P60_PA16_9,
171 V4L2_DV_BT_CEA_2880X576P50_PA4_3,
172 V4L2_DV_BT_CEA_2880X576P50_PA16_9,
173 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
174 V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
175 V4L2_DV_BT_CEA_1280X720P100_PA16_9,
176 V4L2_DV_BT_CEA_720X576P100_PA4_3,
177 V4L2_DV_BT_CEA_720X576P100_PA16_9,
178 V4L2_DV_BT_CEA_1440X576I100_PA4_3,
179 V4L2_DV_BT_CEA_1440X576I100_PA16_9,
180 V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
181 V4L2_DV_BT_CEA_1280X720P120_PA16_9,
182 V4L2_DV_BT_CEA_720X480P120_PA4_3,
183 V4L2_DV_BT_CEA_720X480P120_PA16_9,
184 V4L2_DV_BT_CEA_1440X480I120_PA4_3,
185 V4L2_DV_BT_CEA_1440X480I120_PA16_9,
186 V4L2_DV_BT_CEA_720X576P200_PA4_3,
187 V4L2_DV_BT_CEA_720X576P200_PA16_9,
188 V4L2_DV_BT_CEA_1440X576I200_PA4_3,
189 V4L2_DV_BT_CEA_1440X576I200_PA16_9,
190 V4L2_DV_BT_CEA_720X480P240_PA4_3,
191 V4L2_DV_BT_CEA_720X480P240_PA16_9,
192 V4L2_DV_BT_CEA_1440X480I240_PA4_3,
193 V4L2_DV_BT_CEA_1440X480I240_PA16_9,
194 V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
195 V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
196 V4L2_DV_BT_CEA_1280X720P24_PA64_27,
197 V4L2_DV_BT_CEA_1280X720P25_PA64_27,
198 V4L2_DV_BT_CEA_1280X720P30_PA64_27,
199 V4L2_DV_BT_CEA_1280X720P50_PA64_27,
200 V4L2_DV_BT_CEA_1280X720P60_PA64_27,
201 V4L2_DV_BT_CEA_1280X720P100_PA64_27,
202 V4L2_DV_BT_CEA_1280X720P120_PA64_27,
203 V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
204 V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
205 V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
206 V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
207 V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
208 V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
209 V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
210 V4L2_DV_BT_CEA_1680X720P24_PA64_27,
211 V4L2_DV_BT_CEA_1680X720P25_PA64_27,
212 V4L2_DV_BT_CEA_1680X720P30_PA64_27,
213 V4L2_DV_BT_CEA_1680X720P50_PA64_27,
214 V4L2_DV_BT_CEA_1680X720P60_PA64_27,
215 V4L2_DV_BT_CEA_1680X720P100_PA64_27,
216 V4L2_DV_BT_CEA_1680X720P120_PA64_27,
217 V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
218 V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
219 V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
220 V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
221 V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
222 V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
223 V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
224 V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
225 V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
226 V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
227 V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
228 V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
229 V4L2_DV_BT_CEA_1280X720P48_PA16_9,
230 V4L2_DV_BT_CEA_1280X720P48_PA64_27,
231 V4L2_DV_BT_CEA_1680X720P48_PA64_27,
232 V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
233 V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
234 V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
235 V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
236 V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
237 V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
238 V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
239 V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
240 V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
241 V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
242 V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
243 V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
244 V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
245 V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
246 V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
247 V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
248 V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
249 V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
250 V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
251 V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
> 252 V4L2_DV_BT_CEA_7680X4320P48_PA16_9, 253 V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
254 V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
255 V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
256 V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
257 V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
258 V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
259 V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
260 V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
261 V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
262 V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
263 V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
264 V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
265 V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
266 V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
267 V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
268 V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
269 V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
270 V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
271 V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
272 V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
273 V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
274 V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
275 { }
276 };
277 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC 7/8 media: dwc: dw-hdmi-rx: Add support for Aspect Ratio
In reply to Nelson CostaThis adds support to get aspect ratio for the current video being received and provide the info through v4l2 API query_dv_timings.
--- drivers/media/platform/dwc/dw-hdmi-rx.c | 54 +++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-)
drivers/media/platform/dwc/dw-hdmi-rx.c +52 -2
@@ -2252,13 +2252,31 @@ static u32 dw_hdmi_get_width(struct dw_hdmi_dev *dw_dev)return width; } +static int dw_hdmi_vic_to_cea861 (u8 hdmi_vic) +{ +switch (hdmi_vic) { +case 1 : +return 95 ; +case 2 : +return 94 ; +case 3 : +return 93 ; +case 4 : +return 98 ; +default : +return 0 ; + } +} +static int dw_hdmi_query_dv_timings (struct v4l2_subdev *sd,struct v4l2_dv_timings *timings) {struct dw_hdmi_dev *dw_dev =to_dw_dev (sd);struct v4l2_bt_timings *bt = &timings->bt; +struct v4l2_dv_timings t = {0 };bool is_hdmi_vic;u32 htot, hofs; +u8 cea861_vic;u32 vtot;u8 vic;
@@ -2353,8 +2371,40 @@ static int dw_hdmi_query_dv_timings(struct v4l2_subdev *sd, } } -dev_dbg (dw_dev->dev,"%s: width=%u, height=%u, mbuscode=%u\n" , __func__, - bt->width, bt->height,dw_hdmi_get_mbus_code (dw_dev)); +if (is_hdmi_vic) + cea861_vic =dw_hdmi_vic_to_cea861 (bt->hdmi_vic); +else + cea861_vic = vic; + +/* picture aspect ratio based on v4l2 dv timings array */ +if (v4l2_find_dv_timings_cea861_vic (&t, cea861_vic)) { +/* when the numerator/denominator are zero means that the +* picture aspect ratio is the same of the active measures ratio +*/ +if (!t.bt.picture_aspect.numerator) { +unsigned long n, d; + +rational_best_approximation (t.bt.width, t.bt.height, + t.bt.width, t.bt.height, + &n, &d); + t.bt.picture_aspect.numerator = n; + t.bt.picture_aspect.denominator = d; + } + + bt->picture_aspect = t.bt.picture_aspect; + }else { + bt->picture_aspect.numerator =0 ; + bt->picture_aspect.denominator =0 ; +dev_dbg (dw_dev->dev, +"%s: cea861_vic=%d was not found in v4l2 dv timings" , + __func__, cea861_vic); + } + +dev_dbg (dw_dev->dev, +"%s: width=%u, height=%u, mbuscode=%u, cea861_vic=%d, ar={%d,%d}\n" , + __func__, bt->width, bt->height,dw_hdmi_get_mbus_code (dw_dev), + cea861_vic, bt->picture_aspect.numerator, + bt->picture_aspect.denominator);return 0 ; }
Signature · 1 line
2.7.4
RFC 8/8 media: dwc: dw-hdmi-rx: Add support for CEC
In reply to Nelson CostaThis adds support for the optional HDMI CEC feature for the Synopsys DesignWare HDMI RX Controller.
It uses the generic CEC framework interface.
--- drivers/media/platform/dwc/Kconfig | 10 ++ drivers/media/platform/dwc/dw-hdmi-rx.c | 259 +++++++++++++++++++++++++++++++- drivers/media/platform/dwc/dw-hdmi-rx.h | 57 +++++++ 3 files changed, 324 insertions(+), 2 deletions(-)
drivers/media/platform/dwc/Kconfig +10 -0
@@ -8,3 +8,13 @@ config VIDEO_DWC_HDMI_RX To compile this driver as a module, choose M here. The module will be called dw-hdmi-rx. + +config VIDEO_DWC_HDMI_RX_CEC + bool "Synopsys DesignWare HDMI Receiver CEC support" + depends on VIDEO_DWC_HDMI_RX + select CEC_CORE + help + When selected the Synopsys DesignWare HDMI RX controller + will support the optional HDMI CEC feature. + + It uses the generic CEC framework interface.
drivers/media/platform/dwc/dw-hdmi-rx.c +257 -2
345 lines not on this page · raw message
drivers/media/platform/dwc/dw-hdmi-rx.h +57 -0
69 lines not on this page · raw message
Signature · 1 line
2.7.4