arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
Subsystems (2)
PATCH v2 1/1 arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
A valid implementation choice for the ChooseRandomNonExcludedTag() pseudocode function used by IRG is to behave in the same way as with GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR which must have a non-zero value in order for IRG to properly produce pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value on soft reset and thus may reset to 0. Therefore we must initialize RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves as expected.
--- arch/arm64/mm/proc.S | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/mm/proc.S +12 -0
@@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) msr_s SYS_GCR_EL1, x10 + /* + * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then + * RGSR_EL1.SEED must be non-zero for IRG to produce + * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we + * must initialize it. + */ + mrs x10, CNTVCT_EL0 + ands x10, x10, #SYS_RGSR_EL1_SEED_MASK + csinc x10, x10, xzr, ne + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT + msr_s SYS_RGSR_EL1, x10 + /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr
Signature · 1 line
2.31.1.607.g51e8a6a459-goog
Quoted 9 lines · Peter Collingbourne
A valid implementation choice for the
ChooseRandomNonExcludedTag()pseudocode function used by IRG is to behave in the same way as with GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR which must have a non-zero value in order for IRG to properly produce pseudorandom numbers. However,RGSR_EL1is reset to an UNKNOWN value on soft reset and thus may reset to 0. Therefore we must initialize RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves as expected.
Quoted 4 lines
Signed-off-by Peter Collingbourne <[email protected]>Fixes 3b714d24ef17 ("arm64: mte: CPU feature detection and initial sysreg configuration")Cc <[email protected]> # 5.10
FWIW:
Mark.
Quoted 30 lines
--- arch/arm64/mm/proc.S | 12 ++++++++++++ 1 file changed, 12 insertions(+)arch/arm64/mm/proc.S +12
-0@@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) msr_s SYS_GCR_EL1, x10 + /* + * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then + * RGSR_EL1.SEED must be non-zero for IRG to produce + * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we + * must initialize it. + */ + mrs x10, CNTVCT_EL0 + ands x10, x10, #SYS_RGSR_EL1_SEED_MASK + csinc x10, x10, xzr, ne + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT + msr_s SYS_RGSR_EL1, x10 + /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzrSignature · 1 line
2.31.1.607.g51e8a6a459-goog
Quoted 8 lines · Peter Collingbourne
A valid implementation choice for the
ChooseRandomNonExcludedTag()pseudocode function used by IRG is to behave in the same way as with GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR which must have a non-zero value in order for IRG to properly produce pseudorandom numbers. However,RGSR_EL1is reset to an UNKNOWN value on soft reset and thus may reset to 0. Therefore we must initialize RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves as expected.
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
https://git.kernel.org/arm64/c/37a8024d2655
Signature · 1 line
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