dt-bindings: gpio: stp: convert to json-schema
Subsystems (2)
PATCH v4 1/1 dt-bindings: gpio: stp: convert to json-schema
Convert the Lantiq STP Device Tree binding documentation to json-schema. Add the missing pinctrl property to the example. Add missing lantiq,phy3 and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.
---
Changes since v3:
- Removed description of the reg property.
- Changed regex pattern property.
- Moved lantiq,rising to properties.
Changes since v2:
- Changed phy numbering in description of pattern Properties. Numbering should start with 1.
Changes since v1:
- Renamed node to gpio.
- Dropped default pinctrl from this binding.
- Converted lantiq,phyX to patternProperties.
--- .../bindings/gpio/gpio-stp-xway.txt | 42 -------- .../bindings/gpio/gpio-stp-xway.yaml | 99 +++++++++++++++++++ 2 files changed, 99 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt deleted +0 -42
@@ -1,42 +0,0 @@ -Lantiq SoC Serial To Parallel (STP) GPIO controller - -The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a -peripheral controller used to drive external shift register cascades. At most -3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem -to drive the 2 LSBs of the cascade automatically. - - -Required properties: -- compatible : Should be "lantiq,gpio-stp-xway" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). -- gpio-controller : Marks the device node as a gpio controller. - -Optional properties: -- lantiq,shadow : The default value that we shall assume as already set on the - shift register cascade. -- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled - in the shift register cascade. -- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit - property can enable this feature. -- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. -- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. -- lantiq,rising : use rising instead of falling edge for the shift register - -Example: - -gpio1: stp@e100bb0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x3>; - lantiq,phy1 = <0x7>; - lantiq,phy2 = <0x7>; - /* lantiq,rising; */ -};
Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml new file +99 -0
99 lines not on this page · raw message
Signature · 1 line
2.30.2
Quoted 18 lines · Aleksander Jan Bajkowski
Convert the Lantiq STP Device Tree binding documentation to json-schema. Add the missing pinctrl property to the example. Add missing lantiq,phy3 and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.
Signed-off-by Aleksander Jan Bajkowski <[email protected]>Acked-by Linus Walleij <[email protected]>---
Changes since v3:
- Removed description of the reg property.
- Changed regex pattern property.
- Moved lantiq,rising to properties.
Changes since v2:
- Changed phy numbering in description of pattern Properties. Numbering should start with 1.
Changes since v1:
- Renamed node to gpio.
- Dropped default pinctrl from this binding.
- Converted lantiq,phyX to patternProperties.
Quoted 7 lines
--- .../bindings/gpio/gpio-stp-xway.txt | 42 -------- .../bindings/gpio/gpio-stp-xway.yaml | 99 +++++++++++++++++++ 2 files changed, 99 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
Bartosz Golaszewski
AppliedQuoted 8 lines · Aleksander Jan Bajkowski
Convert the Lantiq STP Device Tree binding documentation to json-schema. Add the missing pinctrl property to the example. Add missing lantiq,phy3 and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.
Signed-off-by Aleksander Jan Bajkowski <[email protected]>Acked-by Linus Walleij <[email protected]>---
Applied, thanks!
Bartosz