Add OTG mode support to Tegra USB PHY, SMB347 and Nexus 7
Subsystems (6)
v5 cover Add OTG mode support to Tegra USB PHY, SMB347 and Nexus 7
Hi,
This series adds USB OTG mode support to the NVIDIA Tegra USB PHY driver, SMB347 charger driver and Nexus 7 tablet.
Changelog:
v5: - Replaced "Remove caching of charger state" patch with "Utilize
generic regmap caching" after Sebastian's notice about disabled regmap caching.
v4: - Added r-b from Rob Herring.
- Added unevaluatedProperties into SMB binding for VBUS regulator, which was Requested by Rob Herring.
- Added cell to nvidia,pmc phandle instead of explicit h/w ID property. Requested by Rob Herring.
- Added stack trace to commit message and ack from Peter Chen to OTG FSM patch.
v3: - Further improved interrupt handling in the PHY driver by removing
assumption that interrupt is enabled by the CI driver at the time of set_wakeup() invocation, which makes this function a bit more universal.
v2: - The PHY's interrupt is now enabled from PHY's set_wakeup() callback.
It prevents getting a spurious interrupt during the CI driver probe time.
Dmitry Osipenko (12):
dt-bindings: phy: tegra20-usb-phy: Convert to schema
dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG
mode
soc/tegra: pmc: Expose USB regmap to all SoCs
usb: phy: tegra: Support OTG mode programming
usb: otg-fsm: Fix hrtimer list corruption
dt-bindings: power: supply: smb347-charger: Document USB VBUS
regulator
power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe
power: supply: smb347-charger: Utilize generic regmap caching
power: supply: smb347-charger: Implement USB VBUS regulator
ARM: tegra: Add new properties to USB PHY device-tree nodes
ARM: tegra: nexus7: Enable USB OTG mode
arm64: tegra132: Add new properties to USB PHY device-tree node
.../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 373 ++++++++++++++++++ .../power/supply/summit,smb347-charger.yaml | 30 ++ arch/arm/boot/dts/tegra114.dtsi | 4 + arch/arm/boot/dts/tegra124.dtsi | 6 + arch/arm/boot/dts/tegra20.dtsi | 6 + .../tegra30-asus-nexus7-grouper-common.dtsi | 25 +- arch/arm/boot/dts/tegra30.dtsi | 6 + arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 + drivers/power/supply/Kconfig | 1 + drivers/power/supply/smb347-charger.c | 260 +++++++++++- drivers/soc/tegra/pmc.c | 6 +- drivers/usb/common/usb-otg-fsm.c | 6 +- drivers/usb/phy/phy-tegra-usb.c | 197 ++++++++- .../dt-bindings/power/summit,smb347-charger.h | 4 + include/linux/usb/otg-fsm.h | 1 + include/linux/usb/tegra_usb_phy.h | 5 + 17 files changed, 906 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
Signature · 1 line
2.32.0
PATCH v5 1/12 dt-bindings: phy: tegra20-usb-phy: Convert to schema
Convert NVIDIA Tegra20 USB PHY binding to schema.
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Dmitry Osipenko <[email protected]>
--- .../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 357 ++++++++++++++++++ 2 files changed, 357 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt deleted +0 -74
@@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml new file +357 -0
357 lines not on this page · raw message
Signature · 1 line
2.32.0
PATCH v5 2/12 dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode
In reply to Dmitry OsipenkoIn order to support OTG mode we need these new properties:
- interrupt
- nvidia,pmc
Add the new properties to the binding.
Signed-off-by Dmitry Osipenko <[email protected]>
--- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml +16 -0
@@ -77,6 +77,9 @@ properties: - const: timer - const: utmi-pads + interrupts: + maxItems: 1 + resets: oneOf: - maxItems: 1
@@ -199,6 +202,15 @@ properties: maxItems: 1 description: GPIO used to reset the PHY. + nvidia,pmc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to Power Management controller. + - description: USB controller ID. + description: + Phandle to Power Management controller. + required: - compatible - reg
@@ -320,6 +332,7 @@ examples: compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <0 97 4>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -338,6 +351,7 @@ examples: nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; }; - |
@@ -346,6 +360,7 @@ examples: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = <0 21 4>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>,
@@ -354,4 +369,5 @@ examples: resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; };
Signature · 1 line
2.32.0
Re: [PATCH v5 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode
Quoted 5 lines · Dmitry Osipenko
In order to support OTG mode we need these new properties:
- interrupt
- nvidia,pmc
Quoted 7 lines
Add the new properties to the binding.
Signed-off-by Dmitry Osipenko <[email protected]>--- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Reviewed-by Rob Herring <[email protected]>
PATCH v5 3/12 soc/tegra: pmc: Expose USB regmap to all SoCs
In reply to Dmitry OsipenkoAll Tegra SoCs prior to Tegra186 have USB power controls within the Power Management controller. These controls need to be configured by USB driver. Expose the regmap to these SoCs.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/soc/tegra/pmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/soc/tegra/pmc.c +3 -3
@@ -3202,7 +3202,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, };static const char *const tegra30_powergates[] = {
@@ -3263,7 +3263,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, };static const char *const tegra114_powergates[] = {
@@ -3320,7 +3320,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, };static const char *const tegra124_powergates[] = {
Signature · 1 line
2.32.0
PATCH v5 4/12 usb: phy: tegra: Support OTG mode programming
In reply to Dmitry OsipenkoSupport programming USB PHY into OTG mode.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/usb/phy/phy-tegra-usb.c | 197 +++++++++++++++++++++++++++++- include/linux/usb/tegra_usb_phy.h | 5 + 2 files changed, 197 insertions(+), 5 deletions(-)
drivers/usb/phy/phy-tegra-usb.c +192 -5
@@ -63,6 +63,10 @@#define A_VBUS_VLD_WAKEUP_EN BIT(30)#define USB_PHY_VBUS_WAKEUP_ID 0x408 +#define ID_INT_EN BIT(0) +#define ID_CHG_DET BIT(1) +#define VBUS_WAKEUP_INT_EN BIT(8) +#define VBUS_WAKEUP_CHG_DET BIT(9)#define VBUS_WAKEUP_STS BIT(10)#define VBUS_WAKEUP_WAKEUP_EN BIT(30)
@@ -158,6 +162,10 @@#define USB_USBMODE_HOST (3 << 0)#define USB_USBMODE_DEVICE (2 << 0) +#define PMC_USB_AO 0xf0 +#define VBUS_WAKEUP_PD_P0 BIT(2) +#define ID_PD_P0 BIT(3) +static DEFINE_SPINLOCK (utmip_pad_lock);static unsigned int utmip_pad_count;
@@ -533,13 +541,14 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) val &= ~USB_WAKE_ON_RESUME_EN ;writel_relaxed (val, base +USB_SUSP_CTRL ); -if (phy->mode ==USB_DR_MODE_PERIPHERAL ) { +if (phy->mode !=USB_DR_MODE_HOST ) { val =readl_relaxed (base +USB_SUSP_CTRL ); val &= ~(USB_WAKE_ON_CNNT_EN_DEV |USB_WAKE_ON_DISCON_EN_DEV );writel_relaxed (val, base +USB_SUSP_CTRL ); val =readl_relaxed (base +USB_PHY_VBUS_WAKEUP_ID ); val &= ~VBUS_WAKEUP_WAKEUP_EN ; + val &= ~(ID_CHG_DET |VBUS_WAKEUP_CHG_DET );writel_relaxed (val, base +USB_PHY_VBUS_WAKEUP_ID ); val =readl_relaxed (base +USB_PHY_VBUS_SENSORS );
@@ -687,9 +696,10 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy)* Ask VBUS sensor to generate wake event once cable is * connected. */ -if (phy->mode ==USB_DR_MODE_PERIPHERAL ) { +if (phy->mode !=USB_DR_MODE_HOST ) { val =readl_relaxed (base +USB_PHY_VBUS_WAKEUP_ID ); val |=VBUS_WAKEUP_WAKEUP_EN ; + val &= ~(ID_CHG_DET |VBUS_WAKEUP_CHG_DET );writel_relaxed (val, base +USB_PHY_VBUS_WAKEUP_ID ); val =readl_relaxed (base +USB_PHY_VBUS_SENSORS );
@@ -904,26 +914,146 @@ static void tegra_usb_phy_shutdown(struct usb_phy *u_phy) phy->freq =NULL ; } +static irqreturn_t tegra_usb_phy_isr (int irq,void *data) +{ +u32 val, int_mask =ID_CHG_DET |VBUS_WAKEUP_CHG_DET ; +struct tegra_usb_phy *phy = data; +void __iomem *base = phy->regs; + +/* +* The PHY interrupt also wakes the USB controller driver since +* interrupt is shared. We don't do anything in the PHY driver, +* so just clear the interrupt. +*/ + val =readl_relaxed (base +USB_PHY_VBUS_WAKEUP_ID ); +writel_relaxed (val, base +USB_PHY_VBUS_WAKEUP_ID ); + +return val & int_mask ?IRQ_HANDLED :IRQ_NONE ; +} +static int tegra_usb_phy_set_wakeup (struct usb_phy *u_phy,bool enable) {struct tegra_usb_phy *phy =to_tegra_usb_phy (u_phy); +void __iomem *base = phy->regs; +int ret =0 ; +u32 val; + +if (phy->wakeup_enabled && phy->mode !=USB_DR_MODE_HOST && + phy->irq >0 ) { +disable_irq (phy->irq); + + val =readl_relaxed (base +USB_PHY_VBUS_WAKEUP_ID ); + val &= ~(ID_INT_EN |VBUS_WAKEUP_INT_EN ); +writel_relaxed (val, base +USB_PHY_VBUS_WAKEUP_ID ); + +enable_irq (phy->irq); + +free_irq (phy->irq, phy); + + phy->wakeup_enabled = false; + } + +if (enable && phy->mode !=USB_DR_MODE_HOST && phy->irq >0 ) { + ret =request_irq (phy->irq, tegra_usb_phy_isr,IRQF_SHARED , +dev_name (phy->u_phy.dev), phy); +if (!ret) { +disable_irq (phy->irq); + +/* +* USB clock will be resumed once wake event will be +* generated. The ID-change event requires to have +* interrupts enabled, otherwise it won't be generated. +*/ + val =readl_relaxed (base +USB_PHY_VBUS_WAKEUP_ID ); + val |=ID_INT_EN |VBUS_WAKEUP_INT_EN ; +writel_relaxed (val, base +USB_PHY_VBUS_WAKEUP_ID ); + +enable_irq (phy->irq); + }else { +dev_err (phy->u_phy.dev, +"Failed to request interrupt: %d" , ret); + enable = false; + } + } phy->wakeup_enabled = enable; -return 0 ; +return ret; }static int tegra_usb_phy_set_suspend (struct usb_phy *u_phy,int suspend) {struct tegra_usb_phy *phy =to_tegra_usb_phy (u_phy); +int ret;if (WARN_ON (!phy->freq))return -EINVAL ; +/* +* PHY is sharing IRQ with the CI driver, hence here we either +* disable interrupt for both PHY and CI or for CI only. The +* interrupt needs to be disabled while hardware is reprogrammed +* because interrupt touches the programmed registers, and thus, +* there could be a race condition. +*/ +if (phy->irq >0 ) +disable_irq (phy->irq); +if (suspend) -return tegra_usb_phy_power_off (phy); + ret =tegra_usb_phy_power_off (phy);else -return tegra_usb_phy_power_on (phy); + ret =tegra_usb_phy_power_on (phy); + +if (phy->irq >0 ) +enable_irq (phy->irq); + +return ret; +} + +static int tegra_usb_phy_configure_pmc (struct tegra_usb_phy *phy) +{ +int err, val =0 ; + +/* older device-trees don't have PMC regmap */ +if (!phy->pmc_regmap) +return 0 ; + +/* +* Tegra20 has a different layout of PMC USB register bits and AO is +* enabled by default after system reset on Tegra20, so assume nothing +* to do on Tegra20. +*/ +if (!phy->soc_config->requires_pmc_ao_power_up) +return 0 ; + +/* enable VBUS wake-up detector */ +if (phy->mode !=USB_DR_MODE_HOST ) + val |=VBUS_WAKEUP_PD_P0 << phy->instance *4 ; + +/* enable ID-pin ACC detector for OTG mode switching */ +if (phy->mode ==USB_DR_MODE_OTG ) + val |=ID_PD_P0 << phy->instance *4 ; + +/* disable detectors to reset them */ + err =regmap_set_bits (phy->pmc_regmap,PMC_USB_AO , val); +if (err) { +dev_err (phy->u_phy.dev,"Failed to disable PMC AO: %d\n" , err); +return err; + } + +usleep_range (10 ,100 ); + +/* enable detectors */ + err =regmap_clear_bits (phy->pmc_regmap,PMC_USB_AO , val); +if (err) { +dev_err (phy->u_phy.dev,"Failed to enable PMC AO: %d\n" , err); +return err; + } + +/* detectors starts to work after 10ms */ +usleep_range (10000 ,15000 ); + +return 0 ; }static int tegra_usb_phy_init (struct usb_phy *u_phy)
@@ -967,6 +1097,10 @@ static int tegra_usb_phy_init(struct usb_phy *u_phy) goto disable_vbus; } + err =tegra_usb_phy_configure_pmc (phy); +if (err) + goto close_phy; + err =tegra_usb_phy_power_on (phy);if (err) goto close_phy;
@@ -1135,11 +1269,56 @@ static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,return 0 ; } +static void tegra_usb_phy_put_pmc_device (void *dev) +{ +put_device (dev); +} + +static int tegra_usb_phy_parse_pmc (struct device *dev, +struct tegra_usb_phy *phy) +{ +struct platform_device *pmc_pdev; +struct of_phandle_args args; +int err; + + err =of_parse_phandle_with_fixed_args (dev->of_node,"nvidia,pmc" , +1 ,0 , &args); +if (err) { +if (err != -ENOENT ) +return err; + +dev_warn_once (dev,"nvidia,pmc is missing, please update your device-tree\n" ); +return 0 ; + } + + pmc_pdev =of_find_device_by_node (args.np); +of_node_put (args.np); +if (!pmc_pdev) +return -ENODEV ; + + err =devm_add_action_or_reset (dev, tegra_usb_phy_put_pmc_device, + &pmc_pdev->dev); +if (err) +return err; + +if (!platform_get_drvdata (pmc_pdev)) +return -EPROBE_DEFER ; + + phy->pmc_regmap =dev_get_regmap (&pmc_pdev->dev,"usb_sleepwalk" ); +if (!phy->pmc_regmap) +return -EINVAL ; + + phy->instance = args.args[0 ]; + +return 0 ; +} +static const struct tegra_phy_soc_config tegra20_soc_config = { .utmi_pll_config_in_car_module = false, .has_hostpc = false, .requires_usbmode_setup = false, .requires_extra_tuning_parameters = false, + .requires_pmc_ao_power_up = false, };static const struct tegra_phy_soc_config tegra30_soc_config = {
@@ -1147,6 +1326,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = { .has_hostpc = true, .requires_usbmode_setup = true, .requires_extra_tuning_parameters = true, + .requires_pmc_ao_power_up = true, };static const struct of_device_id tegra_usb_phy_id_table[] = {
@@ -1172,6 +1352,7 @@ static int tegra_usb_phy_probe(struct platform_device *pdev)return -ENOMEM ; tegra_phy->soc_config =of_device_get_match_data (&pdev->dev); + tegra_phy->irq =platform_get_irq_optional (pdev,0 ); res =platform_get_resource (pdev,IORESOURCE_MEM ,0 );if (!res) {
@@ -1215,6 +1396,12 @@ static int tegra_usb_phy_probe(struct platform_device *pdev)return err; } + err =tegra_usb_phy_parse_pmc (&pdev->dev, tegra_phy); +if (err) { +dev_err_probe (&pdev->dev, err,"Failed to get PMC regmap\n" ); +return err; + } + phy_type =of_usb_get_phy_mode (np);switch (phy_type) {case USBPHY_INTERFACE_MODE_UTMI :
include/linux/usb/tegra_usb_phy.h +5 -0
@@ -18,6 +18,7 @@#include <linux/clk.h> #include <linux/gpio.h> +#include <linux/regmap.h> #include <linux/reset.h> #include <linux/usb/otg.h>
@@ -30,6 +31,7 @@* enter host mode * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level * and hsdiscon_level should be set for adequate signal quality +* requires_pmc_ao_power_up: true if USB AO is powered down by default */ struct tegra_phy_soc_config {
@@ -37,6 +39,7 @@ struct tegra_phy_soc_config {bool has_hostpc;bool requires_usbmode_setup;bool requires_extra_tuning_parameters; +bool requires_pmc_ao_power_up; };struct tegra_utmip_config {
@@ -62,6 +65,7 @@ enum tegra_usb_phy_port_speed {struct tegra_xtal_freq ;struct tegra_usb_phy { +int irq;int instance;const struct tegra_xtal_freq *freq;void __iomem *regs;
@@ -70,6 +74,7 @@ struct tegra_usb_phy {struct clk *pll_u;struct clk *pad_clk;struct regulator *vbus; +struct regmap *pmc_regmap;enum usb_dr_mode mode;void *config;const struct tegra_phy_soc_config *soc_config;
Signature · 1 line
2.32.0
PATCH v5 5/12 usb: otg-fsm: Fix hrtimer list corruption
In reply to Dmitry OsipenkoThe HNP work can be re-scheduled while it's still in-fly. This results in re-initialization of the busy work, resetting the hrtimer's list node of the work and crashing kernel with null dereference within kernel/timer once work's timer is expired. It's very easy to trigger this problem by re-plugging USB cable quickly. Initialize HNP work only once to fix this trouble.
Unable to handle kernel NULL pointer dereference at virtual address 00000126) ... PC is at __run_timers.part.0+0x150/0x228 LR is at __next_timer_interrupt+0x51/0x9c ... (__run_timers.part.0) from [<c0187a2b>] (run_timer_softirq+0x2f/0x50) (run_timer_softirq) from [<c01013ad>] (__do_softirq+0xd5/0x2f0) (__do_softirq) from [<c012589b>] (irq_exit+0xab/0xb8) (irq_exit) from [<c0170341>] (handle_domain_irq+0x45/0x60) (handle_domain_irq) from [<c04c4a43>] (gic_handle_irq+0x6b/0x7c) (gic_handle_irq) from [<c0100b65>] (__irq_svc+0x65/0xac)
Acked-by Peter Chen <[email protected]>
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/usb/common/usb-otg-fsm.c | 6 +++++- include/linux/usb/otg-fsm.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-)
drivers/usb/common/usb-otg-fsm.c +5 -1
@@ -193,7 +193,11 @@ static void otg_start_hnp_polling(struct otg_fsm *fsm)if (!fsm->host_req_flag)return ; -INIT_DELAYED_WORK (&fsm->hnp_polling_work, otg_hnp_polling_work); +if (!fsm->hnp_work_inited) { +INIT_DELAYED_WORK (&fsm->hnp_polling_work, otg_hnp_polling_work); + fsm->hnp_work_inited = true; + } +schedule_delayed_work (&fsm->hnp_polling_work,msecs_to_jiffies (T_HOST_REQ_POLL )); }
include/linux/usb/otg-fsm.h +1 -0
@@ -196,6 +196,7 @@ struct otg_fsm {struct mutex lock;u8 *host_req_flag;struct delayed_work hnp_polling_work; +bool hnp_work_inited;bool state_changed; };
Signature · 1 line
2.32.0
PATCH v5 6/12 dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator
In reply to Dmitry OsipenkoSMB347 can supply power to USB VBUS, which is required by OTG-cable devices that want to switch USB port into the host mode. Add USB VBUS regulator properties.
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Dmitry Osipenko <[email protected]>
--- .../power/supply/summit,smb347-charger.yaml | 30 +++++++++++++++++++ .../dt-bindings/power/summit,smb347-charger.h | 4 +++ 2 files changed, 34 insertions(+)
Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml +30 -0
@@ -73,6 +73,26 @@ properties: - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + summit,inok-polarity: + description: | + Polarity of INOK signal indicating presence of external power supply. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW + - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH + + usb-vbus: + $ref: "../../regulator/regulator.yaml#" + type: object + + properties: + summit,needs-inok-toggle: + type: boolean + description: INOK signal is fixed and polarity needs to be toggled + in order to enable/disable output mode. + + unevaluatedProperties: false + allOf: - if: properties:
@@ -134,6 +154,7 @@ examples: reg = <0x7f>; summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH>; + summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; summit,chip-temperature-threshold-celsius = <110>; summit,mains-current-limit-microamp = <2000000>; summit,usb-current-limit-microamp = <500000>;
@@ -141,6 +162,15 @@ examples: summit,enable-mains-charging; monitored-battery = <&battery>; + + usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + summit,needs-inok-toggle; + }; }; };
include/dt-bindings/power/summit,smb347-charger.h +4 -0
@@ -16,4 +16,8 @@#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 +/* Polarity of INOK signal */ +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 +#endif
Signature · 1 line
2.32.0
PATCH v5 7/12 power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe
In reply to Dmitry OsipenkoThe smb347_set_writable() is used by interrupt handler and outside of it. The interrupt should be disabled when the function is used outside of interrupt handler in order to prevent racing with the interrupt context. Add new parameter to smb347_set_writable() that allows to disable IRQ.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/power/supply/smb347-charger.c | 30 +++++++++++++++++++-------- 1 file changed, 21 insertions(+), 9 deletions(-)
drivers/power/supply/smb347-charger.c +21 -9
@@ -671,10 +671,22 @@ static int smb347_set_temp_limits(struct smb347_charger *smb)* * Returns %0 on success and negative errno in case of failure. */ -static int smb347_set_writable (struct smb347_charger *smb,bool writable) +static int smb347_set_writable (struct smb347_charger *smb,bool writable, +bool irq_toggle) { -return regmap_update_bits (smb->regmap,CMD_A ,CMD_A_ALLOW_WRITE , - writable ?CMD_A_ALLOW_WRITE :0 ); +struct i2c_client *client =to_i2c_client (smb->dev); +int ret; + +if (writable && irq_toggle && !smb->irq_unsupported) +disable_irq (client->irq); + + ret =regmap_update_bits (smb->regmap,CMD_A ,CMD_A_ALLOW_WRITE , + writable ?CMD_A_ALLOW_WRITE :0 ); + +if ((!writable || ret) && irq_toggle && !smb->irq_unsupported) +enable_irq (client->irq); + +return ret; }static int smb347_hw_init (struct smb347_charger *smb)
@@ -682,7 +694,7 @@ static int smb347_hw_init(struct smb347_charger *smb)unsigned int val;int ret; - ret =smb347_set_writable (smb, true); + ret =smb347_set_writable (smb, true, false);if (ret <0 )return ret;
@@ -758,7 +770,7 @@ static int smb347_hw_init(struct smb347_charger *smb) ret =smb347_start_stop_charging (smb); fail: -smb347_set_writable (smb, false); +smb347_set_writable (smb, false, false);return ret; }
@@ -866,7 +878,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable)if (smb->irq_unsupported)return 0 ; - ret =smb347_set_writable (smb, true); + ret =smb347_set_writable (smb, true, true);if (ret <0 )return ret;
@@ -891,7 +903,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable) ret =regmap_update_bits (smb->regmap,CFG_PIN ,CFG_PIN_EN_CHARGER_ERROR , enable ?CFG_PIN_EN_CHARGER_ERROR :0 ); fail: -smb347_set_writable (smb, false); +smb347_set_writable (smb, false, true);return ret; }
@@ -919,7 +931,7 @@ static int smb347_irq_init(struct smb347_charger *smb,if (!client->irq)return 0 ; - ret =smb347_set_writable (smb, true); + ret =smb347_set_writable (smb, true, false);if (ret <0 )return ret;
@@ -931,7 +943,7 @@ static int smb347_irq_init(struct smb347_charger *smb,CFG_STAT_ACTIVE_HIGH |CFG_STAT_DISABLED , CFG_STAT_DISABLED); -smb347_set_writable (smb, false); +smb347_set_writable (smb, false, false);if (ret <0 ) {dev_warn (smb->dev,"failed to initialize IRQ: %d\n" , ret);
Signature · 1 line
2.32.0
PATCH v5 8/12 power: supply: smb347-charger: Utilize generic regmap caching
In reply to Dmitry OsipenkoUtilize generic regmap caching in order to avoid unnecessary slow I2C accesses each time the supply status updated and remove local caching of charger state to make code cleaner.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/power/supply/smb347-charger.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-)
drivers/power/supply/smb347-charger.c +3 -12
@@ -135,7 +135,6 @@* @id: SMB charger ID * @mains_online: is AC/DC input connected * @usb_online: is USB input connected -* @charging_enabled: is charging enabled * @irq_unsupported: is interrupt unsupported by SMB hardware * @max_charge_current: maximum current (in uA) the battery can be charged * @max_charge_voltage: maximum voltage (in uV) the battery can be charged
@@ -192,7 +191,6 @@ struct smb347_charger {unsigned int id;bool mains_online;bool usb_online; -bool charging_enabled;bool irq_unsupported;unsigned int max_charge_current;
@@ -358,21 +356,13 @@ static int smb347_charging_status(struct smb347_charger *smb)static int smb347_charging_set (struct smb347_charger *smb,bool enable) { -int ret =0 ; -if (smb->enable_control !=SMB3XX_CHG_ENABLE_SW ) {dev_dbg (smb->dev,"charging enable/disable in SW disabled\n" );return 0 ; } -if (smb->charging_enabled != enable) { - ret =regmap_update_bits (smb->regmap,CMD_A ,CMD_A_CHG_ENABLED , - enable ?CMD_A_CHG_ENABLED :0 ); -if (!ret) - smb->charging_enabled = enable; - } - -return ret; +return regmap_update_bits (smb->regmap,CMD_A ,CMD_A_CHG_ENABLED , + enable ?CMD_A_CHG_ENABLED :0 ); }static inline int smb347_charging_enable (struct smb347_charger *smb)
@@ -1310,6 +1300,7 @@ static const struct regmap_config smb347_regmap = { .max_register = SMB347_MAX_REGISTER, .volatile_reg = smb347_volatile_reg, .readable_reg = smb347_readable_reg, + .cache_type = REGCACHE_FLAT, };static const struct power_supply_desc smb347_mains_desc = {
Signature · 1 line
2.32.0
PATCH v5 9/12 power: supply: smb347-charger: Implement USB VBUS regulator
In reply to Dmitry OsipenkoSMB347 can supply power to USB VBUS, implement the USB VBUS regulator. USB VBUS needs to be powered for switching OTG-cable USB port into host mode.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/power/supply/Kconfig | 1 + drivers/power/supply/smb347-charger.c | 219 ++++++++++++++++++++++++++ 2 files changed, 220 insertions(+)
drivers/power/supply/Kconfig +1 -0
@@ -694,6 +694,7 @@ config CHARGER_BQ256XX config CHARGER_SMB347 tristate "Summit Microelectronics SMB3XX Battery Charger" depends on I2C + depends on REGULATOR select REGMAP_I2C help Say Y to include support for Summit Microelectronics SMB345,
drivers/power/supply/smb347-charger.c +219 -0
332 lines not on this page · raw message
Signature · 1 line
2.32.0
PATCH v5 10/12 ARM: tegra: Add new properties to USB PHY device-tree nodes
In reply to Dmitry OsipenkoAdd new properties to USB PHYs needed for enabling USB OTG mode.
Signed-off-by Dmitry Osipenko <[email protected]>
--- arch/arm/boot/dts/tegra114.dtsi | 4 ++++ arch/arm/boot/dts/tegra124.dtsi | 6 ++++++ arch/arm/boot/dts/tegra20.dtsi | 6 ++++++ arch/arm/boot/dts/tegra30.dtsi | 6 ++++++ 4 files changed, 22 insertions(+)
arch/arm/boot/dts/tegra114.dtsi +4 -0
@@ -706,6 +706,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000>, <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>, <&tegra_car TEGRA114_CLK_PLL_U>,
@@ -725,6 +726,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; };
@@ -744,6 +746,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>, <&tegra_car TEGRA114_CLK_PLL_U>,
@@ -762,6 +765,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };
arch/arm/boot/dts/tegra124.dtsi +6 -0
@@ -1094,6 +1094,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d000000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1113,6 +1114,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; };
@@ -1132,6 +1134,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d004000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1150,6 +1153,7 @@ phy2: usb-phy@7d004000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; };
@@ -1169,6 +1173,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d008000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1187,6 +1192,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };
arch/arm/boot/dts/tegra20.dtsi +6 -0
@@ -875,6 +875,7 @@ phy1: usb-phy@c5000000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5000000 0x4000>, <0xc5000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USBD>, <&tegra_car TEGRA20_CLK_PLL_U>,
@@ -893,6 +894,7 @@ phy1: usb-phy@c5000000 { nvidia,xcvr-lsfslew = <1>; nvidia,xcvr-lsrslew = <1>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; };
@@ -913,6 +915,7 @@ usb@c5004000 { phy2: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>,
@@ -921,6 +924,7 @@ phy2: usb-phy@c5004000 { resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; };
@@ -942,6 +946,7 @@ phy3: usb-phy@c5008000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5008000 0x4000>, <0xc5000000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USB3>, <&tegra_car TEGRA20_CLK_PLL_U>,
@@ -958,6 +963,7 @@ phy3: usb-phy@c5008000 { nvidia,xcvr-setup = <9>; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };
arch/arm/boot/dts/tegra30.dtsi +6 -0
@@ -1143,6 +1143,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000>, <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>, <&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1163,6 +1164,7 @@ phy1: usb-phy@7d000000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; };
@@ -1184,6 +1186,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d004000 0x4000>, <0x7d000000 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1203,6 +1206,7 @@ phy2: usb-phy@7d004000 { nvidia,xcvr-hsslew = <32>; nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; };
@@ -1224,6 +1228,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>, <&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1243,6 +1248,7 @@ phy3: usb-phy@7d008000 { nvidia,xcvr-hsslew = <32>; nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };
Signature · 1 line
2.32.0
PATCH v5 11/12 ARM: tegra: nexus7: Enable USB OTG mode
In reply to Dmitry OsipenkoNexus 7 has OTG-cable microUSB port, enable OTG mode. USB peripheral devices now can be connected to Nexus 7 using OTG adapter, switching USB port into host mode.
Signed-off-by Dmitry Osipenko <[email protected]>
--- .../tegra30-asus-nexus7-grouper-common.dtsi | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +23 -2
@@ -941,9 +941,29 @@ power_supply: charger@6a { interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; + summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; summit,enable-usb-charging; monitored-battery = <&battery_cell>; + + usb_vbus: usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + + /* + * SMB347 INOK input pin is connected to PMIC's + * ACOK output, which is fixed to ACTIVE_LOW as + * long as battery voltage is in a good range. + * + * Active INOK disables SMB347 output, so polarity + * needs to be toggled when we want to get the + * output. + */ + summit,needs-inok-toggle; + }; }; };
@@ -1017,12 +1037,13 @@ sdmmc4: mmc@78000600 { usb@7d000000 { compatible = "nvidia,tegra30-udc"; status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; + vbus-supply = <&usb_vbus>; }; usb-phy@7d000000 { status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; nvidia,hssync-start-delay = <0>; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>;
Signature · 1 line
2.32.0
PATCH v5 12/12 arm64: tegra132: Add new properties to USB PHY device-tree node
In reply to Dmitry OsipenkoAdd new properties to USB PHYs needed for enabling USB OTG mode.
Signed-off-by Dmitry Osipenko <[email protected]>
--- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/nvidia/tegra132.dtsi +6 -0
@@ -1123,6 +1123,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d000000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1142,6 +1143,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; };
@@ -1162,6 +1164,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d004000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1180,6 +1183,7 @@ phy2: usb-phy@7d004000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; };
@@ -1200,6 +1204,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d008000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1218,6 +1223,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };
Signature · 1 line
2.32.0
17.07.2021 21:21, Dmitry Osipenko пишет:
...
Quoted 3 lines
power: supply: smb347-charger: Make
smb347_set_writable()IRQ-safe
power: supply: smb347-charger: Utilize generic regmap caching
power: supply: smb347-charger: Implement USB VBUS regulator
I noticed that charging doesn't work properly now, will fix it in v6.
30.07.2021 20:37, Dmitry Osipenko пишет:
Quoted 8 lines
17.07.2021 21:21, Dmitry Osipenko пишет:
...Quoted 3 lines
power: supply: smb347-charger: Make
smb347_set_writable()IRQ-safe
power: supply: smb347-charger: Utilize generic regmap caching
power: supply: smb347-charger: Implement USB VBUS regulatorI noticed that charging doesn't work properly now, will fix it in v6.
For the record, it wasn't enough to enable the regmap caching, we also need to fill up the cache on init by specifying the num_reg_defaults_raw parameter.
This uncovered another problem where the pin control "enable" bit was unsettling because the default regmap values were initialized to zeros and driver doesn't set the enable bit at all.