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fixes and enablement for rk356x

PATCH Applied Peter Geis 2 participants 13 messages Jul 28, 2021 – Aug 18, 2021

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Device tree bindings Common clk Arm Rockchip
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Peter Geis

author
#0 lore raw

v2 cover fixes and enablement for rk356x

Good Morning,

This series aims to fix some early issues with the rk356x and enable nodes that are currently supported by the available drivers.

1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64

Changelog:
v2:
Drop "dt-bindings: gpio: rockchip,gpio-bank: increase max clocks" Drop "arm64: dts: rockchip: add missing rk3568 cru phandles" Add clk-pll fix patch as suggested by Heiko
Move ethernet alias to Quartz64 board as suggested by Heiko Adjust tsadc pinctrl as suggested by Heiko and Johan Move tsadc mode and polarity to Quartz64 board

Peter Geis (8):
arm64: dts: rockchip: fix rk3568 mbi-alias
clk: rockchip: fix clk-pll rk356x early pll init
arm64: dts: rockchip: add rk356x gpio debounce clocks
arm64: dts: rockchip: add rk356x gmac1 node
arm64: dts: rockchip: add rk3568 tsadc nodes
arm64: dts: rockchip: adjust rk3568 pll clocks
arm64: dts: rockchip: enable gmac node on quartz64-a
arm64: dts: rockchip: add thermal support to Quartz64 Model A

 .../boot/dts/rockchip/rk3566-quartz64-a.dts   |  71 ++++++++++
 .../boot/dts/rockchip/rk3568-pinctrl.dtsi     |   7 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 131 +++++++++++++++++-
 drivers/clk/rockchip/clk-pll.c                |   2 +-
 4 files changed, 204 insertions(+), 7 deletions(-)
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH v2 1/8 arm64: dts: rockchip: fix rk3568 mbi-alias

The mbi-alias incorrectly points to 0xfd100000 when it should point to 0xfd410000.
This fixes MSIs on rk3568.

Fixes a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568

SoC")

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +1 -1
index 322971318d5a..f7ecdfd66f86 100644
@@ -195,7 +195,7 @@ gic: interrupt-controller@fd400000 {
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		mbi-alias = <0x0 0xfd100000>;
+		mbi-alias = <0x0 0xfd410000>;
 		mbi-ranges = <296 24>;
 		msi-controller;
 	};
Signature · 1 line
2.25.1
author
#2 lore raw

PATCH v2 2/8 clk: rockchip: fix clk-pll rk356x early pll init

In reply to Peter Geis

The rk356x needs to reclock certain plls at boot. If the grf phandles are not linked in the cru and pmucru nodes, it is unable to apply any assigned-clock-rates at boot.

Fix this by removing the check for the grf for selecting the utilized operations.

"The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036 and uses their ops. Which in turn means the pll shouldn't access the GRF at all, as it uses the pll's own register to check the locked state."

Suggested-by Heiko Stuebner <[email protected]>

Link:
https://lore.kernel.org/linux-devicetree/[email protected]/

Fixes c9c3c6eecc55 ("clk: rockchip: simplify GRF handling in pll

clocks")

Signed-off-by Peter Geis <[email protected]>
---
 drivers/clk/rockchip/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/rockchip/clk-pll.c +1 -1
index fe937bcdb487..f7827b3b7fc1 100644
@@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	switch (pll_type) {
 	case pll_rk3036:
 	case pll_rk3328:
-		if (!pll->rate_table || IS_ERR(ctx->grf))
+		if (!pll->rate_table)
 			init.ops = &rockchip_rk3036_pll_clk_norate_ops;
 		else
 			init.ops = &rockchip_rk3036_pll_clk_ops;
Signature · 1 line
2.25.1
author
#3 lore raw

PATCH v2 3/8 arm64: dts: rockchip: add rk356x gpio debounce clocks

In reply to Peter Geis

The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind.
Add the clocks to the rk356x device tree.

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +5 -5
index f7ecdfd66f86..c2aa7aeec58d 100644
@@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xfdd60000 0x0 0x100>;
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmucru PCLK_GPIO0>;
+			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

@@ -761,7 +761,7 @@ gpio1: gpio@fe740000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xfe740000 0x0 0x100>;
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>;
+			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

@@ -772,7 +772,7 @@ gpio2: gpio@fe750000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xfe750000 0x0 0x100>;
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>;
+			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

@@ -783,7 +783,7 @@ gpio3: gpio@fe760000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xfe760000 0x0 0x100>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>;
+			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

@@ -794,7 +794,7 @@ gpio4: gpio@fe770000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xfe770000 0x0 0x100>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO4>;
+			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
Signature · 1 line
2.25.1
author
#4 lore raw

PATCH v2 4/8 arm64: dts: rockchip: add rk356x gmac1 node

In reply to Peter Geis

Add the gmac1 controller to the rk356x device tree. This is the controller common to both the rk3568 and rk3566.

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +47 -0
index c2aa7aeec58d..fbd9f1c366ff 100644
@@ -344,6 +344,53 @@ sdmmc2: mmc@fe000000 {
 		status = "disabled";
 	};
 
+	gmac1: ethernet@fe010000 {
+		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+		reg = <0x0 0xfe010000 0x0 0x10000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
+			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
+			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
+			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
+		clock-names = "stmmaceth", "mac_clk_rx",
+			      "mac_clk_tx", "clk_mac_refout",
+			      "aclk_mac", "pclk_mac",
+			      "clk_mac_speed", "ptp_ref";
+		resets = <&cru SRST_A_GMAC1>;
+		reset-names = "stmmaceth";
+		rockchip,grf = <&grf>;
+		snps,mixed-burst;
+		snps,tso;
+		snps,axi-config = <&gmac1_stmmac_axi_setup>;
+		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+		status = "disabled";
+
+		mdio1: mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		gmac1_stmmac_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <4>;
+			snps,rd_osr_lmt = <8>;
+			snps,blen = <0 0 0 0 16 8 4>;
+		};
+
+		gmac1_mtl_rx_setup: rx-queues-config {
+			snps,rx-queues-to-use = <1>;
+			queue0 {};
+		};
+
+		gmac1_mtl_tx_setup: tx-queues-config {
+			snps,tx-queues-to-use = <1>;
+			queue0 {};
+		};
+	};
+
 	qos_gpu: qos@fe128000 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe128000 0x0 0x20>;
Signature · 1 line
2.25.1
author
#5 lore raw

PATCH v2 5/8 arm64: dts: rockchip: add rk3568 tsadc nodes

In reply to Peter Geis

Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu.

Signed-off-by Peter Geis <[email protected]>
---
 .../boot/dts/rockchip/rk3568-pinctrl.dtsi     |  7 ++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 70 +++++++++++++++++++
 2 files changed, 77 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +7 -0
index a588ca95ace2..3b1efaf2646e 100644
@@ -2420,6 +2420,13 @@ spi3m1_cs1: spi3m1-cs1 {
 	};
 
 	tsadc {
+		/omit-if-no-ref/
+		tsadc_pin: tsadc-pin {
+			rockchip,pins =
+				/* tsadc_pin */
+				<0 RK_PA1 0 &pcfg_pull_none>;
+		};
+
 		/omit-if-no-ref/
 		tsadcm0_shut: tsadcm0-shut {
 			rockchip,pins =
arch/arm64/boot/dts/rockchip/rk356x.dtsi +70 -0

100 lines not on this page · raw message

Signature · 1 line
2.25.1
maintainer
#6 lore raw

Re: [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes

Hi Peter, Kever,

Am Mittwoch, 28. Juli 2021, 20:00:31 CEST schrieb Peter Geis:

Quoted 14 lines

Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu.

Signed-off-by Peter Geis <[email protected]>
---
 .../boot/dts/rockchip/rk3568-pinctrl.dtsi     |  7 ++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 70 +++++++++++++++++++
 2 files changed, 77 insertions(+)
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +0 -0
index a588ca95ace2..3b1efaf2646e 100644

arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi spi3m1_cs1: spi3m1-cs1 { · line 2429

Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +7 -0
@@ -2420,6 +2420,13 @@ spi3m1_cs1: spi3m1-cs1 {
 	};
 
 	tsadc {
+		/omit-if-no-ref/
+		tsadc_pin: tsadc-pin {
+			rockchip,pins =
+				/* tsadc_pin */
+				<0 RK_PA1 0 &pcfg_pull_none>;
+		};
+

The rk3568-pinctrl.dtsi is autogenerated on Rockchip's side and I don't want to break that unnecessarily ;-) .

So the question below is more for Kever and Liang:

The tsadc on most mainline Rockchip socs uses the additional init-pinctrl to set the pin to gpio mode before the tsadc probes and only to the shutdown function after the tsadc has probed sucessfully. This prevents the shutdown firing before the tsadc actually attached to the pin function.

Is it possible to fit the above addition pin setting in the database you have as base for the autogeneration?

Thanks
Heiko

Quoted 113 lines
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +0 -0
 		/omit-if-no-ref/
 		tsadcm0_shut: tsadcm0-shut {
 			rockchip,pins =
arch/arm64/boot/dts/rockchip/rk356x.dtsi +70 -0
index fbd9f1c366ff..c74072941da1 100644
@@ -50,6 +50,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x0>;
 			clocks = <&scmi_clk 0>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};

@@ -58,6 +59,7 @@ cpu1: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x100>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};

@@ -66,6 +68,7 @@ cpu2: cpu@200 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x200>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};

@@ -74,6 +77,7 @@ cpu3: cpu@300 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x300>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};

@@ -773,6 +777,72 @@ uart9: serial@fe6d0000 {
 		status = "disabled";
 	};
 
+	thermal_zones: thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_alert1: cpu_alert1 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit: cpu_crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu_thermal: gpu-thermal {
+			polling-delay-passive = <20>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 1>;
+		};
+	};
+
+	tsadc: tsadc@fe710000 {
+		compatible = "rockchip,rk3568-tsadc";
+		reg = <0x0 0xfe710000 0x0 0x100>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
+		assigned-clock-rates = <17000000>, <700000>;
+		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "tsadc", "apb_pclk";
+		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
+			 <&cru SRST_TSADCPHY>;
+		reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
+		rockchip,grf = <&grf>;
+		rockchip,hw-tshut-temp = <95000>;
+		pinctrl-names = "init", "default", "sleep";
+		pinctrl-0 = <&tsadc_pin>;
+		pinctrl-1 = <&tsadc_shutorg>;
+		pinctrl-2 = <&tsadc_pin>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
 	saradc: saradc@fe720000 {
 		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
 		reg = <0x0 0xfe720000 0x0 0x100>;
author
#7 lore raw

PATCH v2 6/8 arm64: dts: rockchip: adjust rk3568 pll clocks

In reply to Peter Geis

The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. These are set incorrectly by the bootloader, so fix them here.

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +2 -0
index c74072941da1..66d1919dd7eb 100644
@@ -226,6 +226,8 @@ cru: clock-controller@fdd20000 {
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+		assigned-clock-rates = <1200000000>, <200000000>;
 	};
 
 	i2c0: i2c@fdd40000 {
Signature · 1 line
2.25.1
author
#8 lore raw

PATCH v2 7/8 arm64: dts: rockchip: enable gmac node on quartz64-a

In reply to Peter Geis

Enable the gmac controller on the Pine64 Quartz64 Model A.

Signed-off-by Peter Geis <[email protected]>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +38 -0
index a3cdb6c2bec6..b239f314b38a 100644
@@ -11,6 +11,7 @@ / {
 	compatible = "pine64,quartz64-a", "rockchip,rk3566";
 
 	aliases {
+		ethernet0 = &gmac1;
 		mmc0 = &sdmmc0;
 		mmc1 = &sdhci;
 	};

@@ -19,6 +20,13 @@ chosen: chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 

@@ -116,6 +124,29 @@ &cpu3 {
 	cpu-supply = <&vdd_cpu>;
 };
 
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 

@@ -336,6 +367,13 @@ regulator-state-mem {
 	};
 };
 
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
 &pinctrl {
 	bt {
 		bt_enable_h: bt-enable-h {
Signature · 1 line
2.25.1
author
#9 lore raw

PATCH v2 8/8 arm64: dts: rockchip: add thermal support to Quartz64 Model A

In reply to Peter Geis

Add the thermal nodes for the Quartz64 Model A.
The Model A supports a single speed gpio fan.

Signed-off-by Peter Geis <[email protected]>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +33 -0
index b239f314b38a..a244f7b87e38 100644
@@ -27,6 +27,14 @@ gmac1_clkin: external-gmac1-clock {
 		#clock-cells = <0>;
 	};
 
+	fan: gpio_fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		gpio-fan,speed-map = <0    0
+				      4500 1>;
+		#cooling-cells = <2>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 

@@ -124,6 +132,23 @@ &cpu3 {
 	cpu-supply = <&vdd_cpu>;
 };
 
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
 &gmac1 {
 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;

@@ -433,6 +458,14 @@ &sdmmc0 {
 	status = "okay";
 };
 
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_xfer>;
Signature · 1 line
2.25.1
maintainer
#10 lore raw

Re: (subset) [PATCH v2 0/8] fixes and enablement for rk356x

In reply to Peter Geis
Quoted 14 lines · Peter Geis

Good Morning,

This series aims to fix some early issues with the rk356x and enable nodes that are currently supported by the available drivers.

1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64

Quoted 1 line

[...]

Applied the easy ones for now, thanks!

[1/8] arm64: dts: rockchip: fix rk3568 mbi-alias

      commit: 0ecf7b9137e05e2ade45b0555b00248cc0b7ac69

-> just put that in for 5.15, as the rk3568 on 5.14 is
still largely a wip

[2/8] clk: rockchip: fix clk-pll rk356x early pll init

      commit: 6fffe52fb336ec2063270a7305652a93ea677ca1

-> I've adapted the commit message here

[4/8] arm64: dts: rockchip: add rk356x gmac1 node

      commit: 6cdca5eb64c6eff6d552b475b6dc9182d84f2a31

-> did a bit of sorting here

[6/8] arm64: dts: rockchip: adjust rk3568 pll clocks

      commit: 66a6450203e2e9bcaf6cb5938e7a9a159234722a

-> adapted commit message with your reply from v1

[7/8] arm64: dts: rockchip: enable gmac node on quartz64-a

      commit: 797fc427ffb9a746d985c5f31e9c14defc1d1187

Best regards,

Signature · 1 line
Heiko Stuebner <[email protected]>
maintainer Applied
#11 lore raw

Re: (subset) [PATCH v2 0/8] fixes and enablement for rk356x

In reply to Peter Geis
Quoted 14 lines · Peter Geis

Good Morning,

This series aims to fix some early issues with the rk356x and enable nodes that are currently supported by the available drivers.

1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64

Quoted 1 line

[...]

Applied, thanks!

[3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks

      commit: bf092ebe6e81fe7f7b710e749a3debfece193ff5

Best regards,

Signature · 1 line
Heiko Stuebner <[email protected]>
maintainer Applied
#12 lore raw

Re: (subset) [PATCH v2 0/8] fixes and enablement for rk356x

In reply to Peter Geis
Quoted 14 lines · Peter Geis

Good Morning,

This series aims to fix some early issues with the rk356x and enable nodes that are currently supported by the available drivers.

1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64

Quoted 1 line

[...]

Applied, thanks!

[5/8] arm64: dts: rockchip: add rk3568 tsadc nodes

      commit: 1a9563ba0a59b221156d80a3a77a43fdd144576c

[I've moved the tsadc-pin pin setting to the second pinctrl
block meant to hand-crafted pin settings in rk3568-pinctrl.dtsi]

[8/8] arm64: dts: rockchip: add thermal support to Quartz64 Model A

      commit: d0e2e61b3cbaab474e2093ceb2073c4441bd36f8

Looks like we're all done with that series now.

Best regards,

Signature · 1 line
Heiko Stuebner <[email protected]>