RISC-V: add LiteX SoC support; resurrect nmon
Subsystems (7)
v3 cover RISC-V: add LiteX SoC support; resurrect nmon
Changes since v2:
* rebase on top of master branch (f873c7ff2497) +
"RISC-V: extend multi-image to support both S- and M-Mode"
(http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
* "litex serial: add setbrg callback" patch by Marek Czerski is added
for review;
* fix "clocksource: timer-riscv: select CSR from device tree" patch;
* change gpio IP-block base addresses in litex dts;
* gpio-74xx-mmio uses device_get_match_data() now.
Changes since v1:
* rebased on top of next branch;
* new patches are introduced:
* clocksource: timer-riscv: select CSR from device tree
* RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
* RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
* almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
* NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data()
Antony Pavlov (9):
clocksource: timer-riscv: select CSR from device tree
RISC-V: make it possible to run nmon from PBL C code
RISC-V: boards: erizo: make it possible to use nmon
serial: add litex UART driver
gpio: add driver for 74xx-ICs with MMIO access
spi: add litex spiflash driver
net: add LiteEth driver
RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
RISC-V: add litex_linux_defconfig
Marek Czerski (1):
litex serial: add setbrg callback
arch/riscv/Kconfig.socs | 14 + arch/riscv/boards/Makefile | 1 + arch/riscv/boards/erizo/lowlevel.c | 4 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++ arch/riscv/boot/Makefile | 1 + arch/riscv/boot/nmon_entry.S | 13 + arch/riscv/configs/litex_linux_defconfig | 76 +++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/erizo.dtsi | 2 + arch/riscv/dts/litex-linux.dts | 92 ++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 ++++++++ arch/riscv/include/asm/riscv_nmon.h | 49 ++- common/Kconfig | 4 + drivers/clocksource/timer-riscv.c | 24 +- drivers/gpio/Kconfig | 14 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165 ++++++++++ drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 +++++++++++++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 103 +++++++ drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++++++++++++++ images/Makefile.riscv | 4 + 29 files changed, 1370 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/boards/litex-linux/Makefile create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c create mode 100644 arch/riscv/boot/nmon_entry.S create mode 100644 arch/riscv/configs/litex_linux_defconfig create mode 100644 arch/riscv/dts/litex-linux.dts create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi create mode 100644 arch/riscv/include/asm/debug_ll_litex.h create mode 100644 drivers/gpio/gpio-74xx-mmio.c create mode 100644 drivers/net/liteeth.c create mode 100644 drivers/serial/serial_litex.c create mode 100644 drivers/spi/litex_spiflash.c
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PATCH v3 1/10 clocksource: timer-riscv: select CSR from device tree
barebox timer-riscv driver supports one of user counters:
* 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
* 'time', timer for RDTIME instruction (CSR 0xc01).
At the moment in M-mode timer-riscv uses the 'cycle' counter, and in S-mode timer-riscv uses the 'time' timer.
Alas picorv32 CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer.
This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode.
--- arch/riscv/dts/erizo.dtsi | 2 ++ drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-)
arch/riscv/dts/erizo.dtsi +2 -0
@@ -22,6 +22,8 @@ timebase-frequency = <24000000>; + barebox,csr-cycle; + cpu@0 { device_type = "cpu"; compatible = "cliffordwolf,picorv32", "riscv";
drivers/clocksource/timer-riscv.c +12 -12
@@ -12,9 +12,8 @@#include <clock.h> #include <asm/timer.h> #include <asm/csr.h> -#include <asm/system.h> -static u64 notrace riscv_timer_get_count_sbi(void) +static u64 notrace riscv_timer_get_count_time(void) {__maybe_unused u32 hi, lo;
@@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)return ((u64 )hi <<32 ) | lo; } -static u64 notrace riscv_timer_get_count_rdcycle(void) +static u64 notrace riscv_timer_get_count_cycle(void) {__maybe_unused u32 hi, lo;
@@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)return ((u64 )hi <<32 ) | lo; } -static u64 notrace riscv_timer_get_count(void) -{ -if (riscv_mode () ==RISCV_S_MODE ) -return riscv_timer_get_count_sbi (); -else -return riscv_timer_get_count_rdcycle (); -} -static struct clocksource riscv_clocksource = { - .read = riscv_timer_get_count, .mask =CLOCKSOURCE_MASK (64 ), .priority =100 , };static int riscv_timer_init (struct device_d * dev) { +struct device_node *cpu; +dev_info (dev,"running at %lu Hz\n" , riscv_timebase); + cpu =of_find_node_by_path ("/cpus" ); + +if (of_property_read_bool (cpu,"barebox,csr-cycle" )) { + riscv_clocksource.read = riscv_timer_get_count_cycle; + }else { + riscv_clocksource.read = riscv_timer_get_count_time; + } + riscv_clocksource.mult =clocksource_hz2mult (riscv_timebase, riscv_clocksource.shift);return init_clock (&riscv_clocksource);
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Re: [PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree
Hi,
Quoted 5 lines · Antony Pavlov
barebox timer-riscv driver supports one of user counters:
* 'cycle', counter for RDCYCLE instruction (CSR
0xc00);
* 'time', timer for RDTIME instruction (CSR0xc01).
Quoted 8 lines
At the moment in M-mode timer-riscv uses the 'cycle' counter, and in S-mode timer-riscv uses the 'time' timer.
Alas picorv32 CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer.
This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode.
It also changes the default for M-Mode from cycle to time. I can't comment on whether this is ok, I just copied the logic from Linux.
Quoted 80 lines
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/dts/erizo.dtsi | 2 ++ drivers/clocksource/timer-riscv.c | 24 ++++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-)arch/riscv/dts/erizo.dtsi +2
-0@@ -22,6 +22,8 @@ timebase-frequency = <24000000>; + barebox,csr-cycle; + cpu@0 { device_type = "cpu"; compatible = "cliffordwolf,picorv32", "riscv";drivers/clocksource/timer-riscv.c +12
-12@@ -12,9 +12,8 @@#include <clock.h> #include <asm/timer.h> #include <asm/csr.h> -#include <asm/system.h> -static u64 notrace riscv_timer_get_count_sbi(void) +static u64 notrace riscv_timer_get_count_time(void) {__maybe_unused u32 hi, lo;@@ -29,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)return ((u64 )hi <<32 ) | lo; } -static u64 notrace riscv_timer_get_count_rdcycle(void) +static u64 notrace riscv_timer_get_count_cycle(void) {__maybe_unused u32 hi, lo;@@ -44,24 +43,25 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)return ((u64 )hi <<32 ) | lo; } -static u64 notrace riscv_timer_get_count(void) -{ -if (riscv_mode () ==RISCV_S_MODE ) -return riscv_timer_get_count_sbi (); -else -return riscv_timer_get_count_rdcycle (); -} -static struct clocksource riscv_clocksource = { - .read = riscv_timer_get_count, .mask =CLOCKSOURCE_MASK (64 ), .priority =100 , };static int riscv_timer_init (struct device_d * dev) { +struct device_node *cpu; +dev_info (dev,"running at %lu Hz\n" , riscv_timebase); + cpu =of_find_node_by_path ("/cpus" ); + +if (of_property_read_bool (cpu,"barebox,csr-cycle" )) { + riscv_clocksource.read = riscv_timer_get_count_cycle; + }else { + riscv_clocksource.read = riscv_timer_get_count_time; + } + riscv_clocksource.mult =clocksource_hz2mult (riscv_timebase, riscv_clocksource.shift);return init_clock (&riscv_clocksource);
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Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 2/10 RISC-V: make it possible to run nmon from PBL C code
In reply to Antony PavlovAfter migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code:
* use 'lla' macro instruction instead of 'la';
* don't touch the 'ra' register, use 'a2' instead;
* add wrapper C function for nmon.
--- arch/riscv/boot/Makefile | 1 + arch/riscv/boot/nmon_entry.S | 13 ++++++++ arch/riscv/include/asm/riscv_nmon.h | 49 +++++++++++++++++++---------- 3 files changed, 46 insertions(+), 17 deletions(-)
arch/riscv/boot/Makefile +1 -0
@@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += start.o pbl-y += entry.o uncompress.o +pbl-y += nmon_entry.o pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o
arch/riscv/boot/nmon_entry.S new file +13 -0
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <linux/linkage.h> +#include <asm/sections.h> + +#include "asm/debug_ll.h" +#include "asm/riscv_nmon.h" + +.section .text_bare_init + +ENTRY(__barebox_nmon_entry) + riscv_nmon + ret +ENDPROC(__barebox_nmon_entry)
arch/riscv/include/asm/riscv_nmon.h +32 -17
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PATCH v3 3/10 RISC-V: boards: erizo: make it possible to use nmon
In reply to Antony Pavlov--- arch/riscv/boards/erizo/lowlevel.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/riscv/boards/erizo/lowlevel.c +4 -0
@@ -3,6 +3,7 @@#include <common.h> #include <asm/barebox-riscv.h> #include <debug_ll.h> +#include <asm/riscv_nmon.h> ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2) {
@@ -10,6 +11,9 @@ ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)void *fdt;debug_ll_init (); + +barebox_nmon_entry (); +putc_ll ('>' );/* On POR, we are running from read-only memory here. */
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PATCH v3 4/10 serial: add litex UART driver
In reply to Antony Pavlov--- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+)
drivers/serial/Makefile +1 -0
@@ -24,3 +24,4 @@ obj-$(CONFIG_DRIVER_SERIAL_DIGIC) += serial_digic.o obj-$(CONFIG_DRIVER_SERIAL_LPUART) += serial_lpuart.o obj-$(CONFIG_VIRTIO_CONSOLE) += virtio_console.o obj-$(CONFIG_SERIAL_SIFIVE) += serial_sifive.o +obj-$(CONFIG_SOC_LITEX) += serial_litex.o
drivers/serial/serial_litex.c new file +96 -0
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PATCH v3 5/10 litex serial: add setbrg callback
In reply to Antony PavlovFrom: Marek Czerski <[email protected]>
setbrg callback (set baudrate) is needed by the loadx/loady commands. Because litex serial has fixed baudrate the callback only checks if the requested baudrate is the same as the CONFIG_BAUDRATE.
--- drivers/serial/serial_litex.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
drivers/serial/serial_litex.c +8 -1
@@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)return !litex_serial_readb (cdev,UART_RXEMPTY ); } +static int litex_setial_setbaudrate (struct console_device *cdev,int baudrate) +{ +if (baudrate !=CONFIG_BAUDRATE ) +return -EINVAL ; +return 0 ; +} +static int litex_serial_probe (struct device_d *dev) {struct resource *iores;
@@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev) cdev->tstc = &litex_serial_tstc; cdev->putc = &litex_serial_putc; cdev->getc = &litex_serial_getc; - cdev->setbrg =NULL ; + cdev->setbrg = &litex_setial_setbaudrate;console_register (cdev);
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Re: [PATCH v3 05/10] litex serial: add setbrg callback
On Tue, 25 May 2021 10:19:47 +0300
Antony Pavlov <[email protected]> wrote:
Hi all!
Quoted 14 lines
From: Marek Czerski <[email protected]>
setbrg callback (set baudrate) is needed by the loadx/loady commands. Because litex serial has fixed baudrate the callback only checks if the requested baudrate is the same as the
CONFIG_BAUDRATE.--- drivers/serial/serial_litex.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)drivers/serial/serial_litex.c +0
-0
drivers/serial/serial_litex.c static int litex_serial_tstc(struct console_device *cdev) · line 67
Quoted 10 lines
drivers/serial/serial_litex.c +7
-0@@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)return !litex_serial_readb (cdev,UART_RXEMPTY ); } +static int litex_setial_setbaudrate (struct console_device *cdev,int baudrate) +{ +if (baudrate !=CONFIG_BAUDRATE ) +return -EINVAL ; +return 0 ; +} +
I have sent this patch separately because it need special attention.
LiteX serial port hardware has fixed baudrate and setbaudrate has no sence. On the other hand absent setnbaudrate() litex serial makes impossible to use Y-modem data trasfer.
I don't like CONFIG_BAUDRATE here. Can we use
if (baudrate != cdev->baudrate) return -EINVAL; return 0;
instead?
Please comment!
To: Ahmad
It looks like CONFIG_BAUDRATE is a one more global defconfig parameter that complicates "one defconfig for all RISC-V boards" approach.
P.S. There is typo in litex_seTial_setbaudrate name. I have noted just now. It should be fixed of cause.
Quoted 15 lines
drivers/serial/serial_litex.c +1
-1static int litex_serial_probe (struct device_d *dev) {struct resource *iores;@@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev) cdev->tstc = &litex_serial_tstc; cdev->putc = &litex_serial_putc; cdev->getc = &litex_serial_getc; - cdev->setbrg =NULL ; + cdev->setbrg = &litex_setial_setbaudrate;console_register (cdev);Signature · 1 line
2.31.1
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Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 05/10] litex serial: add setbrg callback
Hello Antony,
Quoted 39 lines · Antony Pavlov
On Tue, 25 May 2021 10:19:47 +0300
Antony Pavlov <[email protected]> wrote:Hi all!
Quoted 14 lines
From: Marek Czerski <[email protected]>
setbrg callback (set baudrate) is needed by the loadx/loady commands. Because litex serial has fixed baudrate the callback only checks if the requested baudrate is the same as the
CONFIG_BAUDRATE.--- drivers/serial/serial_litex.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)drivers/serial/serial_litex.c +0
-0drivers/serial/serial_litex.c static int litex_serial_tstc(struct console_device *cdev) · line 67
Quoted 10 lines
drivers/serial/serial_litex.c +7
-0@@ -58,6 +58,13 @@ static int litex_serial_tstc(struct console_device *cdev)return !litex_serial_readb (cdev,UART_RXEMPTY ); } +static int litex_setial_setbaudrate (struct console_device *cdev,int baudrate) +{ +if (baudrate !=CONFIG_BAUDRATE ) +return -EINVAL ; +return 0 ; +} +I have sent this patch separately because it need special attention.
LiteX serial port hardware has fixed baudrate and setbaudrate has no sence. On the other hand absent
setnbaudrate()litex serial makes impossible to use Y-modem data trasfer.I don't like
CONFIG_BAUDRATEhere. Can we use
Quoted 7 lines
if (baudrate != cdev->baudrate) return -EINVAL; return 0;instead?
Please comment!
There are other consoles (efi, linux, virtio) that don't support baud rate setting either, so I think it makes sense to solve this outside of the individual console drivers.
One way to go about it is move
if (cdev->baudrate == baudrate)
return 0;
in common/console.c up. Then setting baud rate to the preconfigured value would succeed everywhere.
Quoted 3 lines
To: Ahmad
It looks likeCONFIG_BAUDRATEis a one more global defconfig parameter that complicates "one defconfig for all RISC-V boards" approach.
It's not a deal breaker, users can still use the environment for fine-grained configuration of the baud rate on a per board basis if they indeed want to ship the same barebox configuration for LiteX and something else.
The idea of one-defconfig-for-all is that we don't introduce unneeded mutually- exclusive configurations. This is not the case here.
(I know I still owe you some patches, I will try to get those sent out soon-ish)
Cheers,
Ahmad
Quoted 22 lines
P.S. There is typo inlitex_seTial_setbaudratename. I have noted just now. It should be fixed of cause.Quoted 15 lines
drivers/serial/serial_litex.c +1
-1static int litex_serial_probe (struct device_d *dev) {struct resource *iores;@@ -73,7 +80,7 @@ static int litex_serial_probe(struct device_d *dev) cdev->tstc = &litex_serial_tstc; cdev->putc = &litex_serial_putc; cdev->getc = &litex_serial_getc; - cdev->setbrg =NULL ; + cdev->setbrg = &litex_setial_setbaudrate;console_register (cdev);Signature · 1 line
2.31.1
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Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 6/10 gpio: add driver for 74xx-ICs with MMIO access
In reply to Antony PavlovThis patch adds driver to support GPIO functionality for 74xx-compatible ICs with MMIO access.
Compatible models include:
1 bit: 741G125 (Input), 741G74 (Output)
2 bits: 742G125 (Input), 7474 (Output)
4 bits: 74125 (Input), 74175 (Output)
6 bits: 74365 (Input), 74174 (Output)
8 bits: 74244 (Input), 74273 (Output)
16 bits: 741624 (Input), 7416374 (Output)--- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165 ++++++++++++++++++++++++++++++++++ 3 files changed, 180 insertions(+)
drivers/gpio/Kconfig +14 -0
@@ -21,6 +21,20 @@ config GPIO_74164 shift registers. This driver can be used to provide access to more gpio outputs. +config GPIO_74XX_MMIO + tristate "GPIO driver for 74xx-ICs with MMIO access" + depends on OFDEVICE + select GPIO_GENERIC + help + Say yes here to support GPIO functionality for 74xx-compatible ICs + with MMIO access. Compatible models include: + 1 bit: 741G125 (Input), 741G74 (Output) + 2 bits: 742G125 (Input), 7474 (Output) + 4 bits: 74125 (Input), 74175 (Output) + 6 bits: 74365 (Input), 74174 (Output) + 8 bits: 74244 (Input), 74273 (Output) + 16 bits: 741624 (Input), 7416374 (Output) + config GPIO_CLPS711X bool "GPIO support for CLPS711X" depends on ARCH_CLPS711X || COMPILE_TEST
drivers/gpio/Makefile +1 -0
@@ -1,6 +1,7 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o obj-$(CONFIG_GPIO_74164) += gpio-74164.o +obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o obj-$(CONFIG_MACH_MIPS_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
drivers/gpio/gpio-74xx-mmio.c new file +165 -0
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PATCH v3 7/10 spi: add litex spiflash driver
In reply to Antony Pavlov--- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+)
drivers/spi/Kconfig +3 -0
@@ -74,6 +74,9 @@ config DRIVER_SPI_IMX_2_3 depends on ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 || ARCH_IMX7 || ARCH_IMX8MQ default y +config DRIVER_SPI_LITEX_SPIFLASH + bool "Litex SPIFLASH bitbang master driver" + config DRIVER_SPI_MXS bool "i.MX (23,28) SPI Master driver" depends on ARCH_IMX28
drivers/spi/Makefile +1 -0
@@ -4,6 +4,7 @@ obj-$(CONFIG_DRIVER_SPI_ATH79) += ath79_spi.o obj-$(CONFIG_DRIVER_SPI_GPIO) += gpio_spi.o obj-$(CONFIG_DRIVER_SPI_FSL_QUADSPI) += spi-fsl-qspi.o obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o +obj-$(CONFIG_DRIVER_SPI_LITEX_SPIFLASH) += litex_spiflash.o obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
drivers/spi/litex_spiflash.c new file +241 -0
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PATCH v3 8/10 net: add LiteEth driver
In reply to Antony PavlovLiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LiteEth can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.
See https://github.com/enjoy-digital/liteeth for details.
--- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 385 insertions(+)
drivers/net/Kconfig +8 -0
@@ -271,6 +271,14 @@ config TSE_USE_DEDICATED_DESC_MEM reserved with a malloc but directly mapped to the memory address (defined in config.h) +config DRIVER_NET_LITEETH + bool "LiteX ethernet driver" + select PHYLIB + select MDIO_BITBANG + help + This option enables support for the LiteX LiteEth + ethernet IP core. + source "drivers/net/phy/Kconfig" source "drivers/net/usb/Kconfig"
drivers/net/Makefile +1 -0
@@ -36,3 +36,4 @@ obj-$(CONFIG_DRIVER_NET_TAP) += tap.o obj-$(CONFIG_DRIVER_NET_TSE) += altera_tse.o obj-$(CONFIG_DRIVER_NET_EFI_SNP) += efi-snp.o obj-$(CONFIG_DRIVER_NET_AG71XX) += ag71xx.o +obj-$(CONFIG_DRIVER_NET_LITEETH) += liteeth.o
drivers/net/liteeth.c new file +376 -0
376 lines not on this page · raw message
Signature · 7 lines
2.31.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 9/10 RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
In reply to Antony PavlovLiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.
--- arch/riscv/Kconfig.socs | 14 +++ arch/riscv/boards/Makefile | 1 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/litex-linux.dts | 92 +++++++++++++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++++++++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 +++++++++++++++++++++++ common/Kconfig | 4 + images/Makefile.riscv | 4 + 11 files changed, 316 insertions(+)
arch/riscv/Kconfig.socs +14 -0
@@ -42,4 +42,18 @@ config BOARD_HIFIVE endif +config SOC_LITEX + bool "LiteX SoCs" + depends on ARCH_RV32I + select HAS_ASM_DEBUG_LL + select HAS_NMON + select USE_COMPRESSED_DTB + select RISCV_TIMER + +config BOARD_LITEX_LINUX + bool "litex linux board" + depends on SOC_LITEX + select RISCV_M_MODE + def_bool y + endmenu
arch/riscv/boards/Makefile +1 -0
@@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/ obj-$(CONFIG_BOARD_HIFIVE) += hifive/ +obj-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux/
arch/riscv/boards/litex-linux/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.o
arch/riscv/boards/litex-linux/lowlevel.c new file +22 -0
@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-riscv.h> +#include <debug_ll.h> +#include <asm/riscv_nmon.h> + +ENTRY_FUNCTION(start_litex_linux, a0, a1, a2) +{ +extern char __dtb_z_litex_linux_start[]; +void *fdt; + +barebox_nmon_entry (); + +putc_ll ('>' ); + +/* On POR, we are running from read-only memory here. */ + + fdt = __dtb_z_litex_linux_start +get_runtime_offset (); + +barebox_riscv_machine_entry (0x40000000 ,SZ_256M , fdt); +}
arch/riscv/dts/Makefile +1 -0
@@ -7,5 +7,6 @@ obj- += dummy.o pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \ hifive-unleashed-a00.dtb.o +pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/dts/litex-linux.dts new file +92 -0
92 lines not on this page · raw message
arch/riscv/dts/litex_soc_linux.dtsi new file +49 -0
49 lines not on this page · raw message
arch/riscv/include/asm/debug_ll.h +3 -0
@@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch) writel(ch, uart0); } +#elif defined CONFIG_DEBUG_LITEX + +#include <asm/debug_ll_litex.h> #endif
arch/riscv/include/asm/debug_ll_litex.h new file +123 -0
123 lines not on this page · raw message
common/Kconfig +4 -0
@@ -1379,6 +1379,10 @@ config DEBUG_SIFIVE bool "SiFive serial0 port" depends on SOC_SIFIVE +config DEBUG_LITEX + bool "LiteX serial port" + depends on SOC_LITEX + endchoice config DEBUG_IMX_UART_PORT
images/Makefile.riscv +4 -0
@@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashed FILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img + +pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux +FILE_barebox-litex-linux.img = start_litex_linux.pblb +image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img
Signature · 7 lines
2.31.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
Quoted 6 lines · Antony Pavlov
LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.
What are your steps for testing this? We have a few ECPIX-5 here, so we should be able to reproduce this.
Regards,
Jan
Quoted 442 lines
Signed-off-by Antony Pavlov <[email protected]>---
arch/riscv/Kconfig.socs | 14 +++ arch/riscv/boards/Makefile | 1 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/litex-linux.dts | 92 +++++++++++++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++++++++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 +++++++++++++++++++++++ common/Kconfig | 4 + images/Makefile.riscv | 4 + 11 files changed, 316 insertions(+)arch/riscv/Kconfig.socs +0
-0@@ -42,4 +42,18 @@ config BOARD_HIFIVEendif
arch/riscv/Kconfig.socs +14
-0+config SOC_LITEX + bool "LiteX SoCs" + depends on ARCH_RV32I + select HAS_ASM_DEBUG_LL + select HAS_NMON + select USE_COMPRESSED_DTB + select RISCV_TIMER + +config BOARD_LITEX_LINUX + bool "litex linux board" + depends on SOC_LITEX + select RISCV_M_MODE + def_bool y +endmenu
arch/riscv/boards/Makefile +0
-0@@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/
obj-$(CONFIG_BOARD_HIFIVE) += hifive/arch/riscv/boards/Makefile +1
-0+obj-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux/arch/riscv/boards/litex-linux/Makefile new file +3
-0@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.oarch/riscv/boards/litex-linux/lowlevel.c new file +22
-0@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-riscv.h> +#include <debug_ll.h> +#include <asm/riscv_nmon.h> + +ENTRY_FUNCTION(start_litex_linux, a0, a1, a2) +{ +extern char __dtb_z_litex_linux_start[]; +void *fdt; + +barebox_nmon_entry (); + +putc_ll ('>' ); + +/* On POR, we are running from read-only memory here. */ + + fdt = __dtb_z_litex_linux_start +get_runtime_offset (); + +barebox_riscv_machine_entry (0x40000000 ,SZ_256M , fdt); +}arch/riscv/dts/Makefile +0
-0@@ -7,5 +7,6 @@ obj- += dummy.opbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
hifive-unleashed-a00.dtb.o +pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.oclean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/dts/litex-linux.dts new file +92
-0@@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "litex_soc_linux.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "LiteX VexRiscV-SoC-Linux"; + compatible = "litex,vexriscv-soc-linux"; + + aliases { + rom = &rom; + sram = &sram; + }; + + /* ARTY board */ + rom: rom@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x00008000>; + read-only; + }; + + sram: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x00004000>; + }; + + main_ram: memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mac0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; + +/ { + ledsgpio: gpio@f000a800 { + compatible = "ti,74175"; + reg = <0xf000a800 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + + ld0 { + label = "arty:green:ld0"; + gpios = <&ledsgpio 0 GPIO_ACTIVE_HIGH>; + }; + + ld1 { + label = "arty:green:ld1"; + gpios = <&ledsgpio 1 GPIO_ACTIVE_HIGH>; + }; + + ld2 { + label = "arty:green:ld2"; + gpios = <&ledsgpio 2 GPIO_ACTIVE_HIGH>; + }; + + ld3 { + label = "arty:green:ld3"; + gpios = <&ledsgpio 3 GPIO_ACTIVE_HIGH>; + }; + }; + + swgpio: gpio@f0006000 { + compatible = "ti,74125"; + reg = <0xf0006000 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; +};arch/riscv/dts/litex_soc_linux.dtsi new file +49
-0@@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +/ { + compatible = "litex,vexriscv-soc-linux"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + timebase-frequency = <100000000>; // 100 MHz + + cpu@0 { + device_type = "cpu"; + compatible = "spinalhdl,vexriscv", "riscv"; + reg = <0>; + }; + }; + + uart0: serial@f0001000 { + compatible = "litex,uart"; + reg = <0xf0001000 0x18>; + status = "disabled"; + }; + + mac0: mac@f0009000 { + compatible = "litex,liteeth"; + reg = <0xf0009000 0x7c /* base */ + 0xf0009800 0x0a /* mdio_base */ + 0xb0000000 0x2000>; /* buf_base */ + tx-fifo-depth = <2>; + rx-fifo-depth = <2>; + status = "disabled"; + }; + + spi0: spi@f000b800 { + compatible = "litex,spiflash"; + + #address-cells = <1>; + #size-cells = <0>; + + reg = <0xf000b800 0x100>; + status = "disabled"; + }; +};arch/riscv/include/asm/debug_ll.h +0
-0@@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch)
writel(ch, uart0);
}arch/riscv/include/asm/debug_ll.h +3
-0+#elif definedCONFIG_DEBUG_LITEX + +#include <asm/debug_ll_litex.h> #endif
arch/riscv/include/asm/debug_ll_litex.h new file +123
-0@@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2019 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __ASM_DEBUG_LL_LITEX__ +#define __ASM_DEBUG_LL_LITEX__ + +/** @file +* This File contains declaration for early output support +*/ + +#include <linux/kconfig.h> + +#define DEBUG_LL_UART_ADDR 0xf0001000 +#define UART_RXTX 0x00 +#define UART_TXFULL 0x04 +#define UART_RXEMPTY 0x08 +#define UART_EV_PENDING 0x10 +#define UART_EV_RX (1 << 1) + + +#ifndef __ASSEMBLY__ + +/* +* C macros +*/ + +#include <asm/io.h> + +static inline void PUTC_LL (char ch) +{ +#ifdef CONFIG_DEBUG_LL +/* wait for space */ +while (__raw_readb ((u8 *)DEBUG_LL_UART_ADDR +UART_TXFULL )) + ; + +__raw_writeb (ch, (u8 *)DEBUG_LL_UART_ADDR +UART_RXTX ); +#endif /* CONFIG_DEBUG_LL */ +} +#else /* __ASSEMBLY__ */ +/* +* Macros for use in assembly language code +*/ + +/* +* output a character in a0 +*/ +.macro debug_ll_outc_a0 +#ifdef CONFIG_DEBUG_LL + + li t0, DEBUG_LL_UART_ADDR + +201: + lbu t1, UART_TXFULL(t0) /* uart tx full ? */ + andi t1, t1, 0xff + bnez t1, 201b /* try again */ + + sb a0, UART_RXTX(t0) /* write the character */ + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character + */ +.macro debug_ll_outc chr +#ifdef CONFIG_DEBUG_LL + li a0, \chr + debug_ll_outc_a0 +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * check character in input buffer + * return value: + * v0 = 0 no character in input buffer + * v0 != 0 character in input buffer + */ +.macro debug_ll_tstc +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + /* get line status and check for data present */ + lbu s0, UART_RXEMPTY(t0) + bnez s0, 243f + li s0, 1 + j 244f +243: li s0, 0 +244: nop +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * get character to v0 + */ +.macro debug_ll_getc +#ifdef CONFIG_DEBUG_LL + +204: + debug_ll_tstc + + /* try again */ + beqz s0, 204b + + /* read a character */ + lb s0, UART_RXTX(t0) + li t1, UART_EV_RX + sb t1, UART_EV_PENDING(t0) + +#endif /* CONFIG_DEBUG_LL */ +.endm +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_DEBUG_LL_LITEX__ */ common/Kconfig +0
-0@@ -1379,6 +1379,10 @@ config DEBUG_SIFIVEbool "SiFive serial0 port"
depends onSOC_SIFIVEcommon/Kconfig +4
-0+config DEBUG_LITEX + bool "LiteX serial port" + depends on SOC_LITEX +endchoice
config
DEBUG_IMX_UART_PORTimages/Makefile.riscv +0
-0@@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashedFILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img
images/Makefile.riscv +4
-0+ +pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux +FILE_barebox-litex-linux.img = start_litex_linux.pblb +image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img
Signature · 10 lines
Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
Quoted 10 lines · On Tue, 25 May 2021 09:47:05 +0200 Jan Lübbe <[email protected]> wrote:
Quoted 6 lines · Antony Pavlov
LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU.
See https://github.com/enjoy-digital/litex and
https://github.com/litex-hub/linux-on-litex-vexriscv
for details.What are your steps for testing this? We have a few ECPIX-5 here, so we should be able to reproduce this.
I use Digilent Arty A7-35T.
Here is listex start banner:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 26 2021 11:00:44
BIOS CRC passed (3dce0a07)
Migen git sha1: 3ffd64c
LiteX git sha1: 58701cc4
--=============== SoC ==================--
CPU: VexRiscv SMP-LINUX @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 0KiB SDRAM: 262144KiB 16-bit @ 800MT/s (CL-6 CWL-5)
Here are my steps to run barebox:
1. compile barebox/images/barebox-litex-linux.img;
2. set up your tftp-server (192.168.8.100);
connect Arty board via ethernet to tftp-server;
3. copy barebox-litex-linux.img to boot.bin in your tftp-server root dir;
4. burn litex bitstream into FPGA;
Litex bios will try to boot from tftp:
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Error: Invalid image length 0xffffffff
Booting from SDCard in SD-Mode...
Booting from boot.json...
Booting from boot.bin...
SDCard boot failed.
Booting from network...
Local IP: 192.168.8.50
Remote IP: 192.168.8.100
Booting from boot.json...
Booting from boot.bin...
Copying boot.bin to 0x40000000... (515567 bytes)
Executing booted program at 0x40000000
--============= Liftoff! ===============--
Quoted 1 line
riscv-timer riscv-timer: running at 100000000 Hz
Switch to console [cs0]
barebox 2021.05.0-00097-g95181d249a-dirty #1 Tue May 25 10:16:07 MSK 2021
Board: LiteX VexRiscV-SoC-Linux
riscv-timer riscv-timer: running at 100000000 Hz
eth0: got preset MAC address: d8:89:f0:4e:00:10mdio_bus: miibus0: probed
liteeth [email protected]: liteeth driver registered m25p80 w25q128@00: n25q128a13 (16384 Kbytes)
netconsole: registered as netconsole-1
malloc space: 0x4eeffc80 -> 0x4fdffc7f (size 15 MiB)
Hit any to stop autoboot: 2
barebox@LiteX VexRiscV-SoC-Linux:/
Quoted 453 lines
Regards,
JanQuoted 442 lines
Signed-off-by Antony Pavlov <[email protected]>---
arch/riscv/Kconfig.socs | 14 +++ arch/riscv/boards/Makefile | 1 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/litex-linux.dts | 92 +++++++++++++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++++++++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 +++++++++++++++++++++++ common/Kconfig | 4 + images/Makefile.riscv | 4 + 11 files changed, 316 insertions(+)arch/riscv/Kconfig.socs +0
-0@@ -42,4 +42,18 @@ config BOARD_HIFIVEendif
arch/riscv/Kconfig.socs +14
-0+config SOC_LITEX + bool "LiteX SoCs" + depends on ARCH_RV32I + select HAS_ASM_DEBUG_LL + select HAS_NMON + select USE_COMPRESSED_DTB + select RISCV_TIMER + +config BOARD_LITEX_LINUX + bool "litex linux board" + depends on SOC_LITEX + select RISCV_M_MODE + def_bool y +endmenu
arch/riscv/boards/Makefile +0
-0@@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/
obj-$(CONFIG_BOARD_HIFIVE) += hifive/arch/riscv/boards/Makefile +1
-0+obj-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux/arch/riscv/boards/litex-linux/Makefile new file +3
-0@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.oarch/riscv/boards/litex-linux/lowlevel.c new file +22
-0@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-riscv.h> +#include <debug_ll.h> +#include <asm/riscv_nmon.h> + +ENTRY_FUNCTION(start_litex_linux, a0, a1, a2) +{ +extern char __dtb_z_litex_linux_start[]; +void *fdt; + +barebox_nmon_entry (); + +putc_ll ('>' ); + +/* On POR, we are running from read-only memory here. */ + + fdt = __dtb_z_litex_linux_start +get_runtime_offset (); + +barebox_riscv_machine_entry (0x40000000 ,SZ_256M , fdt); +}arch/riscv/dts/Makefile +0
-0@@ -7,5 +7,6 @@ obj- += dummy.opbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
hifive-unleashed-a00.dtb.o +pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.oclean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/dts/litex-linux.dts new file +92
-0@@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "litex_soc_linux.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "LiteX VexRiscV-SoC-Linux"; + compatible = "litex,vexriscv-soc-linux"; + + aliases { + rom = &rom; + sram = &sram; + }; + + /* ARTY board */ + rom: rom@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x00008000>; + read-only; + }; + + sram: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x00004000>; + }; + + main_ram: memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mac0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; + +/ { + ledsgpio: gpio@f000a800 { + compatible = "ti,74175"; + reg = <0xf000a800 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + + ld0 { + label = "arty:green:ld0"; + gpios = <&ledsgpio 0 GPIO_ACTIVE_HIGH>; + }; + + ld1 { + label = "arty:green:ld1"; + gpios = <&ledsgpio 1 GPIO_ACTIVE_HIGH>; + }; + + ld2 { + label = "arty:green:ld2"; + gpios = <&ledsgpio 2 GPIO_ACTIVE_HIGH>; + }; + + ld3 { + label = "arty:green:ld3"; + gpios = <&ledsgpio 3 GPIO_ACTIVE_HIGH>; + }; + }; + + swgpio: gpio@f0006000 { + compatible = "ti,74125"; + reg = <0xf0006000 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; +};arch/riscv/dts/litex_soc_linux.dtsi new file +49
-0@@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +/ { + compatible = "litex,vexriscv-soc-linux"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + timebase-frequency = <100000000>; // 100 MHz + + cpu@0 { + device_type = "cpu"; + compatible = "spinalhdl,vexriscv", "riscv"; + reg = <0>; + }; + }; + + uart0: serial@f0001000 { + compatible = "litex,uart"; + reg = <0xf0001000 0x18>; + status = "disabled"; + }; + + mac0: mac@f0009000 { + compatible = "litex,liteeth"; + reg = <0xf0009000 0x7c /* base */ + 0xf0009800 0x0a /* mdio_base */ + 0xb0000000 0x2000>; /* buf_base */ + tx-fifo-depth = <2>; + rx-fifo-depth = <2>; + status = "disabled"; + }; + + spi0: spi@f000b800 { + compatible = "litex,spiflash"; + + #address-cells = <1>; + #size-cells = <0>; + + reg = <0xf000b800 0x100>; + status = "disabled"; + }; +};arch/riscv/include/asm/debug_ll.h +0
-0@@ -37,6 +37,9 @@ static inline void PUTC_LL(char ch)
writel(ch, uart0);
}arch/riscv/include/asm/debug_ll.h +3
-0+#elif definedCONFIG_DEBUG_LITEX + +#include <asm/debug_ll_litex.h> #endif
arch/riscv/include/asm/debug_ll_litex.h new file +123
-0@@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2019 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __ASM_DEBUG_LL_LITEX__ +#define __ASM_DEBUG_LL_LITEX__ + +/** @file +* This File contains declaration for early output support +*/ + +#include <linux/kconfig.h> + +#define DEBUG_LL_UART_ADDR 0xf0001000 +#define UART_RXTX 0x00 +#define UART_TXFULL 0x04 +#define UART_RXEMPTY 0x08 +#define UART_EV_PENDING 0x10 +#define UART_EV_RX (1 << 1) + + +#ifndef __ASSEMBLY__ + +/* +* C macros +*/ + +#include <asm/io.h> + +static inline void PUTC_LL (char ch) +{ +#ifdef CONFIG_DEBUG_LL +/* wait for space */ +while (__raw_readb ((u8 *)DEBUG_LL_UART_ADDR +UART_TXFULL )) + ; + +__raw_writeb (ch, (u8 *)DEBUG_LL_UART_ADDR +UART_RXTX ); +#endif /* CONFIG_DEBUG_LL */ +} +#else /* __ASSEMBLY__ */ +/* +* Macros for use in assembly language code +*/ + +/* +* output a character in a0 +*/ +.macro debug_ll_outc_a0 +#ifdef CONFIG_DEBUG_LL + + li t0, DEBUG_LL_UART_ADDR + +201: + lbu t1, UART_TXFULL(t0) /* uart tx full ? */ + andi t1, t1, 0xff + bnez t1, 201b /* try again */ + + sb a0, UART_RXTX(t0) /* write the character */ + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character + */ +.macro debug_ll_outc chr +#ifdef CONFIG_DEBUG_LL + li a0, \chr + debug_ll_outc_a0 +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * check character in input buffer + * return value: + * v0 = 0 no character in input buffer + * v0 != 0 character in input buffer + */ +.macro debug_ll_tstc +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + /* get line status and check for data present */ + lbu s0, UART_RXEMPTY(t0) + bnez s0, 243f + li s0, 1 + j 244f +243: li s0, 0 +244: nop +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * get character to v0 + */ +.macro debug_ll_getc +#ifdef CONFIG_DEBUG_LL + +204: + debug_ll_tstc + + /* try again */ + beqz s0, 204b + + /* read a character */ + lb s0, UART_RXTX(t0) + li t1, UART_EV_RX + sb t1, UART_EV_PENDING(t0) + +#endif /* CONFIG_DEBUG_LL */ +.endm +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_DEBUG_LL_LITEX__ */ common/Kconfig +0
-0@@ -1379,6 +1379,10 @@ config DEBUG_SIFIVEbool "SiFive serial0 port"
depends onSOC_SIFIVEcommon/Kconfig +4
-0+config DEBUG_LITEX + bool "LiteX serial port" + depends on SOC_LITEX +endchoice
config
DEBUG_IMX_UART_PORTimages/Makefile.riscv +0
-0@@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashedFILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img
images/Makefile.riscv +4
-0+ +pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux +FILE_barebox-litex-linux.img = start_litex_linux.pblb +image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.imgSignature · 4 lines
Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 10/10 RISC-V: add litex_linux_defconfig
In reply to Antony Pavlov--- arch/riscv/configs/litex_linux_defconfig | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+)
arch/riscv/configs/litex_linux_defconfig new file +76 -0
@@ -0,0 +1,76 @@ +CONFIG_SOC_LITEX=y +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_SIZE=0xf00000 +CONFIG_MALLOC_TLSF=y +CONFIG_PANIC_HANG=y +CONFIG_BAUDRATE=1000000 +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_TIMESTAMP is not set +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_NET_LITEETH=y +CONFIG_AR8327N_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_DP83867_PHY=y +CONFIG_LXT_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_NATIONAL_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_DRIVER_SPI_LITEX_SPIFLASH=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=20000 +CONFIG_SRAM=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_GPIO_74XX_MMIO=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_PINCTRL is not set +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_DIGEST_CRC32_GENERIC=y
Signature · 7 lines
2.31.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Hello Antony,
Quoted 32 lines · Antony Pavlov
Changes since v2:
* rebase on top of master branch (
f873c7ff2497) +
"RISC-V: extend multi-image to support both S- and M-Mode"
(http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
* "litex serial: add setbrg callback" patch by Marek Czerski is addedfor review;* fix "clocksource: timer-riscv: select CSR from device tree" patch;
* change gpio IP-block base addresses in litex dts;
* gpio-74xx-mmio usesdevice_get_match_data()now.Changes since v1:
* rebased on top of next branch;
* new patches are introduced:
* clocksource: timer-riscv: select CSR from device tree
* RISC-V: makeRISCV_SBIandRISCV_M_MODEexplicitly mutually exclusive
* RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
* almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
* NOT FIXED: gpio-74xx-mmio still usesdev_get_drvdata(), notdevice_get_match_data()Antony Pavlov (9):
clocksource: timer-riscv: select CSR from device tree
RISC-V: make it possible to run nmon from PBL C code
RISC-V: boards: erizo: make it possible to use nmon
serial: add litex UART driver
gpio: add driver for 74xx-ICs with MMIO access
spi: add litex spiflash driver
net: add LiteEth driver
RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
RISC-V: addlitex_linux_defconfig
Quoted 2 lines
Marek Czerski (1):
litex serial: add setbrg callback
I'd like to give this a try eventually while following:
https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215
Do you intend to submit a new revision soon? Is it ok for you if I respin this series?
Cheers,
Ahmad
Quoted 42 lines
arch/riscv/Kconfig.socs | 14 + arch/riscv/boards/Makefile | 1 + arch/riscv/boards/erizo/lowlevel.c | 4 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++ arch/riscv/boot/Makefile | 1 + arch/riscv/boot/nmon_entry.S | 13 + arch/riscv/configs/litex_linux_defconfig | 76 +++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/erizo.dtsi | 2 + arch/riscv/dts/litex-linux.dts | 92 ++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 ++++++++ arch/riscv/include/asm/riscv_nmon.h | 49 ++- common/Kconfig | 4 + drivers/clocksource/timer-riscv.c | 24 +- drivers/gpio/Kconfig | 14 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165 ++++++++++ drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 +++++++++++++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 103 +++++++ drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++++++++++++++ images/Makefile.riscv | 4 + 29 files changed, 1370 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/boards/litex-linux/Makefile create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c create mode 100644 arch/riscv/boot/nmon_entry.S create mode 100644 arch/riscv/configs/litex_linux_defconfig create mode 100644 arch/riscv/dts/litex-linux.dts create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi create mode 100644 arch/riscv/include/asm/debug_ll_litex.h create mode 100644 drivers/gpio/gpio-74xx-mmio.c create mode 100644 drivers/net/liteeth.c create mode 100644 drivers/serial/serial_litex.c create mode 100644 drivers/spi/litex_spiflash.c
Signature · 9 lines
Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
On Wed, 11 Aug 2021 10:52:53 +0200
Ahmad Fatoum <[email protected]> wrote:
Hi Ahmad!
Quoted 35 lines
Hello Antony,
Quoted 32 lines · Antony Pavlov
Changes since v2:
* rebase on top of master branch (
f873c7ff2497) +
"RISC-V: extend multi-image to support both S- and M-Mode"
(http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
* "litex serial: add setbrg callback" patch by Marek Czerski is addedfor review;* fix "clocksource: timer-riscv: select CSR from device tree" patch;
* change gpio IP-block base addresses in litex dts;
* gpio-74xx-mmio usesdevice_get_match_data()now.Changes since v1:
* rebased on top of next branch;
* new patches are introduced:
* clocksource: timer-riscv: select CSR from device tree
* RISC-V: makeRISCV_SBIandRISCV_M_MODEexplicitly mutually exclusive
* RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
* almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
* NOT FIXED: gpio-74xx-mmio still usesdev_get_drvdata(), notdevice_get_match_data()Antony Pavlov (9):
clocksource: timer-riscv: select CSR from device tree
RISC-V: make it possible to run nmon from PBL C code
RISC-V: boards: erizo: make it possible to use nmon
serial: add litex UART driver
gpio: add driver for 74xx-ICs with MMIO access
spi: add litex spiflash driver
net: add LiteEth driver
RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
RISC-V: addlitex_linux_defconfig
Quoted 8 lines
Quoted 2 lines
Marek Czerski (1):
litex serial: add setbrg callbackI'd like to give this a try eventually while following:
https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215Do you intend to submit a new revision soon? Is it ok for you if I respin this series?
Sorry for delay with reply, I was on vacation.
I have just resend litex patchseries v4.
I have tested it with linux binaries from this repo:
https://github.com/frantony/arty-linux-on-litex-vexriscv-prebuilt
What do you want to respin in the litex patchseries?
Signature · 2 lines
Best regards, Antony Pavlov
Quoted 37 lines
Cheers,
AhmadQuoted 34 lines
arch/riscv/Kconfig.socs | 14 + arch/riscv/boards/Makefile | 1 + arch/riscv/boards/erizo/lowlevel.c | 4 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 22 ++ arch/riscv/boot/Makefile | 1 + arch/riscv/boot/nmon_entry.S | 13 + arch/riscv/configs/litex_linux_defconfig | 76 +++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/erizo.dtsi | 2 + arch/riscv/dts/litex-linux.dts | 92 ++++++ arch/riscv/dts/litex_soc_linux.dtsi | 49 +++ arch/riscv/include/asm/debug_ll.h | 3 + arch/riscv/include/asm/debug_ll_litex.h | 123 ++++++++ arch/riscv/include/asm/riscv_nmon.h | 49 ++- common/Kconfig | 4 + drivers/clocksource/timer-riscv.c | 24 +- drivers/gpio/Kconfig | 14 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165 ++++++++++ drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 +++++++++++++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 103 +++++++ drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++++++++++++++ images/Makefile.riscv | 4 + 29 files changed, 1370 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/boards/litex-linux/Makefile create mode 100644 arch/riscv/boards/litex-linux/lowlevel.c create mode 100644 arch/riscv/boot/nmon_entry.S create mode 100644 arch/riscv/configs/litex_linux_defconfig
Quoted 15 lines
Quoted 8 lines
create mode 100644 arch/riscv/dts/litex-linux.dts create mode 100644 arch/riscv/dts/litex_soc_linux.dtsi create mode 100644 arch/riscv/include/asm/debug_ll_litex.h create mode 100644 drivers/gpio/gpio-74xx-mmio.c create mode 100644 drivers/net/liteeth.c create mode 100644 drivers/serial/serial_litex.c create mode 100644 drivers/spi/litex_spiflash.cSignature · 4 lines
Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
Quoted 43 lines · Antony Pavlov
On Wed, 11 Aug 2021 10:52:53 +0200
Ahmad Fatoum <[email protected]> wrote:Hi Ahmad!
Quoted 38 lines
Hello Antony,
Quoted 34 lines · Antony Pavlov
Changes since v2:
* rebase on top of master branch (
f873c7ff2497) +
"RISC-V: extend multi-image to support both S- and M-Mode"
(http://lists.infradead.org/pipermail/barebox/2021-May/036086.html).
* "litex serial: add setbrg callback" patch by Marek Czerski is addedfor review;* fix "clocksource: timer-riscv: select CSR from device tree" patch;
* change gpio IP-block base addresses in litex dts;
* gpio-74xx-mmio usesdevice_get_match_data()now.Changes since v1:
* rebased on top of next branch;
* new patches are introduced:
* clocksource: timer-riscv: select CSR from device tree
* RISC-V: makeRISCV_SBIandRISCV_M_MODEexplicitly mutually exclusive
* RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n
* almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped);
* NOT FIXED: gpio-74xx-mmio still usesdev_get_drvdata(), notdevice_get_match_data()Antony Pavlov (9):
clocksource: timer-riscv: select CSR from device tree
RISC-V: make it possible to run nmon from PBL C code
RISC-V: boards: erizo: make it possible to use nmon
serial: add litex UART driver
gpio: add driver for 74xx-ICs with MMIO access
spi: add litex spiflash driver
net: add LiteEth driver
RISC-V: add LiteX SoC and linux-on-litex-vexriscv support
RISC-V: addlitex_linux_defconfigMarek Czerski (1):
litex serial: add setbrg callback
Quoted 7 lines
Quoted 5 lines
I'd like to give this a try eventually while following:
https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215Do you intend to submit a new revision soon? Is it ok for you if I respin this series?
Sorry for delay with reply, I was on vacation.
No worries. :)
Quoted 7 lines
I have just resend litex patchseries v4.
I have tested it with linux binaries from this repo:https://github.com/frantony/arty-linux-on-litex-vexriscv-prebuilt
What do you want to respin in the litex patchseries?
Just rebase, address feedback and give it a try.
Thanks for the respin. Building and loading linux-on-litex-vexriscv onto my FPGA worked, so I'll give your series a try as well later.
(What doesn't yet work is use as PCIe endpoint[1]. Still monkey debugging that)
[1]: https://github.com/enjoy-digital/litepcie/issues/54
Cheers,
Ahmad
Quoted 1 line
Signature · 9 lines
Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox