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x86/ACPI/State: Optimize C3 entry on AMD CPUs

PATCH Applied Deepak Sharma 4 participants 9 messages Aug 19, 2021 – Sep 24, 2021

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x86 ACPI
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Deepak Sharma

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#0 lore raw

PATCH 1/1 x86/ACPI/State: Optimize C3 entry on AMD CPUs

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>
---
 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +15 -0
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		 */
 		flags->bm_control = 0;
 	}
+	if (c->x86_vendor == X86_VENDOR_AMD) {
+		/*
+		 * For all AMD CPUs that support C3, caches should not be
+		 * flushed by software while entering C3 type state. Set
+		 * bm->check to 1 so that kernel doesn't need to execute
+		 * cache flush operation.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * In current AMD C state implementation ARB_DIS is no longer
+		 * used. So set bm_control to zero to indicate ARB_DIS is not
+		 * required while entering C3 type state.
+		 */
+		flags->bm_control = 0;
+	}
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
Signature · 1 line
2.25.1
maintainer Applied
#1 lore raw
Quoted 7 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

Quoted 33 lines
---
 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +15 -1
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                 */
                flags->bm_control = 0;
        }
+       if (c->x86_vendor == X86_VENDOR_AMD) {
+               /*
+                * For all AMD CPUs that support C3, caches should not be
+                * flushed by software while entering C3 type state. Set
+                * bm->check to 1 so that kernel doesn't need to execute
+                * cache flush operation.
+                */
+               flags->bm_check = 1;
+               /*
+                * In current AMD C state implementation ARB_DIS is no longer
+                * used. So set bm_control to zero to indicate ARB_DIS is not
+                * required while entering C3 type state.
+                */
+               flags->bm_control = 0;
+       }
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
--

2.25.1

#2 lore raw
Quoted 9 lines · Rafael J. Wysocki
Quoted 6 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me to git and branch where this has been merged.

Quoted 33 lines
Quoted 33 lines
---
  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
  1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +15 -1
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                  */
                 flags->bm_control = 0;
         }
+       if (c->x86_vendor == X86_VENDOR_AMD) {
+               /*
+                * For all AMD CPUs that support C3, caches should not be
+                * flushed by software while entering C3 type state. Set
+                * bm->check to 1 so that kernel doesn't need to execute
+                * cache flush operation.
+                */
+               flags->bm_check = 1;
+               /*
+                * In current AMD C state implementation ARB_DIS is no longer
+                * used. So set bm_control to zero to indicate ARB_DIS is not
+                * required while entering C3 type state.
+                */
+               flags->bm_control = 0;
+       }
  }
  EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
--

2.25.1

maintainer
#3 lore raw
Quoted 9 lines · Deepak Sharma
Quoted 6 lines · Rafael J. Wysocki
Quoted 5 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me to git and branch where this has been merged.

git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

Quoted 33 lines
Quoted 33 lines
Quoted 33 lines
---
  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
  1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +15 -1
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                  */
                 flags->bm_control = 0;
         }
+       if (c->x86_vendor == X86_VENDOR_AMD) {
+               /*
+                * For all AMD CPUs that support C3, caches should not be
+                * flushed by software while entering C3 type state. Set
+                * bm->check to 1 so that kernel doesn't need to execute
+                * cache flush operation.
+                */
+               flags->bm_check = 1;
+               /*
+                * In current AMD C state implementation ARB_DIS is no longer
+                * used. So set bm_control to zero to indicate ARB_DIS is not
+                * required while entering C3 type state.
+                */
+               flags->bm_control = 0;
+       }
  }
  EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
--

2.25.1

#4 lore raw

Hi Rafael,

Quoted 9 lines · Rafael J. Wysocki
Quoted 8 lines · Deepak Sharma
Quoted 6 lines · Rafael J. Wysocki
Quoted 5 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Quoted 6 lines
Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me to git and branch where this has been merged.

git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

Still I am not able to see this patch merged on linux-next branch.

Thanks,

Deepak

Quoted 33 lines
Quoted 33 lines
Quoted 33 lines
Quoted 33 lines
---
   arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
   1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +15 -1
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                   */
                  flags->bm_control = 0;
          }
+       if (c->x86_vendor == X86_VENDOR_AMD) {
+               /*
+                * For all AMD CPUs that support C3, caches should not be
+                * flushed by software while entering C3 type state. Set
+                * bm->check to 1 so that kernel doesn't need to execute
+                * cache flush operation.
+                */
+               flags->bm_check = 1;
+               /*
+                * In current AMD C state implementation ARB_DIS is no longer
+                * used. So set bm_control to zero to indicate ARB_DIS is not
+                * required while entering C3 type state.
+                */
+               flags->bm_control = 0;
+       }
   }
   EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
--

2.25.1

maintainer
#5 lore raw
Quoted 13 lines · Deepak

Hi Rafael,

Quoted 9 lines · Rafael J. Wysocki
Quoted 8 lines · Deepak Sharma
Quoted 6 lines · Rafael J. Wysocki
Quoted 5 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Quoted 8 lines
Quoted 6 lines
Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me to git and branch where this has been merged.

git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

Still I am not able to see this patch merged on linux-next branch.

It was there, but got dropped before the merge window due to the unclear next steps.

I'd rather see this resent along with the subsequent patch you were talking about.

#6 lore raw
Quoted 17 lines · Rafael J. Wysocki
Quoted 16 lines · Deepak

Hi Rafael,

Quoted 13 lines · Rafael J. Wysocki
Quoted 12 lines · Deepak Sharma
Quoted 9 lines · Rafael J. Wysocki
Quoted 6 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>

Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me to git and branch where this has been merged.

Quoted 7 lines
Quoted 2 lines
Quoted 1 line

git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next

Still I am not able to see this patch merged on linux-next branch.

It was there, but got dropped before the merge window due to the unclear next steps.

I'd rather see this resent along with the subsequent patch you were talking about.

Thanks for the clarification. I will resend patch with subsequent changes which will have support for zen onward CPU's.

#7 lore raw
In reply to Deepak Sharma
Quoted 18 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>
---
 arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +0 -0
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 		 */
 		flags->bm_control = 0;
 	}

arch/x86/kernel/acpi/cstate.c void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, · line 91

Quoted 10 lines
arch/x86/kernel/acpi/cstate.c +10 -0
+	if (c->x86_vendor == X86_VENDOR_AMD) {
+		/*
+		 * For all AMD CPUs that support C3, caches should not be
+		 * flushed by software while entering C3 type state. Set
+		 * bm->check to 1 so that kernel doesn't need to execute
+		 * cache flush operation.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * In current AMD C state implementation ARB_DIS is no longer

Fine for current implementations, but what about older implementations?

Thanks,

tglx

#8 lore raw
Quoted 23 lines · Thomas Gleixner
Quoted 21 lines · Deepak Sharma

AMD CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause performance drop for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly.

Signed-off-by Deepak Sharma <[email protected]>
---
  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
  1 file changed, 15 insertions(+)
arch/x86/kernel/acpi/cstate.c +3 -0
index 7de599eba7f0..62a5986d625a 100644
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
  		 */
  		flags->bm_control = 0;
  	}
+	if (c->x86_vendor == X86_VENDOR_AMD) {
+		/*
+		 * For all AMD CPUs that support C3, caches should not be
Quoted 8 lines

arch/x86/kernel/acpi/cstate.c void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, · line 91

Quoted 7 lines
arch/x86/kernel/acpi/cstate.c +7 -0
+		 * flushed by software while entering C3 type state. Set
+		 * bm->check to 1 so that kernel doesn't need to execute
+		 * cache flush operation.
+		 */
+		flags->bm_check = 1;
+		/*
+		 * In current AMD C state implementation ARB_DIS is no longer

Fine for current implementations, but what about older implementations?

We are internally discussing about its validity on much older implementations. Will send subsequent patch based on the conclusion.

Thanks,

Deepak