drm/nouveau/ga102-: support ttm buffer moves via copy engine
Subsystems (4)
PATCH v2 1/1 drm/nouveau/ga102-: support ttm buffer moves via copy engine
From: Ben Skeggs <[email protected]>
We don't currently have any kind of real acceleration on Ampere GPUs, but the TTM memcpy() fallback paths aren't really designed to handle copies between different devices, such as on Optimus systems, and result in a kernel OOPS.
A few options were investigated to try and fix this, but didn't work out, and likely would have resulted in a very unpleasant experience for users anyway.
This commit adds just enough support for setting up a single channel connected to a copy engine, which the kernel can use to accelerate the buffer copies between devices. Userspace has no access to this incomplete channel support, but it's suitable for TTM's needs.
A more complete implementation of host(fifo) for Ampere GPUs is in the works, but the required changes are far too invasive that they would be unsuitable to backport to fix this issue on current kernels.
v2: fix GPFIFO length in RAMFC (reported by Karol)
Signed-off-by Ben Skeggs <[email protected]>
Cc Lyude Paul <[email protected]>
Cc Karol Herbst <[email protected]>
Cc <[email protected]> # v5.12+
Reviewed-by Karol Herbst <[email protected]>
Signed-off-by Karol Herbst <[email protected]>
--- drivers/gpu/drm/nouveau/include/nvif/class.h | 2 + .../drm/nouveau/include/nvkm/engine/fifo.h | 1 + drivers/gpu/drm/nouveau/nouveau_bo.c | 1 + drivers/gpu/drm/nouveau/nouveau_chan.c | 6 +- drivers/gpu/drm/nouveau/nouveau_drm.c | 4 + drivers/gpu/drm/nouveau/nv84_fence.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/device/base.c | 3 + .../gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/ga102.c | 308 ++++++++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/top/ga100.c | 7 +- 10 files changed, 329 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c
drivers/gpu/drm/nouveau/include/nvif/class.h +2 -0
@@ -71,6 +71,7 @@#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f#define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f#define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f +#define AMPERE_CHANNEL_GPFIFO_B /* clc36f.h */ 0x0000c76f#define NV50_DISP /* cl5070.h */ 0x00005070#define G82_DISP /* cl5070.h */ 0x00008270
@@ -200,6 +201,7 @@#define PASCAL_DMA_COPY_B 0x0000c1b5#define VOLTA_DMA_COPY_A 0x0000c3b5#define TURING_DMA_COPY_A 0x0000c5b5 +#define AMPERE_DMA_COPY_B 0x0000c7b5#define FERMI_DECOMPRESS 0x000090b8
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +1 -0
@@ -77,4 +77,5 @@ int gp100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, structint gp10b_fifo_new (struct nvkm_device *,enum nvkm_subdev_type ,int inst,struct nvkm_fifo **);int gv100_fifo_new (struct nvkm_device *,enum nvkm_subdev_type ,int inst,struct nvkm_fifo **);int tu102_fifo_new (struct nvkm_device *,enum nvkm_subdev_type ,int inst,struct nvkm_fifo **); +int ga102_fifo_new (struct nvkm_device *,enum nvkm_subdev_type ,int inst,struct nvkm_fifo **);#endif
drivers/gpu/drm/nouveau/nouveau_bo.c +1 -0
@@ -844,6 +844,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm) struct ttm_resource *, struct ttm_resource *);int (*init)(struct nouveau_channel *,u32 handle); } _methods[] = { + { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init }, { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
drivers/gpu/drm/nouveau/nouveau_chan.c +4 -2
@@ -250,7 +250,8 @@ static int nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, u64 runlist, bool priv, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { TURING_CHANNEL_GPFIFO_A, + static const u16 oclasses[] = { AMPERE_CHANNEL_GPFIFO_B, + TURING_CHANNEL_GPFIFO_A, VOLTA_CHANNEL_GPFIFO_A, PASCAL_CHANNEL_GPFIFO_A, MAXWELL_CHANNEL_GPFIFO_A,
@@ -386,7 +387,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)nvif_object_map (&chan->user,NULL ,0 ); -if (chan->user.oclass >=FERMI_CHANNEL_GPFIFO ) { +if (chan->user.oclass >=FERMI_CHANNEL_GPFIFO && + chan->user.oclass <AMPERE_CHANNEL_GPFIFO_B ) { ret = nvif_notify_ctor(&chan->user, "abi16ChanKilled", nouveau_channel_killed, true, NV906F_V0_NTFY_KILLED,
drivers/gpu/drm/nouveau/nouveau_drm.c +4 -0
@@ -345,6 +345,9 @@ nouveau_accel_gr_init(struct nouveau_drm *drm)u32 arg0, arg1;int ret; +if (device->info.family >=NV_DEVICE_INFO_V0_AMPERE ) +return ; +/* Allocate channel that has access to the graphics engine. */ if (device->info.family >=NV_DEVICE_INFO_V0_KEPLER ) { arg0 =nvif_fifo_runlist (device,NV_DEVICE_HOST_RUNLIST_ENGINES_GR );
@@ -469,6 +472,7 @@ nouveau_accel_init(struct nouveau_drm *drm)case PASCAL_CHANNEL_GPFIFO_A :case VOLTA_CHANNEL_GPFIFO_A :case TURING_CHANNEL_GPFIFO_A : +case AMPERE_CHANNEL_GPFIFO_B : ret =nvc0_fence_create (drm);break ;default :
drivers/gpu/drm/nouveau/nv84_fence.c +1 -1
@@ -204,7 +204,7 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_new = nv84_fence_context_new; priv->base.context_del = nv84_fence_context_del; - priv->base.uevent = true; + priv->base.uevent = drm->client.device.info.family <NV_DEVICE_INFO_V0_AMPERE ;mutex_init (&priv->mutex);
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +3 -0
@@ -2602,6 +2602,7 @@ nv172_chipset = { .top = { 0x00000001, ga100_top_new }, .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, }; static const struct nvkm_device_chip
@@ -2622,6 +2623,7 @@ nv174_chipset = { .top = { 0x00000001, ga100_top_new }, .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, }; static const struct nvkm_device_chip
@@ -2642,6 +2644,7 @@ nv177_chipset = { .top = { 0x00000001, ga100_top_new }, .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, + .fifo = { 0x00000001, ga102_fifo_new }, }; static int
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +1 -0
@@ -18,6 +18,7 @@ nvkm-y += nvkm/engine/fifo/gp100.o nvkm-y += nvkm/engine/fifo/gp10b.o nvkm-y += nvkm/engine/fifo/gv100.o nvkm-y += nvkm/engine/fifo/tu102.o +nvkm-y += nvkm/engine/fifo/ga102.o nvkm-y += nvkm/engine/fifo/chan.o nvkm-y += nvkm/engine/fifo/channv50.o
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c new file +308 -0
308 lines not on this page · raw message
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c +4 -3
@@ -54,7 +54,7 @@ ga100_top_oneinit(struct nvkm_top *top) info->reset = (data &0x0000001f );break ;case 2 : - info->runlist = (data &0x0000fc00 ) >>10 ; + info->runlist = (data &0x00fffc00 ); info->engine = (data &0x00000003 );break ;default :
@@ -85,9 +85,10 @@ ga100_top_oneinit(struct nvkm_top *top) }nvkm_debug (subdev,"%02x.%d (%8s): addr %06x fault %2d " -"runlist %2d engine %2d reset %2d\n" , type, inst, +"runlist %6x engine %2d reset %2d\n" , type, inst, info->type ==NVKM_SUBDEV_NR ?"????????" : nvkm_subdev_type[info->type], - info->addr, info->fault, info->runlist, info->engine, info->reset); + info->addr, info->fault, info->runlist <0 ?0 : info->runlist, + info->engine, info->reset); info =NULL ; }
Signature · 1 line
2.31.1