ARM: dts: ixp4xx: Group PCI interrupt properties together

PATCH In review Rob Herring 2 participants 2 messages Sep 28, 2021 – Oct 20, 2021 Device tree bindings

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Rob Herring

author maintainer

2021-09-28 19:21 UTC #0 lore raw

PATCH 1/1 ARM: dts: ixp4xx: Group PCI interrupt properties together

Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties alongside the 'interrupt-map' property in each board dts. This avoids having incomplete set of interrupt properties which may fail validation.

Cc Linus Walleij <[email protected]>

Signed-off-by Rob Herring <[email protected]>

---
 arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts        | 2 ++
 arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts      | 2 ++
 arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts    | 2 ++
 arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts     | 2 ++
 arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts  | 2 ++
 arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts    | 2 ++
 arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts          | 2 ++
 arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts     | 2 ++
 arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts    | 2 ++
 arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts   | 2 ++
 arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts  | 2 ++
 arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi | 2 ++
 arch/arm/boot/dts/intel-ixp4xx.dtsi                  | 2 --
 13 files changed, 24 insertions(+), 2 deletions(-)

arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts +2 -0

index 44c017b78008..bd4230d7dac9 100644
@@ -63,6 +63,8 @@ pci@c0000000 {
 			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
 			 * each handling all IRQs.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */

arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts +2 -0

index 7200126cb3b5..92b987bc3f99 100644
@@ -120,6 +120,8 @@ pci@c0000000 {
 			 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
 			 * per slot. This interrupt is shared (OR:ed) by all four pins.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */

arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts +2 -0

index 8b32e9f22d81..5ab09fb10dae 100644
@@ -129,6 +129,8 @@ pci@c0000000 {
 			 * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
 			 * Only slot 3 have three IRQs.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */

arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +2 -0

index 77e78c6dc2cd..598586fc0862 100644
@@ -106,6 +106,8 @@ pci@c0000000 {
 			 * Written based on the FSG-3 PCI boardfile.
 			 * We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 12 */
 			<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */

arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts +2 -0

index a20277ff0420..a5943f51e8c2 100644
@@ -115,6 +115,8 @@ pci@c0000000 {
 			 *
 			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts +2 -0

index 8c18d802c849..cbc87b344f6a 100644
@@ -115,6 +115,8 @@ pci@c0000000 {
 			 * Taken from NAS 100D PCI boardfile (nas100d-pci.c)
 			 * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts +2 -0

index 002a8705abc9..f17cab12a64b 100644
@@ -68,6 +68,8 @@ pci@c0000000 {
 			 * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
 			 * for 12 & 13 and one for 14.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 12 */
 			<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */

arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +2 -0

index e3a32b08d167..0edc5928e00b 100644
@@ -122,6 +122,8 @@ pci@c0000000 {
 			 * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
 			 * We have slots (IDSEL) 1, 2 and 3.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts +2 -0

index 6b28dda747fd..5e7e31b74b04 100644
@@ -123,6 +123,8 @@ pci@c0000000 {
 			 * We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
 			 * Derived from the GTWX5715 PCI boardfile.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 0 */
 			<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */

arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts +2 -0

index 04a0f7138967..a57009436ed8 100644
@@ -62,6 +62,8 @@ pci@c0000000 {
 			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
 			 * each handling all IRQs.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */

arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +2 -0

index 84e6aec8e665..cf4010d60187 100644
@@ -131,6 +131,8 @@ pci@c0000000 {
 			 * have instead assumed that they are rotated (swizzled) like
 			 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi +2 -0

index c1d9c49982b3..146352ba848b 100644
@@ -106,6 +106,8 @@ pci@c0000000 {
 			 * PCI slots on the BIXMB425BD base card.
 			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
 			 */
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map =
 			/* IDSEL 1 */
 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */

arch/arm/boot/dts/intel-ixp4xx.dtsi +0 -2

index e5af2d463074..46fede021476 100644
@@ -78,8 +78,6 @@ pci@c0000000 {
 			dma-ranges =
 			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
 
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0xf800 0 0 7>;
 			/* Each unique DTS using PCI must specify the swizzling */
 		};

Signature · 1 line

2.30.2

Linus Walleij

2021-10-20 00:32 UTC #1 lore raw

Quoted 6 lines · Rob Herring

Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties alongside the 'interrupt-map' property in each board dts. This avoids having incomplete set of interrupt properties which may fail validation.
Cc Linus Walleij <[email protected]>
Signed-off-by Rob Herring <[email protected]>

Patch applied. Sorry for the delay.

Yours,
Linus Walleij