fixes and enhancements to Truflow

index 0da6070d7d..ce878d8e02 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon May 17 15:30:41 2021 */
+/* date: Wed Aug 25 14:37:06 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_04bc] = 30,
 	[BNXT_ULP_ACT_HID_00a9] = 31,
 	[BNXT_ULP_ACT_HID_020f] = 32,
-	[BNXT_ULP_ACT_HID_04a9] = 33,
-	[BNXT_ULP_ACT_HID_01fc] = 34,
-	[BNXT_ULP_ACT_HID_04be] = 35,
-	[BNXT_ULP_ACT_HID_00ab] = 36,
-	[BNXT_ULP_ACT_HID_0211] = 37,
-	[BNXT_ULP_ACT_HID_04ab] = 38,
-	[BNXT_ULP_ACT_HID_01fe] = 39,
-	[BNXT_ULP_ACT_HID_0667] = 40,
-	[BNXT_ULP_ACT_HID_0254] = 41,
-	[BNXT_ULP_ACT_HID_03ba] = 42,
-	[BNXT_ULP_ACT_HID_0654] = 43,
-	[BNXT_ULP_ACT_HID_03a7] = 44,
-	[BNXT_ULP_ACT_HID_0669] = 45,
-	[BNXT_ULP_ACT_HID_0256] = 46,
-	[BNXT_ULP_ACT_HID_03bc] = 47,
-	[BNXT_ULP_ACT_HID_0656] = 48,
-	[BNXT_ULP_ACT_HID_03a9] = 49,
-	[BNXT_ULP_ACT_HID_021b] = 50,
-	[BNXT_ULP_ACT_HID_021c] = 51,
-	[BNXT_ULP_ACT_HID_021e] = 52,
-	[BNXT_ULP_ACT_HID_063f] = 53,
-	[BNXT_ULP_ACT_HID_0510] = 54,
-	[BNXT_ULP_ACT_HID_03c6] = 55,
-	[BNXT_ULP_ACT_HID_0082] = 56,
-	[BNXT_ULP_ACT_HID_06bb] = 57,
-	[BNXT_ULP_ACT_HID_021d] = 58,
-	[BNXT_ULP_ACT_HID_0641] = 59,
-	[BNXT_ULP_ACT_HID_0512] = 60,
-	[BNXT_ULP_ACT_HID_03c8] = 61,
-	[BNXT_ULP_ACT_HID_0084] = 62,
-	[BNXT_ULP_ACT_HID_06bd] = 63,
-	[BNXT_ULP_ACT_HID_06d7] = 64,
-	[BNXT_ULP_ACT_HID_02c4] = 65,
-	[BNXT_ULP_ACT_HID_042a] = 66,
-	[BNXT_ULP_ACT_HID_06c4] = 67,
-	[BNXT_ULP_ACT_HID_0417] = 68,
-	[BNXT_ULP_ACT_HID_06d9] = 69,
-	[BNXT_ULP_ACT_HID_02c6] = 70,
-	[BNXT_ULP_ACT_HID_042c] = 71,
-	[BNXT_ULP_ACT_HID_06c6] = 72,
-	[BNXT_ULP_ACT_HID_0419] = 73,
-	[BNXT_ULP_ACT_HID_0119] = 74,
-	[BNXT_ULP_ACT_HID_046f] = 75,
-	[BNXT_ULP_ACT_HID_05d5] = 76,
-	[BNXT_ULP_ACT_HID_0106] = 77,
-	[BNXT_ULP_ACT_HID_05c2] = 78,
-	[BNXT_ULP_ACT_HID_011b] = 79,
-	[BNXT_ULP_ACT_HID_0471] = 80,
-	[BNXT_ULP_ACT_HID_05d7] = 81,
-	[BNXT_ULP_ACT_HID_0108] = 82,
-	[BNXT_ULP_ACT_HID_05c4] = 83,
-	[BNXT_ULP_ACT_HID_00a2] = 84,
-	[BNXT_ULP_ACT_HID_00a4] = 85
+	[BNXT_ULP_ACT_HID_0153] = 33,
+	[BNXT_ULP_ACT_HID_04a9] = 34,
+	[BNXT_ULP_ACT_HID_01fc] = 35,
+	[BNXT_ULP_ACT_HID_04be] = 36,
+	[BNXT_ULP_ACT_HID_00ab] = 37,
+	[BNXT_ULP_ACT_HID_0211] = 38,
+	[BNXT_ULP_ACT_HID_0155] = 39,
+	[BNXT_ULP_ACT_HID_04ab] = 40,
+	[BNXT_ULP_ACT_HID_01fe] = 41,
+	[BNXT_ULP_ACT_HID_0667] = 42,
+	[BNXT_ULP_ACT_HID_0254] = 43,
+	[BNXT_ULP_ACT_HID_03ba] = 44,
+	[BNXT_ULP_ACT_HID_02fe] = 45,
+	[BNXT_ULP_ACT_HID_0654] = 46,
+	[BNXT_ULP_ACT_HID_03a7] = 47,
+	[BNXT_ULP_ACT_HID_0669] = 48,
+	[BNXT_ULP_ACT_HID_0256] = 49,
+	[BNXT_ULP_ACT_HID_03bc] = 50,
+	[BNXT_ULP_ACT_HID_0300] = 51,
+	[BNXT_ULP_ACT_HID_0656] = 52,
+	[BNXT_ULP_ACT_HID_03a9] = 53,
+	[BNXT_ULP_ACT_HID_021b] = 54,
+	[BNXT_ULP_ACT_HID_021c] = 55,
+	[BNXT_ULP_ACT_HID_021e] = 56,
+	[BNXT_ULP_ACT_HID_063f] = 57,
+	[BNXT_ULP_ACT_HID_0510] = 58,
+	[BNXT_ULP_ACT_HID_03c6] = 59,
+	[BNXT_ULP_ACT_HID_0082] = 60,
+	[BNXT_ULP_ACT_HID_06bb] = 61,
+	[BNXT_ULP_ACT_HID_021d] = 62,
+	[BNXT_ULP_ACT_HID_0641] = 63,
+	[BNXT_ULP_ACT_HID_0512] = 64,
+	[BNXT_ULP_ACT_HID_03c8] = 65,
+	[BNXT_ULP_ACT_HID_0084] = 66,
+	[BNXT_ULP_ACT_HID_06bd] = 67,
+	[BNXT_ULP_ACT_HID_06d7] = 68,
+	[BNXT_ULP_ACT_HID_02c4] = 69,
+	[BNXT_ULP_ACT_HID_042a] = 70,
+	[BNXT_ULP_ACT_HID_036e] = 71,
+	[BNXT_ULP_ACT_HID_06c4] = 72,
+	[BNXT_ULP_ACT_HID_0417] = 73,
+	[BNXT_ULP_ACT_HID_06d9] = 74,
+	[BNXT_ULP_ACT_HID_02c6] = 75,
+	[BNXT_ULP_ACT_HID_042c] = 76,
+	[BNXT_ULP_ACT_HID_0370] = 77,
+	[BNXT_ULP_ACT_HID_06c6] = 78,
+	[BNXT_ULP_ACT_HID_0419] = 79,
+	[BNXT_ULP_ACT_HID_0119] = 80,
+	[BNXT_ULP_ACT_HID_046f] = 81,
+	[BNXT_ULP_ACT_HID_05d5] = 82,
+	[BNXT_ULP_ACT_HID_0519] = 83,
+	[BNXT_ULP_ACT_HID_0106] = 84,
+	[BNXT_ULP_ACT_HID_05c2] = 85,
+	[BNXT_ULP_ACT_HID_011b] = 86,
+	[BNXT_ULP_ACT_HID_0471] = 87,
+	[BNXT_ULP_ACT_HID_05d7] = 88,
+	[BNXT_ULP_ACT_HID_051b] = 89,
+	[BNXT_ULP_ACT_HID_0108] = 90,
+	[BNXT_ULP_ACT_HID_05c4] = 91,
+	[BNXT_ULP_ACT_HID_00a2] = 92,
+	[BNXT_ULP_ACT_HID_00a4] = 93
 };
 
 /* Array for the act matcher list */

@@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 3
 	},
 	[33] = {
-	.act_hid = BNXT_ULP_ACT_HID_04a9,
+	.act_hid = BNXT_ULP_ACT_HID_0153,
 	.act_pattern_id = 3,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[34] = {
-	.act_hid = BNXT_ULP_ACT_HID_01fc,
+	.act_hid = BNXT_ULP_ACT_HID_04a9,
 	.act_pattern_id = 4,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |

@@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 3
 	},
 	[35] = {
-	.act_hid = BNXT_ULP_ACT_HID_04be,
+	.act_hid = BNXT_ULP_ACT_HID_01fc,
 	.act_pattern_id = 5,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[36] = {
-	.act_hid = BNXT_ULP_ACT_HID_00ab,
+	.act_hid = BNXT_ULP_ACT_HID_04be,
 	.act_pattern_id = 6,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[37] = {
-	.act_hid = BNXT_ULP_ACT_HID_0211,
+	.act_hid = BNXT_ULP_ACT_HID_00ab,
 	.act_pattern_id = 7,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[38] = {
-	.act_hid = BNXT_ULP_ACT_HID_04ab,
+	.act_hid = BNXT_ULP_ACT_HID_0211,
 	.act_pattern_id = 8,
 	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[39] = {
+	.act_hid = BNXT_ULP_ACT_HID_0155,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[40] = {
+	.act_hid = BNXT_ULP_ACT_HID_04ab,
+	.act_pattern_id = 10,
+	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |

@@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[39] = {
+	[41] = {
 	.act_hid = BNXT_ULP_ACT_HID_01fe,
-	.act_pattern_id = 9,
+	.act_pattern_id = 11,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[40] = {
+	[42] = {
 	.act_hid = BNXT_ULP_ACT_HID_0667,
-	.act_pattern_id = 10,
+	.act_pattern_id = 12,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[41] = {
+	[43] = {
 	.act_hid = BNXT_ULP_ACT_HID_0254,
-	.act_pattern_id = 11,
+	.act_pattern_id = 13,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[42] = {
+	[44] = {
 	.act_hid = BNXT_ULP_ACT_HID_03ba,
-	.act_pattern_id = 12,
+	.act_pattern_id = 14,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[43] = {
+	[45] = {
+	.act_hid = BNXT_ULP_ACT_HID_02fe,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[46] = {
 	.act_hid = BNXT_ULP_ACT_HID_0654,
-	.act_pattern_id = 13,
+	.act_pattern_id = 16,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[44] = {
+	[47] = {
 	.act_hid = BNXT_ULP_ACT_HID_03a7,
-	.act_pattern_id = 14,
+	.act_pattern_id = 17,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[45] = {
+	[48] = {
 	.act_hid = BNXT_ULP_ACT_HID_0669,
-	.act_pattern_id = 15,
+	.act_pattern_id = 18,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[46] = {
+	[49] = {
 	.act_hid = BNXT_ULP_ACT_HID_0256,
-	.act_pattern_id = 16,
+	.act_pattern_id = 19,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[47] = {
+	[50] = {
 	.act_hid = BNXT_ULP_ACT_HID_03bc,
-	.act_pattern_id = 17,
+	.act_pattern_id = 20,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[48] = {
+	[51] = {
+	.act_hid = BNXT_ULP_ACT_HID_0300,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[52] = {
 	.act_hid = BNXT_ULP_ACT_HID_0656,
-	.act_pattern_id = 18,
+	.act_pattern_id = 22,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[49] = {
+	[53] = {
 	.act_hid = BNXT_ULP_ACT_HID_03a9,
-	.act_pattern_id = 19,
+	.act_pattern_id = 23,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[50] = {
+	[54] = {
 	.act_hid = BNXT_ULP_ACT_HID_021b,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[51] = {
+	[55] = {
 	.act_hid = BNXT_ULP_ACT_HID_021c,
 	.act_pattern_id = 1,
 	.app_sig = 0,

@@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[52] = {
+	[56] = {
 	.act_hid = BNXT_ULP_ACT_HID_021e,
 	.act_pattern_id = 2,
 	.app_sig = 0,

@@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[53] = {
+	[57] = {
 	.act_hid = BNXT_ULP_ACT_HID_063f,
 	.act_pattern_id = 3,
 	.app_sig = 0,

@@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[54] = {
+	[58] = {
 	.act_hid = BNXT_ULP_ACT_HID_0510,
 	.act_pattern_id = 4,
 	.app_sig = 0,

@@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[55] = {
+	[59] = {
 	.act_hid = BNXT_ULP_ACT_HID_03c6,
 	.act_pattern_id = 5,
 	.app_sig = 0,

@@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[56] = {
+	[60] = {
 	.act_hid = BNXT_ULP_ACT_HID_0082,
 	.act_pattern_id = 6,
 	.app_sig = 0,

@@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[57] = {
+	[61] = {
 	.act_hid = BNXT_ULP_ACT_HID_06bb,
 	.act_pattern_id = 7,
 	.app_sig = 0,

@@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[58] = {
+	[62] = {
 	.act_hid = BNXT_ULP_ACT_HID_021d,
 	.act_pattern_id = 8,
 	.app_sig = 0,

@@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[59] = {
+	[63] = {
 	.act_hid = BNXT_ULP_ACT_HID_0641,
 	.act_pattern_id = 9,
 	.app_sig = 0,

@@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[60] = {
+	[64] = {
 	.act_hid = BNXT_ULP_ACT_HID_0512,
 	.act_pattern_id = 10,
 	.app_sig = 0,

@@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[61] = {
+	[65] = {
 	.act_hid = BNXT_ULP_ACT_HID_03c8,
 	.act_pattern_id = 11,
 	.app_sig = 0,

@@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[62] = {
+	[66] = {
 	.act_hid = BNXT_ULP_ACT_HID_0084,
 	.act_pattern_id = 12,
 	.app_sig = 0,

@@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[63] = {
+	[67] = {
 	.act_hid = BNXT_ULP_ACT_HID_06bd,
 	.act_pattern_id = 13,
 	.app_sig = 0,

@@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[64] = {
+	[68] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d7,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[65] = {
+	[69] = {
 	.act_hid = BNXT_ULP_ACT_HID_02c4,
 	.act_pattern_id = 1,
 	.app_sig = 0,

@@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[66] = {
+	[70] = {
 	.act_hid = BNXT_ULP_ACT_HID_042a,
 	.act_pattern_id = 2,
 	.app_sig = 0,

@@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[67] = {
-	.act_hid = BNXT_ULP_ACT_HID_06c4,
+	[71] = {
+	.act_hid = BNXT_ULP_ACT_HID_036e,
 	.act_pattern_id = 3,
 	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[72] = {
+	.act_hid = BNXT_ULP_ACT_HID_06c4,
+	.act_pattern_id = 4,
+	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |

@@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[68] = {
+	[73] = {
 	.act_hid = BNXT_ULP_ACT_HID_0417,
-	.act_pattern_id = 4,
+	.act_pattern_id = 5,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |

@@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[69] = {
+	[74] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d9,
-	.act_pattern_id = 5,
+	.act_pattern_id = 6,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[70] = {
+	[75] = {
 	.act_hid = BNXT_ULP_ACT_HID_02c6,
-	.act_pattern_id = 6,
+	.act_pattern_id = 7,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[71] = {
+	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_042c,
-	.act_pattern_id = 7,
+	.act_pattern_id = 8,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[72] = {
+	[77] = {
+	.act_hid = BNXT_ULP_ACT_HID_0370,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[78] = {
 	.act_hid = BNXT_ULP_ACT_HID_06c6,
-	.act_pattern_id = 8,
+	.act_pattern_id = 10,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[73] = {
+	[79] = {
 	.act_hid = BNXT_ULP_ACT_HID_0419,
-	.act_pattern_id = 9,
+	.act_pattern_id = 11,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[74] = {
+	[80] = {
 	.act_hid = BNXT_ULP_ACT_HID_0119,
-	.act_pattern_id = 10,
+	.act_pattern_id = 12,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[75] = {
+	[81] = {
 	.act_hid = BNXT_ULP_ACT_HID_046f,
-	.act_pattern_id = 11,
+	.act_pattern_id = 13,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[76] = {
+	[82] = {
 	.act_hid = BNXT_ULP_ACT_HID_05d5,
-	.act_pattern_id = 12,
+	.act_pattern_id = 14,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[77] = {
+	[83] = {
+	.act_hid = BNXT_ULP_ACT_HID_0519,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[84] = {
 	.act_hid = BNXT_ULP_ACT_HID_0106,
-	.act_pattern_id = 13,
+	.act_pattern_id = 16,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[78] = {
+	[85] = {
 	.act_hid = BNXT_ULP_ACT_HID_05c2,
-	.act_pattern_id = 14,
+	.act_pattern_id = 17,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[79] = {
+	[86] = {
 	.act_hid = BNXT_ULP_ACT_HID_011b,
-	.act_pattern_id = 15,
+	.act_pattern_id = 18,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[80] = {
+	[87] = {
 	.act_hid = BNXT_ULP_ACT_HID_0471,
-	.act_pattern_id = 16,
+	.act_pattern_id = 19,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[81] = {
+	[88] = {
 	.act_hid = BNXT_ULP_ACT_HID_05d7,
-	.act_pattern_id = 17,
+	.act_pattern_id = 20,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[82] = {
+	[89] = {
+	.act_hid = BNXT_ULP_ACT_HID_051b,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[90] = {
 	.act_hid = BNXT_ULP_ACT_HID_0108,
-	.act_pattern_id = 18,
+	.act_pattern_id = 22,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[83] = {
+	[91] = {
 	.act_hid = BNXT_ULP_ACT_HID_05c4,
-	.act_pattern_id = 19,
+	.act_pattern_id = 23,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[84] = {
+	[92] = {
 	.act_hid = BNXT_ULP_ACT_HID_00a2,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[85] = {
+	[93] = {
 	.act_hid = BNXT_ULP_ACT_HID_00a4,
 	.act_pattern_id = 1,
 	.app_sig = 0,

index c016e1940a..fcd460e707 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Aug 20 17:59:14 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_

@@ -20,7 +20,7 @@
 #define BNXT_ULP_CLASS_HID_SHFTL 28
 #define BNXT_ULP_CLASS_HID_MASK 65535
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
 #define BNXT_ULP_ACT_HID_SHFTR 27

@@ -29,7 +29,7 @@
 #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277
 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
 #define BNXT_ULP_COND_GOTO_REJECT 1023
 #define BNXT_ULP_COND_GOTO_RF 0x10000

@@ -50,11 +50,11 @@
 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
 #define ULP_THOR_CLASS_COND_LIST_SIZE 55
 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7
 #define ULP_THOR_ACT_TBL_LIST_SIZE 36
 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16

@@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_04bc = 0x04bc,
 	BNXT_ULP_ACT_HID_00a9 = 0x00a9,
 	BNXT_ULP_ACT_HID_020f = 0x020f,
+	BNXT_ULP_ACT_HID_0153 = 0x0153,
 	BNXT_ULP_ACT_HID_04a9 = 0x04a9,
 	BNXT_ULP_ACT_HID_01fc = 0x01fc,
 	BNXT_ULP_ACT_HID_04be = 0x04be,
 	BNXT_ULP_ACT_HID_00ab = 0x00ab,
 	BNXT_ULP_ACT_HID_0211 = 0x0211,
+	BNXT_ULP_ACT_HID_0155 = 0x0155,
 	BNXT_ULP_ACT_HID_04ab = 0x04ab,
 	BNXT_ULP_ACT_HID_01fe = 0x01fe,
 	BNXT_ULP_ACT_HID_0667 = 0x0667,
 	BNXT_ULP_ACT_HID_0254 = 0x0254,
 	BNXT_ULP_ACT_HID_03ba = 0x03ba,
+	BNXT_ULP_ACT_HID_02fe = 0x02fe,
 	BNXT_ULP_ACT_HID_0654 = 0x0654,
 	BNXT_ULP_ACT_HID_03a7 = 0x03a7,
 	BNXT_ULP_ACT_HID_0669 = 0x0669,
 	BNXT_ULP_ACT_HID_0256 = 0x0256,
 	BNXT_ULP_ACT_HID_03bc = 0x03bc,
+	BNXT_ULP_ACT_HID_0300 = 0x0300,
 	BNXT_ULP_ACT_HID_0656 = 0x0656,
 	BNXT_ULP_ACT_HID_03a9 = 0x03a9,
 	BNXT_ULP_ACT_HID_021b = 0x021b,

@@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_06d7 = 0x06d7,
 	BNXT_ULP_ACT_HID_02c4 = 0x02c4,
 	BNXT_ULP_ACT_HID_042a = 0x042a,
+	BNXT_ULP_ACT_HID_036e = 0x036e,
 	BNXT_ULP_ACT_HID_06c4 = 0x06c4,
 	BNXT_ULP_ACT_HID_0417 = 0x0417,
 	BNXT_ULP_ACT_HID_06d9 = 0x06d9,
 	BNXT_ULP_ACT_HID_02c6 = 0x02c6,
 	BNXT_ULP_ACT_HID_042c = 0x042c,
+	BNXT_ULP_ACT_HID_0370 = 0x0370,
 	BNXT_ULP_ACT_HID_06c6 = 0x06c6,
 	BNXT_ULP_ACT_HID_0419 = 0x0419,
 	BNXT_ULP_ACT_HID_0119 = 0x0119,
 	BNXT_ULP_ACT_HID_046f = 0x046f,
 	BNXT_ULP_ACT_HID_05d5 = 0x05d5,
+	BNXT_ULP_ACT_HID_0519 = 0x0519,
 	BNXT_ULP_ACT_HID_0106 = 0x0106,
 	BNXT_ULP_ACT_HID_05c2 = 0x05c2,
 	BNXT_ULP_ACT_HID_011b = 0x011b,
 	BNXT_ULP_ACT_HID_0471 = 0x0471,
 	BNXT_ULP_ACT_HID_05d7 = 0x05d7,
+	BNXT_ULP_ACT_HID_051b = 0x051b,
 	BNXT_ULP_ACT_HID_0108 = 0x0108,
 	BNXT_ULP_ACT_HID_05c4 = 0x05c4,
 	BNXT_ULP_ACT_HID_00a2 = 0x00a2,

index 684fa66f48..84be09b368 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Aug 17 12:16:42 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.direction               = TF_DIR_RX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,
-	.count                   = 64
+	.count                   = 2048
 	},
 	{
 	.app_id                  = 0,

@@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.direction               = TF_DIR_TX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,
-	.count                   = 64
+	.count                   = 2048
 	},
 	{
 	.app_id                  = 0,

@@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.app_id                  = 0,
 	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
 	.direction               = TF_DIR_TX,
-	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,
-	.count                   = 32
-	},
-	{
-	.app_id                  = 0,
-	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
-	.direction               = TF_DIR_TX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.count                   = 272

index 68c1e292b2..95205a2421 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Aug 20 18:05:25 2021 */
+/* date: Wed Aug 25 16:41:37 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

293 lines not on this page · raw message

index 5121d05da6..b9e120d94b 100644
@@ -724,6 +724,14 @@ struct bnxt {
 	uint16_t		chip_num;
 #define CHIP_NUM_58818		0xd818
 #define BNXT_CHIP_SR2(bp)	((bp)->chip_num == CHIP_NUM_58818)
+#define	BNXT_FLAGS2_TESTPMD_EN			BIT(3)
+#define	BNXT_TESTPMD_EN(bp)			\
+	((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
+#define BNXT_THOR_PTP_TIMESYNC_ENABLED(bp)	\
+	((bp)->flags & BNXT_FLAGS_PTP_TIMESYNC_ENABLED)
+#define	BNXT_FLAGS2_MULTIROOT_EN		BIT(4)
+#define	BNXT_MULTIROOT_EN(bp)			\
+	((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)
 
 	uint32_t		fw_cap;
 #define BNXT_FW_CAP_HOT_RESET		BIT(0)

index 503add42fd..8ccee79f0a 100644
@@ -3385,6 +3385,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
 {
 	struct hwrm_func_qcfg_input req = {0};
 	struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
+	uint16_t flags;
 	int rc;
 
 	if (!BNXT_VF_IS_TRUSTED(bp))

@@ -3408,6 +3409,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
 	bp->parent->fid = rte_le_to_cpu_16(resp->fid);
 	bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
 
+	flags = rte_le_to_cpu_16(resp->flags);
+	/* check for the multi-root support */
+	if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
+		bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
+		PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
+	}
+
 	HWRM_UNLOCK();
 
 	return 0;

2,966 lines not on this page · raw message

index 3b86410fb1..092c22e505 100644

Lines of this file are not shown. View the raw message.

index 3c6e7fe924..84c83de35c 100644
@@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist,
 {
 	uint64_t bentry;
 	uint32_t idx = 0, jdx = 0;
+	uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES;
 
 	/* Iterate all numbers that have all 1's */
 	do {
 		bentry = blist->bdata[idx++];
-	} while (bentry == -1UL && idx < blist->bsize);
+	} while (bentry == -1UL && idx <= bsize_64);
 
-	if (idx < blist->bsize) {
+	if (idx <= bsize_64) {
 		if (bentry)
 			jdx = __builtin_clzl(~bentry);
 		*index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx;
 		ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx);
 		return 0;
 	}
-	jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE);
+	jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE);
 	BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx);
 	return -1;
 }

@@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist,
 				   uint32_t index)
 {
 	uint32_t idx = 0, jdx;
+	uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES;
 
 	idx = index / ULP_INDEX_BITMAP_SIZE;
-	if (idx >= blist->bsize) {
+	if (idx >= bsize_64) {
 		BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx,
 			    blist->bsize);
 		return -EINVAL;

@@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams,
 	hash_tbl->hash_mask = size - 1;
 
 	/* allocate the memory for the bit allocator */
-	size = (cparams->num_key_entries / sizeof(uint64_t)) + 1;
+	size = (cparams->num_key_entries / sizeof(uint64_t));
+	size = ULP_BYTE_ROUND_OFF_8(size);
 	hash_tbl->bit_list.bsize = size;
 	hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size,
 					       ULP_BUFFER_ALIGN_64_BYTE);

@@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl,
 		BNXT_TF_DBG(ERR, "Error in bit list alloc\n");
 		return -ENOMEM;
 	}
-
+	if (key_index > hash_tbl->num_key_entries) {
+		BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index,
+			    hash_tbl->num_key_entries);
+		ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index);
+		return -ENOMEM;
+	}
 	/* Update the hash entry */
 	ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index);
 

index 9ed66525b7..c2146bd53c 100644
@@ -1058,8 +1058,8 @@ struct hwrm_err_output {
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 2
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 54
-#define HWRM_VERSION_STR "1.10.2.54"
+#define HWRM_VERSION_RSVD 55
+#define HWRM_VERSION_STR "1.10.2.55"
 
 /****************
  * hwrm_ver_get *

@@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input {
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates tx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
 	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
 		HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
+	/*
+	 * When set use the special access register access to clear
+	 * the table entry on read.
+	 */
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \
+		UINT32_C(0x2)
 	/* unused. */
 	uint8_t	unused0[2];
 	/*

@@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input {
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates tx flow. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
 	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
 		HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
+	/*
+	 * When set use the special access register access to clear
+	 * the table entries on read.
+	 */
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
+		UINT32_C(0x2)
 	/* unused. */
 	uint8_t	unused0[2];
 	/*

index 0fbb2fe837..ea6e2af7ce 100644
@@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 		     uint16_t hcapi_type,
 		     uint16_t size,
 		     uint8_t *data,
-		     uint32_t index)
+		     uint32_t index,
+		     bool clear_on_read)
 {
 	int rc;
 	struct hwrm_tf_tbl_type_get_input req = { 0 };

@@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 	uint8_t fw_session_id;
 	struct tf_dev_info *dev;
 	struct tf_session *tfs;
+	uint32_t flags = 0;
 
 	/* Retrieve the session information */
 	rc = tf_session_get_session_internal(tfp, &tfs);

@@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	flags = (dir == TF_DIR_TX ?
+		 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX :
+		 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX);
+
+	if (clear_on_read)
+		flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ;
 
 	/* Populate the request */
 	req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
-	req.flags = tfp_cpu_to_le_16(dir);
+	req.flags = tfp_cpu_to_le_16(flags);
 	req.type = tfp_cpu_to_le_32(hcapi_type);
 	req.index = tfp_cpu_to_le_32(index);
 

@@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			  uint32_t starting_idx,
 			  uint16_t num_entries,
 			  uint16_t entry_sz_in_bytes,
-			  uint64_t physical_mem_addr)
+			  uint64_t physical_mem_addr,
+			  bool clear_on_read)
 {
 	int rc;
 	struct tfp_send_msg_parms parms = { 0 };

@@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 	uint8_t fw_session_id;
 	struct tf_dev_info *dev;
 	struct tf_session *tfs;
+	uint32_t flags = 0;
 
 	/* Retrieve the session information */
 	rc = tf_session_get_session(tfp, &tfs);

@@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	flags = (dir == TF_DIR_TX ?
+		 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX :
+		 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX);
+
+	if (clear_on_read)
+		flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ;
 
 	/* Populate the request */
 	req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
-	req.flags = tfp_cpu_to_le_16(dir);
+	req.flags = tfp_cpu_to_le_16(flags);
 	req.type = tfp_cpu_to_le_32(hcapi_type);
 	req.start_index = tfp_cpu_to_le_32(starting_idx);
 	req.num_entries = tfp_cpu_to_le_32(num_entries);

index b26b15bfa3..718bc2f3b2 100644
@@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp,
 			 uint16_t hcapi_type,
 			 uint16_t size,
 			 uint8_t *data,
-			 uint32_t index);
+			 uint32_t index,
+			 bool clear_on_read);
 
 /* HWRM Tunneled messages */
 

@@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			      uint32_t starting_idx,
 			      uint16_t num_entries,
 			      uint16_t entry_sz_in_bytes,
-			      uint64_t physical_mem_addr);
+			      uint64_t physical_mem_addr,
+			      bool clear_on_read);
 
 /**
  * Sends Set message of a IF Table Type element to the firmware.

index 0a8720e7b6..12eca36491 100644
@@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp,
 				  hcapi_type,
 				  parms->data_sz_in_bytes,
 				  parms->data,
-				  parms->idx);
+				  parms->idx,
+				  false);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Get failed, type:%s, rc:%s\n",

@@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp,
 				       parms->starting_idx,
 				       parms->num_entries,
 				       parms->entry_sz_in_bytes,
-				       parms->physical_mem_addr);
+				       parms->physical_mem_addr,
+				       false);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Bulk get failed, type:%s, rc:%s\n",

index 636811bc2d..567f912dfa 100644
@@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp,
 	struct tf_tbl_sram_get_info_parms iparms = { 0 };
 	struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
 	void *sram_handle = NULL;
+	bool clear_on_read = false;
 
 	TF_CHECK_PARMS3(tfp, parms, parms->data);
 

@@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	if (parms->type == TF_TBL_TYPE_ACT_STATS_64)
+		clear_on_read = true;
 
 	/* Get the entry */
 	rc = tf_msg_get_tbl_entry(tfp,

@@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp,
 				  hcapi_type,
 				  parms->data_sz_in_bytes,
 				  parms->data,
-				  parms->idx);
+				  parms->idx,
+				  clear_on_read);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Get failed, type:%s, rc:%s\n",

@@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 	struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
 	bool allocated = false;
 	void *sram_handle = NULL;
+	bool clear_on_read = false;
 
 	TF_CHECK_PARMS2(tfp, parms);
 

@@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 		return rc;
 	}
 
+	if (parms->type == TF_TBL_TYPE_ACT_STATS_64)
+		clear_on_read = true;
+
 	/* Get the entries */
 	rc = tf_msg_bulk_get_tbl_entry(tfp,
 				       parms->dir,

@@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 				       parms->starting_idx,
 				       parms->num_entries,
 				       parms->entry_sz_in_bytes,
-				       parms->physical_mem_addr);
+				       parms->physical_mem_addr,
+				       clear_on_read);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Bulk get failed, type:%s, rc:%s\n",

index 092c22e505..3083c40113 100644
@@ -1488,7 +1488,8 @@ bnxt_ulp_port_init(struct bnxt *bp)
 		goto jump_to_error;
 	}
 
-	if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp))
+	/* set the accumulation of the stats */
+	if (BNXT_ACCUM_STATS_EN(bp))
 		bp->ulp_ctx->cfg_data->accum_stats = true;
 
 	BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n",

index b9e120d94b..9bf6697006 100644
@@ -1060,19 +1060,6 @@ int32_t
 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
 int32_t
 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
-void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
-			uint8_t *mac, uint8_t *parent_mac);
-uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
-struct bnxt *bnxt_get_bp(uint16_t port);
-uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
-		       enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_phy_port_id(uint16_t port);
-uint16_t bnxt_get_vport(uint16_t port);
-enum bnxt_ulp_intf_type
-bnxt_get_interface_type(uint16_t port);
 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 
 void bnxt_cancel_fc_thread(struct bnxt *bp);

209 lines not on this page · raw message

index 3083c40113..58a58a431d 100644
@@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
 }
 
 int32_t
-bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
+bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
 			     uint8_t app_id, uint32_t dev_id)
 {
 	struct bnxt_ulp_app_capabilities_info *info;
 	uint32_t num = 0;
 	uint16_t i;
 	bool found = false;
+	struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
 
 	if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) {
 		BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",

@@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
 		if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY)
 			ulp_ctx->cfg_data->ulp_flags |=
 				BNXT_ULP_APP_UNICAST_ONLY;
+		if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) {
+			/* Enable socket direction only if MR is enabled in fw*/
+			if (BNXT_MULTIROOT_EN(bp))
+				ulp_ctx->cfg_data->ulp_flags |=
+					BNXT_ULP_APP_SOCKET_DIRECT;
+		}
 	}
 	if (!found) {
 		BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",

@@ -837,7 +844,7 @@ ulp_ctx_init(struct bnxt *bp,
 	}
 	BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
 
-	rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
+	rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n",
 			    bp->app_id, devid);

index 006df9cbc5..68f1470c61 100644
@@ -13,6 +13,7 @@
 #include "rte_version.h"
 #include "rte_ethdev.h"
 
+#include "bnxt.h"
 #include "ulp_template_db_enum.h"
 #include "ulp_tun.h"
 #include "bnxt_tf_common.h"

@@ -33,12 +34,15 @@
 #define BNXT_ULP_APP_DEV_UNSUPPORTED	0x4
 #define BNXT_ULP_HIGH_AVAIL_ENABLED	0x8
 #define BNXT_ULP_APP_UNICAST_ONLY	0x10
+#define BNXT_ULP_APP_SOCKET_DIRECT	0x20
+
 #define ULP_VF_REP_IS_ENABLED(flag)	((flag) & BNXT_ULP_VF_REP_ENABLED)
 #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\
 					     BNXT_ULP_SHARED_SESSION_ENABLED)
 #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag)	((flag) &\
 						 BNXT_ULP_APP_DEV_UNSUPPORTED)
 #define ULP_HIGH_AVAIL_IS_ENABLED(flag)	((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED)
+#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT)
 
 enum bnxt_ulp_flow_mem_type {
 	BNXT_ULP_FLOW_MEM_TYPE_INT = 0,

@@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info *
 bnxt_ulp_app_cap_list_get(uint32_t *num_entries);
 
 int32_t
-bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
+bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
 			     uint8_t app_id, uint32_t dev_id);
 
 struct bnxt_ulp_resource_resv_info *

index 413e4c3b26..6413afdaf2 100644
@@ -118,9 +118,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID,
 			    params->flow_sig_id);
 
+	if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags))
+		return;
+
 	/* update the WC Priority flag */
-	if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) &&
-	    ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) {
+	if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) {
 		enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW;
 		int32_t rc;
 

@@ -132,6 +134,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 					    BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG,
 					    1);
 	}
+
+	/* Update the socket direct flag */
+	if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags))
+		ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1);
 }
 
 /* Function to create the rte flow. */

index fcd460e707..31a94c14dc 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Aug 26 17:43:36 2021 */
+/* date: Thu Sep  9 11:11:05 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_

@@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx {
 	BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
 	BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
 	BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
-	BNXT_ULP_CF_IDX_LAST = 74
+	BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74,
+	BNXT_ULP_CF_IDX_LAST = 75
 };
 
 enum bnxt_ulp_cond_list_opc {

@@ -582,7 +583,8 @@ enum bnxt_ulp_template_type {
 enum bnxt_ulp_app_cap {
 	BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001,
 	BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002,
-	BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004
+	BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004,
+	BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008
 };
 
 enum bnxt_ulp_fdb_resource_flags {

index 84be09b368..5383e2cd70 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Aug 26 17:43:36 2021 */
+/* date: Thu Sep  9 11:11:05 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
 	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
 	.flags                   = BNXT_ULP_APP_CAP_SHARED_EN |
 				   BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
-				   BNXT_ULP_APP_CAP_UNICAST_ONLY
+				   BNXT_ULP_APP_CAP_UNICAST_ONLY |
+				   BNXT_ULP_APP_CAP_SOCKET_DIRECT
 	},
 	{
 	.app_id                  = 2,

index 31a94c14dc..8706e45f28 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Sep  9 11:11:05 2021 */
+/* date: Thu Sep  9 12:11:08 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_

@@ -48,7 +48,7 @@
 #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
-#define ULP_THOR_CLASS_COND_LIST_SIZE 55
+#define ULP_THOR_CLASS_COND_LIST_SIZE 54
 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2

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index 3a9c9bba27..09ebfeb785 100644
@@ -1079,7 +1079,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
 
 	/* Set the ipv4 header bitmap and computed l3 header bitmaps */
 	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
-	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
+	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) ||
+	    ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4);
 		ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1);
 		inner_flag = 1;

@@ -1205,7 +1206,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
 
 	/* Set the ipv6 header bitmap and computed l3 header bitmaps */
 	if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
-	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
+	    ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) ||
+	    ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) {
 		ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6);
 		ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1);
 		inner_flag = 1;

@@ -2087,7 +2089,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item
 		       BNXT_ULP_ACT_BIT_VXLAN_DECAP);
 	/* Update computational field with tunnel decap info */
 	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1);
-	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
 	return BNXT_TF_RC_SUCCESS;
 }
 

index d3bfb8c12d..7d1bc06a3e 100644
@@ -27,7 +27,7 @@
 #define BNXT_ULP_PROTO_HDR_UDP_NUM	4
 #define BNXT_ULP_PROTO_HDR_TCP_NUM	9
 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM	4
-#define BNXT_ULP_PROTO_HDR_GRE_NUM	6
+#define BNXT_ULP_PROTO_HDR_GRE_NUM	2
 #define BNXT_ULP_PROTO_HDR_ICMP_NUM	5
 #define BNXT_ULP_PROTO_HDR_MAX		128
 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX	64

index c2146bd53c..114e9fcc88 100644
@@ -1058,8 +1058,8 @@ struct hwrm_err_output {
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 2
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 55
-#define HWRM_VERSION_STR "1.10.2.55"
+#define HWRM_VERSION_RSVD 58
+#define HWRM_VERSION_STR "1.10.2.58"
 
 /****************
  * hwrm_ver_get *

@@ -45178,7 +45178,7 @@ struct hwrm_tf_version_get_input {
 	uint64_t	resp_addr;
 } __rte_packed;
 
-/* hwrm_tf_version_get_output (size:128b/16B) */
+/* hwrm_tf_version_get_output (size:256b/32B) */
 struct hwrm_tf_version_get_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;

@@ -45195,7 +45195,14 @@ struct hwrm_tf_version_get_output {
 	/* Version Update number. */
 	uint8_t	update;
 	/* unused. */
-	uint8_t	unused0[4];
+	uint8_t	unused0[5];
+	/*
+	 * This field is used to indicate device's capabilities and
+	 * configurations.
+	 */
+	uint64_t	dev_caps_cfg;
+	/* unused. */
+	uint8_t	unused1[7];
 	/*
 	 * This field is used in Output records to indicate that the output
 	 * is completely written to RAM. This field should be read as '1'

index 936102c804..7873bfc02c 100644
@@ -1802,3 +1802,33 @@ int tf_get_session_info(struct tf *tfp,
 
 	return 0;
 }
+
+int tf_get_version(struct tf *tfp,
+		   struct tf_get_version_parms *parms)
+{
+	int rc;
+	struct tf_dev_info dev;
+
+	TF_CHECK_PARMS2(tfp, parms);
+
+	/* This function can be called before open session, filter
+	 * out any non-supported device types on the Core side.
+	 */
+	if (parms->device_type != TF_DEVICE_TYPE_WH &&
+	    parms->device_type != TF_DEVICE_TYPE_THOR &&
+	    parms->device_type != TF_DEVICE_TYPE_SR) {
+		TFP_DRV_LOG(ERR,
+			    "Unsupported device type %d\n",
+			    parms->device_type);
+		return -ENOTSUP;
+	}
+
+	tf_dev_bind_ops(parms->device_type, &dev);
+
+	rc = tf_msg_get_version(parms->bp, &dev, parms);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+

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index ea6e2af7ce..25bf026658 100644
@@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp,
 
 	return 0;
 }
+
+int
+tf_msg_get_version(struct bnxt *bp,
+		   struct tf_dev_info *dev,
+		   struct tf_get_version_parms *params)
+
+{
+	int rc;
+	struct hwrm_tf_version_get_input req = { 0 };
+	struct hwrm_tf_version_get_output resp = { 0 };
+	struct tfp_send_msg_parms parms = { 0 };
+
+	/* Populate the request */
+	parms.tf_type = HWRM_TF_VERSION_GET,
+	parms.req_data = (uint32_t *)&req;
+	parms.req_size = sizeof(req);
+	parms.resp_data = (uint32_t *)&resp;
+	parms.resp_size = sizeof(resp);
+	parms.mailbox = dev->ops->tf_dev_get_mailbox();
+
+	rc = tfp_send_msg_direct(bp,
+				 &parms);
+
+	params->major = resp.major;
+	params->minor = resp.minor;
+	params->update = resp.update;
+
+	dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg,
+					&params->dev_ident_caps,
+					&params->dev_tcam_caps,
+					&params->dev_tbl_caps,
+					&params->dev_em_caps);
+
+	return rc;
+}

index 718bc2f3b2..08d20cdd7a 100644
@@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp,
 int tf_msg_get_if_tbl_entry(struct tf *tfp,
 			    struct tf_if_tbl_get_parms *params);
 
+/**
+ * Send get version request to the firmware.
+ *
+ * [in] bp
+ *   Pointer to bnxt handle
+ *
+ * [in] dev
+ *   Pointer to the associated device
+ *
+ * [in/out] parms
+ *   Pointer to the version info parameter
+ *
+ * Returns:
+ *  0 on Success else internal Truflow error
+ */
+int
+tf_msg_get_version(struct bnxt *bp,
+		   struct tf_dev_info *dev,
+		   struct tf_get_version_parms *parms);
 #endif  /* _TF_MSG_H_ */

index 9bf6697006..0209bb5c39 100644
@@ -240,7 +240,11 @@ struct bnxt_parent_info {
 struct bnxt_pf_info {
 #define BNXT_FIRST_PF_FID	1
 #define BNXT_MAX_VFS(bp)	((bp)->pf->max_vfs)
-#define BNXT_MAX_VF_REPS	64
+#define BNXT_MAX_VF_REPS_WH     64
+#define BNXT_MAX_VF_REPS_TH     256
+#define BNXT_MAX_VF_REPS(bp) \
+				(BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \
+				BNXT_MAX_VF_REPS_WH)
 #define BNXT_TOTAL_VFS(bp)	((bp)->pf->total_vfs)
 #define BNXT_FIRST_VF_FID	128
 #define BNXT_PF_RINGS_USED(bp)	bnxt_get_num_queues(bp)

index 63ff02a198..6bb70d516e 100644
@@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp,
 			BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT;
 	PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid);
 
-	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) {
+	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) {
 		eth_dev = bp->rep_info[vf_id].vfr_eth_dev;
 		if (!eth_dev)
 			continue;

index 63d764f968..034f4cdcaa 100644
@@ -1185,7 +1185,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 	struct rte_eth_link *link = &eth_dev->data->dev_link;
 
 	if (link->link_status)
-		PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
+		PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n",
 			eth_dev->data->port_id,
 			(uint32_t)link->link_speed,
 			(link->link_duplex == ETH_LINK_FULL_DUPLEX) ?

@@ -6046,7 +6046,7 @@ static int bnxt_init_rep_info(struct bnxt *bp)
 		return 0;
 
 	bp->rep_info = rte_zmalloc("bnxt_rep_info",
-				   sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
+				   sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp),
 				   0);
 	if (!bp->rep_info) {
 		PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");

@@ -6088,7 +6088,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 {
 	struct rte_eth_dev *vf_rep_eth_dev;
 	char name[RTE_ETH_NAME_MAX_LEN];
-	struct bnxt *backing_bp;
+	struct bnxt *backing_bp = backing_eth_dev->data->dev_private;
+	uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp);
+
 	uint16_t num_rep;
 	int i, ret = 0;
 	struct rte_kvargs *kvlist = NULL;

@@ -6101,9 +6103,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		return -ENOTSUP;
 	}
 	num_rep = eth_da->nb_representor_ports;
-	if (num_rep > BNXT_MAX_VF_REPS) {
+	if (num_rep > max_vf_reps) {
 		PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
-			    num_rep, BNXT_MAX_VF_REPS);
+			    num_rep, max_vf_reps);
 		return -EINVAL;
 	}
 

@@ -6114,8 +6116,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		return -EINVAL;
 	}
 
-	backing_bp = backing_eth_dev->data->dev_private;
-
 	if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
 		PMD_DRV_LOG(ERR,
 			    "Not a PF or trusted VF. No Representor support\n");

@@ -6135,9 +6135,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 			.parent_dev = backing_eth_dev
 		};
 
-		if (representor.vf_id >= BNXT_MAX_VF_REPS) {
+		if (representor.vf_id >= max_vf_reps) {
 			PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
-				    representor.vf_id, BNXT_MAX_VF_REPS);
+				    representor.vf_id, max_vf_reps);
 			continue;
 		}
 

index bdbad53b7d..0feefe156c 100644
@@ -209,7 +209,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 	eth_dev->data->dev_link.link_status = link->link_status;
 	eth_dev->data->dev_link.link_autoneg = link->link_autoneg;
 
-	PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n");
 	bnxt_print_link_info(eth_dev);
 
 	PMD_DRV_LOG(INFO,

@@ -818,7 +817,7 @@ int bnxt_rep_stop_all(struct bnxt *bp)
 	if (!bp->rep_info)
 		return 0;
 
-	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) {
+	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) {
 		rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev;
 		if (!rep_eth_dev)
 			continue;

index 68f1470c61..960a5a0c93 100644
@@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx,
 				  uint32_t *flags);
 
 int32_t
-bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx,
+bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx,
 			  struct bnxt_ulp_df_rule_info *info);
 
 struct bnxt_ulp_vfr_rule_info*

index 5383e2cd70..e43e341927 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Sep  9 11:11:05 2021 */
+/* date: Thu Sep 16 11:49:55 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
 	},
 	[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
 		BNXT_ULP_DIRECTION_EGRESS] = {
-	.name                    = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
-	.result_num_entries      = 256,
+	.name                    = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
+	.result_num_entries      = 4096,
 	.result_num_bytes        = 6,
 	.key_num_bytes           = 17,
 	.num_buckets             = 8,
-	.hash_tbl_entries        = 1024,
+	.hash_tbl_entries        = 16384,
 	.result_byte_order       = BNXT_ULP_BYTE_ORDER_LE
 	}
 };

index d8336d164e..01233c0f5e 100644
@@ -441,7 +441,7 @@ void
 bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
 {
 	struct bnxt_ulp_df_rule_info *info;
-	uint8_t port_id;
+	uint16_t port_id;
 
 	if (!BNXT_TRUFLOW_EN(bp) ||
 	    BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))

@@ -505,7 +505,7 @@ int32_t
 bnxt_ulp_create_df_rules(struct bnxt *bp)
 {
 	struct bnxt_ulp_df_rule_info *info;
-	uint8_t port_id;
+	uint16_t port_id;
 	int rc = 0;
 
 	if (!BNXT_TRUFLOW_EN(bp) ||

@@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
 	struct bnxt *bp = parent_dev->data->dev_private;
 	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
-	uint8_t port_id;
+	uint16_t port_id;
 	int rc;
 
 	if (!bp || !BNXT_TRUFLOW_EN(bp))

index 0da6070d7d..ce878d8e02 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon May 17 15:30:41 2021 */
+/* date: Wed Aug 25 14:37:06 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_04bc] = 30,
 	[BNXT_ULP_ACT_HID_00a9] = 31,
 	[BNXT_ULP_ACT_HID_020f] = 32,
-	[BNXT_ULP_ACT_HID_04a9] = 33,
-	[BNXT_ULP_ACT_HID_01fc] = 34,
-	[BNXT_ULP_ACT_HID_04be] = 35,
-	[BNXT_ULP_ACT_HID_00ab] = 36,
-	[BNXT_ULP_ACT_HID_0211] = 37,
-	[BNXT_ULP_ACT_HID_04ab] = 38,
-	[BNXT_ULP_ACT_HID_01fe] = 39,
-	[BNXT_ULP_ACT_HID_0667] = 40,
-	[BNXT_ULP_ACT_HID_0254] = 41,
-	[BNXT_ULP_ACT_HID_03ba] = 42,
-	[BNXT_ULP_ACT_HID_0654] = 43,
-	[BNXT_ULP_ACT_HID_03a7] = 44,
-	[BNXT_ULP_ACT_HID_0669] = 45,
-	[BNXT_ULP_ACT_HID_0256] = 46,
-	[BNXT_ULP_ACT_HID_03bc] = 47,
-	[BNXT_ULP_ACT_HID_0656] = 48,
-	[BNXT_ULP_ACT_HID_03a9] = 49,
-	[BNXT_ULP_ACT_HID_021b] = 50,
-	[BNXT_ULP_ACT_HID_021c] = 51,
-	[BNXT_ULP_ACT_HID_021e] = 52,
-	[BNXT_ULP_ACT_HID_063f] = 53,
-	[BNXT_ULP_ACT_HID_0510] = 54,
-	[BNXT_ULP_ACT_HID_03c6] = 55,
-	[BNXT_ULP_ACT_HID_0082] = 56,
-	[BNXT_ULP_ACT_HID_06bb] = 57,
-	[BNXT_ULP_ACT_HID_021d] = 58,
-	[BNXT_ULP_ACT_HID_0641] = 59,
-	[BNXT_ULP_ACT_HID_0512] = 60,
-	[BNXT_ULP_ACT_HID_03c8] = 61,
-	[BNXT_ULP_ACT_HID_0084] = 62,
-	[BNXT_ULP_ACT_HID_06bd] = 63,
-	[BNXT_ULP_ACT_HID_06d7] = 64,
-	[BNXT_ULP_ACT_HID_02c4] = 65,
-	[BNXT_ULP_ACT_HID_042a] = 66,
-	[BNXT_ULP_ACT_HID_06c4] = 67,
-	[BNXT_ULP_ACT_HID_0417] = 68,
-	[BNXT_ULP_ACT_HID_06d9] = 69,
-	[BNXT_ULP_ACT_HID_02c6] = 70,
-	[BNXT_ULP_ACT_HID_042c] = 71,
-	[BNXT_ULP_ACT_HID_06c6] = 72,
-	[BNXT_ULP_ACT_HID_0419] = 73,
-	[BNXT_ULP_ACT_HID_0119] = 74,
-	[BNXT_ULP_ACT_HID_046f] = 75,
-	[BNXT_ULP_ACT_HID_05d5] = 76,
-	[BNXT_ULP_ACT_HID_0106] = 77,
-	[BNXT_ULP_ACT_HID_05c2] = 78,
-	[BNXT_ULP_ACT_HID_011b] = 79,
-	[BNXT_ULP_ACT_HID_0471] = 80,
-	[BNXT_ULP_ACT_HID_05d7] = 81,
-	[BNXT_ULP_ACT_HID_0108] = 82,
-	[BNXT_ULP_ACT_HID_05c4] = 83,
-	[BNXT_ULP_ACT_HID_00a2] = 84,
-	[BNXT_ULP_ACT_HID_00a4] = 85
+	[BNXT_ULP_ACT_HID_0153] = 33,
+	[BNXT_ULP_ACT_HID_04a9] = 34,
+	[BNXT_ULP_ACT_HID_01fc] = 35,
+	[BNXT_ULP_ACT_HID_04be] = 36,
+	[BNXT_ULP_ACT_HID_00ab] = 37,
+	[BNXT_ULP_ACT_HID_0211] = 38,
+	[BNXT_ULP_ACT_HID_0155] = 39,
+	[BNXT_ULP_ACT_HID_04ab] = 40,
+	[BNXT_ULP_ACT_HID_01fe] = 41,
+	[BNXT_ULP_ACT_HID_0667] = 42,
+	[BNXT_ULP_ACT_HID_0254] = 43,
+	[BNXT_ULP_ACT_HID_03ba] = 44,
+	[BNXT_ULP_ACT_HID_02fe] = 45,
+	[BNXT_ULP_ACT_HID_0654] = 46,
+	[BNXT_ULP_ACT_HID_03a7] = 47,
+	[BNXT_ULP_ACT_HID_0669] = 48,
+	[BNXT_ULP_ACT_HID_0256] = 49,
+	[BNXT_ULP_ACT_HID_03bc] = 50,
+	[BNXT_ULP_ACT_HID_0300] = 51,
+	[BNXT_ULP_ACT_HID_0656] = 52,
+	[BNXT_ULP_ACT_HID_03a9] = 53,
+	[BNXT_ULP_ACT_HID_021b] = 54,
+	[BNXT_ULP_ACT_HID_021c] = 55,
+	[BNXT_ULP_ACT_HID_021e] = 56,
+	[BNXT_ULP_ACT_HID_063f] = 57,
+	[BNXT_ULP_ACT_HID_0510] = 58,
+	[BNXT_ULP_ACT_HID_03c6] = 59,
+	[BNXT_ULP_ACT_HID_0082] = 60,
+	[BNXT_ULP_ACT_HID_06bb] = 61,
+	[BNXT_ULP_ACT_HID_021d] = 62,
+	[BNXT_ULP_ACT_HID_0641] = 63,
+	[BNXT_ULP_ACT_HID_0512] = 64,
+	[BNXT_ULP_ACT_HID_03c8] = 65,
+	[BNXT_ULP_ACT_HID_0084] = 66,
+	[BNXT_ULP_ACT_HID_06bd] = 67,
+	[BNXT_ULP_ACT_HID_06d7] = 68,
+	[BNXT_ULP_ACT_HID_02c4] = 69,
+	[BNXT_ULP_ACT_HID_042a] = 70,
+	[BNXT_ULP_ACT_HID_036e] = 71,
+	[BNXT_ULP_ACT_HID_06c4] = 72,
+	[BNXT_ULP_ACT_HID_0417] = 73,
+	[BNXT_ULP_ACT_HID_06d9] = 74,
+	[BNXT_ULP_ACT_HID_02c6] = 75,
+	[BNXT_ULP_ACT_HID_042c] = 76,
+	[BNXT_ULP_ACT_HID_0370] = 77,
+	[BNXT_ULP_ACT_HID_06c6] = 78,
+	[BNXT_ULP_ACT_HID_0419] = 79,
+	[BNXT_ULP_ACT_HID_0119] = 80,
+	[BNXT_ULP_ACT_HID_046f] = 81,
+	[BNXT_ULP_ACT_HID_05d5] = 82,
+	[BNXT_ULP_ACT_HID_0519] = 83,
+	[BNXT_ULP_ACT_HID_0106] = 84,
+	[BNXT_ULP_ACT_HID_05c2] = 85,
+	[BNXT_ULP_ACT_HID_011b] = 86,
+	[BNXT_ULP_ACT_HID_0471] = 87,
+	[BNXT_ULP_ACT_HID_05d7] = 88,
+	[BNXT_ULP_ACT_HID_051b] = 89,
+	[BNXT_ULP_ACT_HID_0108] = 90,
+	[BNXT_ULP_ACT_HID_05c4] = 91,
+	[BNXT_ULP_ACT_HID_00a2] = 92,
+	[BNXT_ULP_ACT_HID_00a4] = 93
 };
 
 /* Array for the act matcher list */

@@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 3
 	},
 	[33] = {
-	.act_hid = BNXT_ULP_ACT_HID_04a9,
+	.act_hid = BNXT_ULP_ACT_HID_0153,
 	.act_pattern_id = 3,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[34] = {
-	.act_hid = BNXT_ULP_ACT_HID_01fc,
+	.act_hid = BNXT_ULP_ACT_HID_04a9,
 	.act_pattern_id = 4,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_ACT_BIT_SET_TP_DST |

@@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 3
 	},
 	[35] = {
-	.act_hid = BNXT_ULP_ACT_HID_04be,
+	.act_hid = BNXT_ULP_ACT_HID_01fc,
 	.act_pattern_id = 5,
 	.app_sig = 0,
 	.act_sig = { .bits =
-		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[36] = {
-	.act_hid = BNXT_ULP_ACT_HID_00ab,
+	.act_hid = BNXT_ULP_ACT_HID_04be,
 	.act_pattern_id = 6,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
-		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[37] = {
-	.act_hid = BNXT_ULP_ACT_HID_0211,
+	.act_hid = BNXT_ULP_ACT_HID_00ab,
 	.act_pattern_id = 7,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
-		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
 	[38] = {
-	.act_hid = BNXT_ULP_ACT_HID_04ab,
+	.act_hid = BNXT_ULP_ACT_HID_0211,
 	.act_pattern_id = 8,
 	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[39] = {
+	.act_hid = BNXT_ULP_ACT_HID_0155,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[40] = {
+	.act_hid = BNXT_ULP_ACT_HID_04ab,
+	.act_pattern_id = 10,
+	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |

@@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[39] = {
+	[41] = {
 	.act_hid = BNXT_ULP_ACT_HID_01fe,
-	.act_pattern_id = 9,
+	.act_pattern_id = 11,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[40] = {
+	[42] = {
 	.act_hid = BNXT_ULP_ACT_HID_0667,
-	.act_pattern_id = 10,
+	.act_pattern_id = 12,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[41] = {
+	[43] = {
 	.act_hid = BNXT_ULP_ACT_HID_0254,
-	.act_pattern_id = 11,
+	.act_pattern_id = 13,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[42] = {
+	[44] = {
 	.act_hid = BNXT_ULP_ACT_HID_03ba,
-	.act_pattern_id = 12,
+	.act_pattern_id = 14,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[43] = {
+	[45] = {
+	.act_hid = BNXT_ULP_ACT_HID_02fe,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[46] = {
 	.act_hid = BNXT_ULP_ACT_HID_0654,
-	.act_pattern_id = 13,
+	.act_pattern_id = 16,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[44] = {
+	[47] = {
 	.act_hid = BNXT_ULP_ACT_HID_03a7,
-	.act_pattern_id = 14,
+	.act_pattern_id = 17,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[45] = {
+	[48] = {
 	.act_hid = BNXT_ULP_ACT_HID_0669,
-	.act_pattern_id = 15,
+	.act_pattern_id = 18,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[46] = {
+	[49] = {
 	.act_hid = BNXT_ULP_ACT_HID_0256,
-	.act_pattern_id = 16,
+	.act_pattern_id = 19,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[47] = {
+	[50] = {
 	.act_hid = BNXT_ULP_ACT_HID_03bc,
-	.act_pattern_id = 17,
+	.act_pattern_id = 20,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[48] = {
+	[51] = {
+	.act_hid = BNXT_ULP_ACT_HID_0300,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[52] = {
 	.act_hid = BNXT_ULP_ACT_HID_0656,
-	.act_pattern_id = 18,
+	.act_pattern_id = 22,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[49] = {
+	[53] = {
 	.act_hid = BNXT_ULP_ACT_HID_03a9,
-	.act_pattern_id = 19,
+	.act_pattern_id = 23,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 3
 	},
-	[50] = {
+	[54] = {
 	.act_hid = BNXT_ULP_ACT_HID_021b,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[51] = {
+	[55] = {
 	.act_hid = BNXT_ULP_ACT_HID_021c,
 	.act_pattern_id = 1,
 	.app_sig = 0,

@@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[52] = {
+	[56] = {
 	.act_hid = BNXT_ULP_ACT_HID_021e,
 	.act_pattern_id = 2,
 	.app_sig = 0,

@@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[53] = {
+	[57] = {
 	.act_hid = BNXT_ULP_ACT_HID_063f,
 	.act_pattern_id = 3,
 	.app_sig = 0,

@@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[54] = {
+	[58] = {
 	.act_hid = BNXT_ULP_ACT_HID_0510,
 	.act_pattern_id = 4,
 	.app_sig = 0,

@@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[55] = {
+	[59] = {
 	.act_hid = BNXT_ULP_ACT_HID_03c6,
 	.act_pattern_id = 5,
 	.app_sig = 0,

@@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[56] = {
+	[60] = {
 	.act_hid = BNXT_ULP_ACT_HID_0082,
 	.act_pattern_id = 6,
 	.app_sig = 0,

@@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[57] = {
+	[61] = {
 	.act_hid = BNXT_ULP_ACT_HID_06bb,
 	.act_pattern_id = 7,
 	.app_sig = 0,

@@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[58] = {
+	[62] = {
 	.act_hid = BNXT_ULP_ACT_HID_021d,
 	.act_pattern_id = 8,
 	.app_sig = 0,

@@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[59] = {
+	[63] = {
 	.act_hid = BNXT_ULP_ACT_HID_0641,
 	.act_pattern_id = 9,
 	.app_sig = 0,

@@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[60] = {
+	[64] = {
 	.act_hid = BNXT_ULP_ACT_HID_0512,
 	.act_pattern_id = 10,
 	.app_sig = 0,

@@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[61] = {
+	[65] = {
 	.act_hid = BNXT_ULP_ACT_HID_03c8,
 	.act_pattern_id = 11,
 	.app_sig = 0,

@@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[62] = {
+	[66] = {
 	.act_hid = BNXT_ULP_ACT_HID_0084,
 	.act_pattern_id = 12,
 	.app_sig = 0,

@@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[63] = {
+	[67] = {
 	.act_hid = BNXT_ULP_ACT_HID_06bd,
 	.act_pattern_id = 13,
 	.app_sig = 0,

@@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 4
 	},
-	[64] = {
+	[68] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d7,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[65] = {
+	[69] = {
 	.act_hid = BNXT_ULP_ACT_HID_02c4,
 	.act_pattern_id = 1,
 	.app_sig = 0,

@@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[66] = {
+	[70] = {
 	.act_hid = BNXT_ULP_ACT_HID_042a,
 	.act_pattern_id = 2,
 	.app_sig = 0,

@@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[67] = {
-	.act_hid = BNXT_ULP_ACT_HID_06c4,
+	[71] = {
+	.act_hid = BNXT_ULP_ACT_HID_036e,
 	.act_pattern_id = 3,
 	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[72] = {
+	.act_hid = BNXT_ULP_ACT_HID_06c4,
+	.act_pattern_id = 4,
+	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
 		BNXT_ULP_ACT_BIT_SET_TP_SRC |

@@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[68] = {
+	[73] = {
 	.act_hid = BNXT_ULP_ACT_HID_0417,
-	.act_pattern_id = 4,
+	.act_pattern_id = 5,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |

@@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[69] = {
+	[74] = {
 	.act_hid = BNXT_ULP_ACT_HID_06d9,
-	.act_pattern_id = 5,
+	.act_pattern_id = 6,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[70] = {
+	[75] = {
 	.act_hid = BNXT_ULP_ACT_HID_02c6,
-	.act_pattern_id = 6,
+	.act_pattern_id = 7,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[71] = {
+	[76] = {
 	.act_hid = BNXT_ULP_ACT_HID_042c,
-	.act_pattern_id = 7,
+	.act_pattern_id = 8,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[72] = {
+	[77] = {
+	.act_hid = BNXT_ULP_ACT_HID_0370,
+	.act_pattern_id = 9,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[78] = {
 	.act_hid = BNXT_ULP_ACT_HID_06c6,
-	.act_pattern_id = 8,
+	.act_pattern_id = 10,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[73] = {
+	[79] = {
 	.act_hid = BNXT_ULP_ACT_HID_0419,
-	.act_pattern_id = 9,
+	.act_pattern_id = 11,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |

@@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[74] = {
+	[80] = {
 	.act_hid = BNXT_ULP_ACT_HID_0119,
-	.act_pattern_id = 10,
+	.act_pattern_id = 12,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[75] = {
+	[81] = {
 	.act_hid = BNXT_ULP_ACT_HID_046f,
-	.act_pattern_id = 11,
+	.act_pattern_id = 13,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[76] = {
+	[82] = {
 	.act_hid = BNXT_ULP_ACT_HID_05d5,
-	.act_pattern_id = 12,
+	.act_pattern_id = 14,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[77] = {
+	[83] = {
+	.act_hid = BNXT_ULP_ACT_HID_0519,
+	.act_pattern_id = 15,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[84] = {
 	.act_hid = BNXT_ULP_ACT_HID_0106,
-	.act_pattern_id = 13,
+	.act_pattern_id = 16,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[78] = {
+	[85] = {
 	.act_hid = BNXT_ULP_ACT_HID_05c2,
-	.act_pattern_id = 14,
+	.act_pattern_id = 17,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[79] = {
+	[86] = {
 	.act_hid = BNXT_ULP_ACT_HID_011b,
-	.act_pattern_id = 15,
+	.act_pattern_id = 18,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[80] = {
+	[87] = {
 	.act_hid = BNXT_ULP_ACT_HID_0471,
-	.act_pattern_id = 16,
+	.act_pattern_id = 19,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[81] = {
+	[88] = {
 	.act_hid = BNXT_ULP_ACT_HID_05d7,
-	.act_pattern_id = 17,
+	.act_pattern_id = 20,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[82] = {
+	[89] = {
+	.act_hid = BNXT_ULP_ACT_HID_051b,
+	.act_pattern_id = 21,
+	.app_sig = 0,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[90] = {
 	.act_hid = BNXT_ULP_ACT_HID_0108,
-	.act_pattern_id = 18,
+	.act_pattern_id = 22,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[83] = {
+	[91] = {
 	.act_hid = BNXT_ULP_ACT_HID_05c4,
-	.act_pattern_id = 19,
+	.act_pattern_id = 23,
 	.app_sig = 0,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |

@@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 5
 	},
-	[84] = {
+	[92] = {
 	.act_hid = BNXT_ULP_ACT_HID_00a2,
 	.act_pattern_id = 0,
 	.app_sig = 0,

@@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.act_tid = 6
 	},
-	[85] = {
+	[93] = {
 	.act_hid = BNXT_ULP_ACT_HID_00a4,
 	.act_pattern_id = 1,
 	.app_sig = 0,

index c016e1940a..fcd460e707 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Aug 20 17:59:14 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_

@@ -20,7 +20,7 @@
 #define BNXT_ULP_CLASS_HID_SHFTL 28
 #define BNXT_ULP_CLASS_HID_MASK 65535
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
 #define BNXT_ULP_ACT_HID_SHFTR 27

@@ -29,7 +29,7 @@
 #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277
 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
 #define BNXT_ULP_COND_GOTO_REJECT 1023
 #define BNXT_ULP_COND_GOTO_RF 0x10000

@@ -50,11 +50,11 @@
 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
 #define ULP_THOR_CLASS_COND_LIST_SIZE 55
 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7
 #define ULP_THOR_ACT_TBL_LIST_SIZE 36
 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16

@@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_04bc = 0x04bc,
 	BNXT_ULP_ACT_HID_00a9 = 0x00a9,
 	BNXT_ULP_ACT_HID_020f = 0x020f,
+	BNXT_ULP_ACT_HID_0153 = 0x0153,
 	BNXT_ULP_ACT_HID_04a9 = 0x04a9,
 	BNXT_ULP_ACT_HID_01fc = 0x01fc,
 	BNXT_ULP_ACT_HID_04be = 0x04be,
 	BNXT_ULP_ACT_HID_00ab = 0x00ab,
 	BNXT_ULP_ACT_HID_0211 = 0x0211,
+	BNXT_ULP_ACT_HID_0155 = 0x0155,
 	BNXT_ULP_ACT_HID_04ab = 0x04ab,
 	BNXT_ULP_ACT_HID_01fe = 0x01fe,
 	BNXT_ULP_ACT_HID_0667 = 0x0667,
 	BNXT_ULP_ACT_HID_0254 = 0x0254,
 	BNXT_ULP_ACT_HID_03ba = 0x03ba,
+	BNXT_ULP_ACT_HID_02fe = 0x02fe,
 	BNXT_ULP_ACT_HID_0654 = 0x0654,
 	BNXT_ULP_ACT_HID_03a7 = 0x03a7,
 	BNXT_ULP_ACT_HID_0669 = 0x0669,
 	BNXT_ULP_ACT_HID_0256 = 0x0256,
 	BNXT_ULP_ACT_HID_03bc = 0x03bc,
+	BNXT_ULP_ACT_HID_0300 = 0x0300,
 	BNXT_ULP_ACT_HID_0656 = 0x0656,
 	BNXT_ULP_ACT_HID_03a9 = 0x03a9,
 	BNXT_ULP_ACT_HID_021b = 0x021b,

@@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_06d7 = 0x06d7,
 	BNXT_ULP_ACT_HID_02c4 = 0x02c4,
 	BNXT_ULP_ACT_HID_042a = 0x042a,
+	BNXT_ULP_ACT_HID_036e = 0x036e,
 	BNXT_ULP_ACT_HID_06c4 = 0x06c4,
 	BNXT_ULP_ACT_HID_0417 = 0x0417,
 	BNXT_ULP_ACT_HID_06d9 = 0x06d9,
 	BNXT_ULP_ACT_HID_02c6 = 0x02c6,
 	BNXT_ULP_ACT_HID_042c = 0x042c,
+	BNXT_ULP_ACT_HID_0370 = 0x0370,
 	BNXT_ULP_ACT_HID_06c6 = 0x06c6,
 	BNXT_ULP_ACT_HID_0419 = 0x0419,
 	BNXT_ULP_ACT_HID_0119 = 0x0119,
 	BNXT_ULP_ACT_HID_046f = 0x046f,
 	BNXT_ULP_ACT_HID_05d5 = 0x05d5,
+	BNXT_ULP_ACT_HID_0519 = 0x0519,
 	BNXT_ULP_ACT_HID_0106 = 0x0106,
 	BNXT_ULP_ACT_HID_05c2 = 0x05c2,
 	BNXT_ULP_ACT_HID_011b = 0x011b,
 	BNXT_ULP_ACT_HID_0471 = 0x0471,
 	BNXT_ULP_ACT_HID_05d7 = 0x05d7,
+	BNXT_ULP_ACT_HID_051b = 0x051b,
 	BNXT_ULP_ACT_HID_0108 = 0x0108,
 	BNXT_ULP_ACT_HID_05c4 = 0x05c4,
 	BNXT_ULP_ACT_HID_00a2 = 0x00a2,

index 684fa66f48..84be09b368 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Aug 17 12:16:42 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.direction               = TF_DIR_RX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,
-	.count                   = 64
+	.count                   = 2048
 	},
 	{
 	.app_id                  = 0,

@@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.direction               = TF_DIR_TX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type           = TF_TBL_TYPE_ACT_ENCAP_64B,
-	.count                   = 64
+	.count                   = 2048
 	},
 	{
 	.app_id                  = 0,

@@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
 	.app_id                  = 0,
 	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
 	.direction               = TF_DIR_TX,
-	.resource_func           = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type           = TF_TBL_TYPE_ACT_MODIFY_64B,
-	.count                   = 32
-	},
-	{
-	.app_id                  = 0,
-	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
-	.direction               = TF_DIR_TX,
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type           = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.count                   = 272

index 68c1e292b2..95205a2421 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Aug 20 18:05:25 2021 */
+/* date: Wed Aug 25 16:41:37 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

293 lines not on this page · raw message

index 6743cf92b0..e3e38ffa19 100644
@@ -723,6 +723,9 @@ struct bnxt {
 	uint16_t		chip_num;
 #define CHIP_NUM_58818		0xd818
 #define BNXT_CHIP_SR2(bp)	((bp)->chip_num == CHIP_NUM_58818)
+#define	BNXT_FLAGS2_MULTIROOT_EN		BIT(4)
+#define	BNXT_MULTIROOT_EN(bp)			\
+	((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)
 
 	uint32_t		fw_cap;
 #define BNXT_FW_CAP_HOT_RESET		BIT(0)

index 181e607d7b..c7041143a3 100644
@@ -3394,6 +3394,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
 {
 	struct hwrm_func_qcfg_input req = {0};
 	struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
+	uint16_t flags;
 	int rc;
 
 	if (!BNXT_VF_IS_TRUSTED(bp))

@@ -3417,6 +3418,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
 	bp->parent->fid = rte_le_to_cpu_16(resp->fid);
 	bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
 
+	flags = rte_le_to_cpu_16(resp->flags);
+	/* check for the multi-root support */
+	if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
+		bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
+		PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
+	}
+
 	HWRM_UNLOCK();
 
 	return 0;

2,971 lines not on this page · raw message

index bd57229968..dbc8a3c5bb 100644

Lines of this file are not shown. View the raw message.

index 3c6e7fe924..84c83de35c 100644
@@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist,
 {
 	uint64_t bentry;
 	uint32_t idx = 0, jdx = 0;
+	uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES;
 
 	/* Iterate all numbers that have all 1's */
 	do {
 		bentry = blist->bdata[idx++];
-	} while (bentry == -1UL && idx < blist->bsize);
+	} while (bentry == -1UL && idx <= bsize_64);
 
-	if (idx < blist->bsize) {
+	if (idx <= bsize_64) {
 		if (bentry)
 			jdx = __builtin_clzl(~bentry);
 		*index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx;
 		ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx);
 		return 0;
 	}
-	jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE);
+	jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE);
 	BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx);
 	return -1;
 }

@@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist,
 				   uint32_t index)
 {
 	uint32_t idx = 0, jdx;
+	uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES;
 
 	idx = index / ULP_INDEX_BITMAP_SIZE;
-	if (idx >= blist->bsize) {
+	if (idx >= bsize_64) {
 		BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx,
 			    blist->bsize);
 		return -EINVAL;

@@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams,
 	hash_tbl->hash_mask = size - 1;
 
 	/* allocate the memory for the bit allocator */
-	size = (cparams->num_key_entries / sizeof(uint64_t)) + 1;
+	size = (cparams->num_key_entries / sizeof(uint64_t));
+	size = ULP_BYTE_ROUND_OFF_8(size);
 	hash_tbl->bit_list.bsize = size;
 	hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size,
 					       ULP_BUFFER_ALIGN_64_BYTE);

@@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl,
 		BNXT_TF_DBG(ERR, "Error in bit list alloc\n");
 		return -ENOMEM;
 	}
-
+	if (key_index > hash_tbl->num_key_entries) {
+		BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index,
+			    hash_tbl->num_key_entries);
+		ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index);
+		return -ENOMEM;
+	}
 	/* Update the hash entry */
 	ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index);
 

index 2a1e6ab97e..77981b5cdb 100644
@@ -1058,8 +1058,8 @@ struct hwrm_err_output {
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 2
 /* non-zero means beta version */
-#define HWRM_VERSION_RSVD 54
-#define HWRM_VERSION_STR "1.10.2.54"
+#define HWRM_VERSION_RSVD 55
+#define HWRM_VERSION_STR "1.10.2.55"
 
 /****************
  * hwrm_ver_get *

@@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input {
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates tx flow. */
-	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
 	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
 		HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
+	/*
+	 * When set use the special access register access to clear
+	 * the table entry on read.
+	 */
+	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \
+		UINT32_C(0x2)
 	/* unused. */
 	uint8_t	unused0[2];
 	/*

@@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input {
 	/* Control flags. */
 	uint16_t	flags;
 	/* Indicates the flow direction. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
+		UINT32_C(0x1)
 	/* If this bit set to 0, then it indicates rx flow. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
+		UINT32_C(0x0)
 	/* If this bit is set to 1, then it indicates tx flow. */
-	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
+		UINT32_C(0x1)
 	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
 		HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
+	/*
+	 * When set use the special access register access to clear
+	 * the table entries on read.
+	 */
+	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
+		UINT32_C(0x2)
 	/* unused. */
 	uint8_t	unused0[2];
 	/*

index 0fbb2fe837..ea6e2af7ce 100644
@@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 		     uint16_t hcapi_type,
 		     uint16_t size,
 		     uint8_t *data,
-		     uint32_t index)
+		     uint32_t index,
+		     bool clear_on_read)
 {
 	int rc;
 	struct hwrm_tf_tbl_type_get_input req = { 0 };

@@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 	uint8_t fw_session_id;
 	struct tf_dev_info *dev;
 	struct tf_session *tfs;
+	uint32_t flags = 0;
 
 	/* Retrieve the session information */
 	rc = tf_session_get_session_internal(tfp, &tfs);

@@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	flags = (dir == TF_DIR_TX ?
+		 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX :
+		 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX);
+
+	if (clear_on_read)
+		flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ;
 
 	/* Populate the request */
 	req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
-	req.flags = tfp_cpu_to_le_16(dir);
+	req.flags = tfp_cpu_to_le_16(flags);
 	req.type = tfp_cpu_to_le_32(hcapi_type);
 	req.index = tfp_cpu_to_le_32(index);
 

@@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			  uint32_t starting_idx,
 			  uint16_t num_entries,
 			  uint16_t entry_sz_in_bytes,
-			  uint64_t physical_mem_addr)
+			  uint64_t physical_mem_addr,
+			  bool clear_on_read)
 {
 	int rc;
 	struct tfp_send_msg_parms parms = { 0 };

@@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 	uint8_t fw_session_id;
 	struct tf_dev_info *dev;
 	struct tf_session *tfs;
+	uint32_t flags = 0;
 
 	/* Retrieve the session information */
 	rc = tf_session_get_session(tfp, &tfs);

@@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	flags = (dir == TF_DIR_TX ?
+		 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX :
+		 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX);
+
+	if (clear_on_read)
+		flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ;
 
 	/* Populate the request */
 	req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
-	req.flags = tfp_cpu_to_le_16(dir);
+	req.flags = tfp_cpu_to_le_16(flags);
 	req.type = tfp_cpu_to_le_32(hcapi_type);
 	req.start_index = tfp_cpu_to_le_32(starting_idx);
 	req.num_entries = tfp_cpu_to_le_32(num_entries);

index b26b15bfa3..718bc2f3b2 100644
@@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp,
 			 uint16_t hcapi_type,
 			 uint16_t size,
 			 uint8_t *data,
-			 uint32_t index);
+			 uint32_t index,
+			 bool clear_on_read);
 
 /* HWRM Tunneled messages */
 

@@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp,
 			      uint32_t starting_idx,
 			      uint16_t num_entries,
 			      uint16_t entry_sz_in_bytes,
-			      uint64_t physical_mem_addr);
+			      uint64_t physical_mem_addr,
+			      bool clear_on_read);
 
 /**
  * Sends Set message of a IF Table Type element to the firmware.

index 0a8720e7b6..12eca36491 100644
@@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp,
 				  hcapi_type,
 				  parms->data_sz_in_bytes,
 				  parms->data,
-				  parms->idx);
+				  parms->idx,
+				  false);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Get failed, type:%s, rc:%s\n",

@@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp,
 				       parms->starting_idx,
 				       parms->num_entries,
 				       parms->entry_sz_in_bytes,
-				       parms->physical_mem_addr);
+				       parms->physical_mem_addr,
+				       false);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Bulk get failed, type:%s, rc:%s\n",

index 636811bc2d..567f912dfa 100644
@@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp,
 	struct tf_tbl_sram_get_info_parms iparms = { 0 };
 	struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
 	void *sram_handle = NULL;
+	bool clear_on_read = false;
 
 	TF_CHECK_PARMS3(tfp, parms, parms->data);
 

@@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp,
 			    strerror(-rc));
 		return rc;
 	}
+	if (parms->type == TF_TBL_TYPE_ACT_STATS_64)
+		clear_on_read = true;
 
 	/* Get the entry */
 	rc = tf_msg_get_tbl_entry(tfp,

@@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp,
 				  hcapi_type,
 				  parms->data_sz_in_bytes,
 				  parms->data,
-				  parms->idx);
+				  parms->idx,
+				  clear_on_read);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Get failed, type:%s, rc:%s\n",

@@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 	struct tf_sram_mgr_is_allocated_parms aparms = { 0 };
 	bool allocated = false;
 	void *sram_handle = NULL;
+	bool clear_on_read = false;
 
 	TF_CHECK_PARMS2(tfp, parms);
 

@@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 		return rc;
 	}
 
+	if (parms->type == TF_TBL_TYPE_ACT_STATS_64)
+		clear_on_read = true;
+
 	/* Get the entries */
 	rc = tf_msg_bulk_get_tbl_entry(tfp,
 				       parms->dir,

@@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
 				       parms->starting_idx,
 				       parms->num_entries,
 				       parms->entry_sz_in_bytes,
-				       parms->physical_mem_addr);
+				       parms->physical_mem_addr,
+				       clear_on_read);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s, Bulk get failed, type:%s, rc:%s\n",

index dbc8a3c5bb..f1763e2519 100644
@@ -1483,7 +1483,8 @@ bnxt_ulp_port_init(struct bnxt *bp)
 		goto jump_to_error;
 	}
 
-	if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp))
+	/* set the accumulation of the stats */
+	if (BNXT_ACCUM_STATS_EN(bp))
 		bp->ulp_ctx->cfg_data->accum_stats = true;
 
 	BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n",

index e3e38ffa19..c65e360446 100644
@@ -1054,19 +1054,6 @@ int32_t
 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
 int32_t
 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
-void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
-			uint8_t *mac, uint8_t *parent_mac);
-uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
-struct bnxt *bnxt_get_bp(uint16_t port);
-uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
-		       enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type);
-uint16_t bnxt_get_phy_port_id(uint16_t port);
-uint16_t bnxt_get_vport(uint16_t port);
-enum bnxt_ulp_intf_type
-bnxt_get_interface_type(uint16_t port);
 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 
 void bnxt_cancel_fc_thread(struct bnxt *bp);

209 lines not on this page · raw message

index f1763e2519..2ac1a8625f 100644
@@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
 }
 
 int32_t
-bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
+bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
 			     uint8_t app_id, uint32_t dev_id)
 {
 	struct bnxt_ulp_app_capabilities_info *info;
 	uint32_t num = 0;
 	uint16_t i;
 	bool found = false;
+	struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
 
 	if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) {
 		BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",

@@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
 		if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY)
 			ulp_ctx->cfg_data->ulp_flags |=
 				BNXT_ULP_APP_UNICAST_ONLY;
+		if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) {
+			/* Enable socket direction only if MR is enabled in fw*/
+			if (BNXT_MULTIROOT_EN(bp))
+				ulp_ctx->cfg_data->ulp_flags |=
+					BNXT_ULP_APP_SOCKET_DIRECT;
+		}
 	}
 	if (!found) {
 		BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",

@@ -832,7 +839,7 @@ ulp_ctx_init(struct bnxt *bp,
 	}
 	BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id);
 
-	rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid);
+	rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n",
 			    bp->app_id, devid);

index 006df9cbc5..68f1470c61 100644
@@ -13,6 +13,7 @@
 #include "rte_version.h"
 #include "rte_ethdev.h"
 
+#include "bnxt.h"
 #include "ulp_template_db_enum.h"
 #include "ulp_tun.h"
 #include "bnxt_tf_common.h"

@@ -33,12 +34,15 @@
 #define BNXT_ULP_APP_DEV_UNSUPPORTED	0x4
 #define BNXT_ULP_HIGH_AVAIL_ENABLED	0x8
 #define BNXT_ULP_APP_UNICAST_ONLY	0x10
+#define BNXT_ULP_APP_SOCKET_DIRECT	0x20
+
 #define ULP_VF_REP_IS_ENABLED(flag)	((flag) & BNXT_ULP_VF_REP_ENABLED)
 #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\
 					     BNXT_ULP_SHARED_SESSION_ENABLED)
 #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag)	((flag) &\
 						 BNXT_ULP_APP_DEV_UNSUPPORTED)
 #define ULP_HIGH_AVAIL_IS_ENABLED(flag)	((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED)
+#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT)
 
 enum bnxt_ulp_flow_mem_type {
 	BNXT_ULP_FLOW_MEM_TYPE_INT = 0,

@@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info *
 bnxt_ulp_app_cap_list_get(uint32_t *num_entries);
 
 int32_t
-bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx,
+bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
 			     uint8_t app_id, uint32_t dev_id);
 
 struct bnxt_ulp_resource_resv_info *

index 2fec79a388..272195f6a2 100644
@@ -115,9 +115,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID,
 			    params->flow_sig_id);
 
+	if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags))
+		return;
+
 	/* update the WC Priority flag */
-	if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) &&
-	    ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) {
+	if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) {
 		enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW;
 		int32_t rc;
 

@@ -129,6 +131,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 					    BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG,
 					    1);
 	}
+
+	/* Update the socket direct flag */
+	if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags))
+		ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1);
 }
 
 /* Function to create the rte flow. */

index fcd460e707..31a94c14dc 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Aug 26 17:43:36 2021 */
+/* date: Thu Sep  9 11:11:05 2021 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_

@@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx {
 	BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71,
 	BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72,
 	BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
-	BNXT_ULP_CF_IDX_LAST = 74
+	BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74,
+	BNXT_ULP_CF_IDX_LAST = 75
 };
 
 enum bnxt_ulp_cond_list_opc {

@@ -582,7 +583,8 @@ enum bnxt_ulp_template_type {
 enum bnxt_ulp_app_cap {
 	BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001,
 	BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002,
-	BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004
+	BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004,
+	BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008
 };
 
 enum bnxt_ulp_fdb_resource_flags {

index 84be09b368..5383e2cd70 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Thu Aug 26 17:43:36 2021 */
+/* date: Thu Sep  9 11:11:05 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
 	.device_id               = BNXT_ULP_DEVICE_ID_THOR,
 	.flags                   = BNXT_ULP_APP_CAP_SHARED_EN |
 				   BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
-				   BNXT_ULP_APP_CAP_UNICAST_ONLY
+				   BNXT_ULP_APP_CAP_UNICAST_ONLY |
+				   BNXT_ULP_APP_CAP_SOCKET_DIRECT
 	},
 	{
 	.app_id                  = 2,

index ad3866243d..1d1e6463e0 100644
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Aug  6 11:15:47 2021 */
+/* date: Thu Sep 16 13:12:05 2021 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"

@@ -1016,7 +1016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_55dd,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 4096,
+	.flow_sig_id = 4096UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1031,7 +1031,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1df1,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 4104,
+	.flow_sig_id = 4104UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1047,7 +1047,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3e55,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 6144,
+	.flow_sig_id = 6144UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1063,7 +1063,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0649,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 6152,
+	.flow_sig_id = 6152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1080,7 +1080,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1011,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 16384,
+	.flow_sig_id = 16384UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1095,7 +1095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_40e9,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 16392,
+	.flow_sig_id = 16392UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1111,7 +1111,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3e99,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 24576,
+	.flow_sig_id = 24576UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1127,7 +1127,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_06ad,
 	.class_tid = 1,
 	.hdr_sig_id = 1,
-	.flow_sig_id = 24584,
+	.flow_sig_id = 24584UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1144,7 +1144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_38c7,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 32768,
+	.flow_sig_id = 32768UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1160,7 +1160,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_00fb,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 32776,
+	.flow_sig_id = 32776UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1177,7 +1177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_24d3,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 32832,
+	.flow_sig_id = 32832UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1194,7 +1194,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_559b,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 32840,
+	.flow_sig_id = 32840UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1212,7 +1212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5003,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 49152,
+	.flow_sig_id = 49152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1229,7 +1229,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1837,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 49160,
+	.flow_sig_id = 49160UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1247,7 +1247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3bef,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 49216,
+	.flow_sig_id = 49216UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1265,7 +1265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0403,
 	.class_tid = 1,
 	.hdr_sig_id = 2,
-	.flow_sig_id = 49224,
+	.flow_sig_id = 49224UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1284,7 +1284,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3d3f,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 131072,
+	.flow_sig_id = 131072UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1300,7 +1300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0543,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 131080,
+	.flow_sig_id = 131080UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1317,7 +1317,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_292b,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 131136,
+	.flow_sig_id = 131136UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1334,7 +1334,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_59e3,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 131144,
+	.flow_sig_id = 131144UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1352,7 +1352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5d3b,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 196608,
+	.flow_sig_id = 196608UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1369,7 +1369,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_254f,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 196616,
+	.flow_sig_id = 196616UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1387,7 +1387,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4917,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 196672,
+	.flow_sig_id = 196672UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1405,7 +1405,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_113b,
 	.class_tid = 1,
 	.hdr_sig_id = 3,
-	.flow_sig_id = 196680,
+	.flow_sig_id = 196680UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1424,7 +1424,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_55fd,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 4096,
+	.flow_sig_id = 4096UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1440,7 +1440,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1dd1,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 4104,
+	.flow_sig_id = 4104UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1457,7 +1457,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3e75,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 6144,
+	.flow_sig_id = 6144UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1474,7 +1474,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0669,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 6152,
+	.flow_sig_id = 6152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1492,7 +1492,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1ba1,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 12288,
+	.flow_sig_id = 12288UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1509,7 +1509,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4c69,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 12296,
+	.flow_sig_id = 12296UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1527,7 +1527,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0439,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 14336,
+	.flow_sig_id = 14336UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1545,7 +1545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_34e1,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 14344,
+	.flow_sig_id = 14344UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1564,7 +1564,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0465,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 20480,
+	.flow_sig_id = 20480UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1581,7 +1581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_352d,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 20488,
+	.flow_sig_id = 20488UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1599,7 +1599,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_55b1,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 22528,
+	.flow_sig_id = 22528UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1617,7 +1617,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1da5,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 22536,
+	.flow_sig_id = 22536UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1636,7 +1636,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_32fd,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 28672,
+	.flow_sig_id = 28672UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1654,7 +1654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_63a5,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 28680,
+	.flow_sig_id = 28680UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1673,7 +1673,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1b75,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 30720,
+	.flow_sig_id = 30720UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1692,7 +1692,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4c3d,
 	.class_tid = 1,
 	.hdr_sig_id = 4,
-	.flow_sig_id = 30728,
+	.flow_sig_id = 30728UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1712,7 +1712,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1031,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 16384,
+	.flow_sig_id = 16384UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1728,7 +1728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_40c9,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 16392,
+	.flow_sig_id = 16392UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1745,7 +1745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3eb9,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 24576,
+	.flow_sig_id = 24576UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1762,7 +1762,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_068d,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 24584,
+	.flow_sig_id = 24584UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1780,7 +1780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5039,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 49152,
+	.flow_sig_id = 49152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1797,7 +1797,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_180d,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 49160,
+	.flow_sig_id = 49160UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1815,7 +1815,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_15fd,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 57344,
+	.flow_sig_id = 57344UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1833,7 +1833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_46b5,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 57352,
+	.flow_sig_id = 57352UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1852,7 +1852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_303d,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 81920,
+	.flow_sig_id = 81920UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1869,7 +1869,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_60f5,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 81928,
+	.flow_sig_id = 81928UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1887,7 +1887,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5ea5,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 90112,
+	.flow_sig_id = 90112UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1905,7 +1905,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_2689,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 90120,
+	.flow_sig_id = 90120UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1924,7 +1924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0771,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 114688,
+	.flow_sig_id = 114688UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1942,7 +1942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3809,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 114696,
+	.flow_sig_id = 114696UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1961,7 +1961,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_35f9,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 122880,
+	.flow_sig_id = 122880UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -1980,7 +1980,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_66b1,
 	.class_tid = 1,
 	.hdr_sig_id = 5,
-	.flow_sig_id = 122888,
+	.flow_sig_id = 122888UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2000,7 +2000,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_559d,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 4096,
+	.flow_sig_id = 4096UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2016,7 +2016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1db1,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 4104,
+	.flow_sig_id = 4104UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2033,7 +2033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3e15,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 6144,
+	.flow_sig_id = 6144UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2050,7 +2050,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0609,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 6152,
+	.flow_sig_id = 6152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2068,7 +2068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1bc1,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 12288,
+	.flow_sig_id = 12288UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2085,7 +2085,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4c09,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 12296,
+	.flow_sig_id = 12296UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2103,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0459,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 14336,
+	.flow_sig_id = 14336UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2121,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3481,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 14344,
+	.flow_sig_id = 14344UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2140,7 +2140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0405,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 20480,
+	.flow_sig_id = 20480UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2157,7 +2157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_354d,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 20488,
+	.flow_sig_id = 20488UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2175,7 +2175,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_55d1,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 22528,
+	.flow_sig_id = 22528UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2193,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1dc5,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 22536,
+	.flow_sig_id = 22536UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2212,7 +2212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_329d,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 28672,
+	.flow_sig_id = 28672UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2230,7 +2230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_63c5,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 28680,
+	.flow_sig_id = 28680UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2249,7 +2249,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1b15,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 30720,
+	.flow_sig_id = 30720UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2268,7 +2268,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4c5d,
 	.class_tid = 1,
 	.hdr_sig_id = 6,
-	.flow_sig_id = 30728,
+	.flow_sig_id = 30728UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2288,7 +2288,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1051,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 16384,
+	.flow_sig_id = 16384UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2304,7 +2304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_40a9,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 16392,
+	.flow_sig_id = 16392UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2321,7 +2321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3ed9,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 24576,
+	.flow_sig_id = 24576UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2338,7 +2338,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_06ed,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 24584,
+	.flow_sig_id = 24584UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2356,7 +2356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5059,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 49152,
+	.flow_sig_id = 49152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2373,7 +2373,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_186d,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 49160,
+	.flow_sig_id = 49160UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2391,7 +2391,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_159d,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 57344,
+	.flow_sig_id = 57344UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2409,7 +2409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_46d5,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 57352,
+	.flow_sig_id = 57352UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2428,7 +2428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_305d,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 81920,
+	.flow_sig_id = 81920UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2445,7 +2445,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_6095,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 81928,
+	.flow_sig_id = 81928UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2463,7 +2463,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5ec5,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 90112,
+	.flow_sig_id = 90112UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2481,7 +2481,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_26e9,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 90120,
+	.flow_sig_id = 90120UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2500,7 +2500,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0711,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 114688,
+	.flow_sig_id = 114688UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2518,7 +2518,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3869,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 114696,
+	.flow_sig_id = 114696UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2537,7 +2537,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3599,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 122880,
+	.flow_sig_id = 122880UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2556,7 +2556,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_66d1,
 	.class_tid = 1,
 	.hdr_sig_id = 7,
-	.flow_sig_id = 122888,
+	.flow_sig_id = 122888UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2576,7 +2576,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_38e7,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 32768,
+	.flow_sig_id = 32768UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2593,7 +2593,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_00db,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 32776,
+	.flow_sig_id = 32776UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2611,7 +2611,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_24f3,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 32832,
+	.flow_sig_id = 32832UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2629,7 +2629,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_55bb,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 32840,
+	.flow_sig_id = 32840UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2648,7 +2648,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5023,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 49152,
+	.flow_sig_id = 49152UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2666,7 +2666,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1817,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 49160,
+	.flow_sig_id = 49160UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2685,7 +2685,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3bcf,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 49216,
+	.flow_sig_id = 49216UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2704,7 +2704,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0423,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 49224,
+	.flow_sig_id = 49224UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2724,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_58e3,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 98304,
+	.flow_sig_id = 98304UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2742,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_20d7,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 98312,
+	.flow_sig_id = 98312UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2761,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_448f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 98368,
+	.flow_sig_id = 98368UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2780,7 +2780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0ce3,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 98376,
+	.flow_sig_id = 98376UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2800,7 +2800,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_076b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 114688,
+	.flow_sig_id = 114688UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2819,7 +2819,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3813,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 114696,
+	.flow_sig_id = 114696UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2839,7 +2839,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5bcb,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 114752,
+	.flow_sig_id = 114752UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2859,7 +2859,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_243f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 114760,
+	.flow_sig_id = 114760UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2880,7 +2880,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_144b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 163840,
+	.flow_sig_id = 163840UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2898,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4573,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 163848,
+	.flow_sig_id = 163848UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2917,7 +2917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0057,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 163904,
+	.flow_sig_id = 163904UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2936,7 +2936,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_311f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 163912,
+	.flow_sig_id = 163912UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2956,7 +2956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_2b87,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 180224,
+	.flow_sig_id = 180224UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2975,7 +2975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_5c4f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 180232,
+	.flow_sig_id = 180232UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -2995,7 +2995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_1793,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 180288,
+	.flow_sig_id = 180288UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3015,7 +3015,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_485b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 180296,
+	.flow_sig_id = 180296UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3036,7 +3036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3447,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 229376,
+	.flow_sig_id = 229376UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3055,7 +3055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_650f,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 229384,
+	.flow_sig_id = 229384UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3075,7 +3075,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_2053,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 229440,
+	.flow_sig_id = 229440UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3095,7 +3095,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_511b,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 229448,
+	.flow_sig_id = 229448UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3116,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_4b83,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 245760,
+	.flow_sig_id = 245760UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3136,7 +3136,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_13f7,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 245768,
+	.flow_sig_id = 245768UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3157,7 +3157,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_37af,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 245824,
+	.flow_sig_id = 245824UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3178,7 +3178,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_6857,
 	.class_tid = 1,
 	.hdr_sig_id = 8,
-	.flow_sig_id = 245832,
+	.flow_sig_id = 245832UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3200,7 +3200,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_3d1f,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
-	.flow_sig_id = 131072,
+	.flow_sig_id = 131072UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3217,7 +3217,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0563,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
-	.flow_sig_id = 131080,
+	.flow_sig_id = 131080UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3235,7 +3235,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_290b,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
-	.flow_sig_id = 131136,
+	.flow_sig_id = 131136UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =

@@ -3253,7 +3253,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_hid = BNXT_ULP_CLASS_HID_59c3,
 	.class_tid = 1,
 	.hdr_sig_id = 9,
-	.flow_sig_id = 131144,
+	.flow_sig_id = 131144UL,
 	.flow_pattern_id = 0,
 	.app_sig = 0,
 	.hdr_sig = { .bits =