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drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers

PATCH Superseded Lyude Paul 3 participants 12 messages Oct 1, 2021 – Oct 7, 2021

Subsystems (6)

v2 of 5 Superseded Latest is v5 →

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Lyude Paul

author maintainer
#0 lore raw

v2 cover drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges.

So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well!

Changes:
* Fixup docs
* Add patch to stop us from breaking nouveau

Lyude Paul (4):
drm/i915: Add support for panels with VESA backlights with PWM
enable/disable
drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux
enable/brightness
drm/dp, drm/i915: Add support for VESA backlights using PWM for
brightness control
drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++------
 .../drm/i915/display/intel_dp_aux_backlight.c | 80 ++++++++++++++-----
 drivers/gpu/drm/nouveau/nouveau_backlight.c   |  5 +-
 include/drm/drm_dp_helper.h                   |  7 +-
 4 files changed, 122 insertions(+), 45 deletions(-)
Signature · 1 line
2.31.1
author maintainer
#1 lore raw

PATCH v2 1/4 drm/i915: Add support for panels with VESA backlights with PWM enable/disable

This simply adds proper support for panel backlights that can be controlled via VESA's backlight control protocol, but which also require that we enable and disable the backlight via PWM instead of via the DPCD interface. We also enable this by default, in order to fix some people's backlights that were broken by not having this enabled.

For reference, backlights that require this and use VESA's backlight interface tend to be laptops with hybrid GPUs, but this very well may change in the future.

Fixes fe7d52bccab6 ("drm/i915/dp: Don't use DPCD backlights that need PWM enable/disable")
Cc <[email protected]> # v5.12+
---
 .../drm/i915/display/intel_dp_aux_backlight.c | 24 ++++++++++++++-----
 1 file changed, 18 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +18 -6
index 569d17b4d00f..594fdc7453ca 100644
@@ -293,6 +293,10 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
 	struct intel_panel *panel = &connector->panel;
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
 
+	if (!panel->backlight.edp.vesa.info.aux_enable)
+		panel->backlight.pwm_funcs->enable(crtc_state, conn_state,
+						   panel->backlight.pwm_level_max);
+
 	drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
 }
 
@@ -304,6 +308,10 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
 	struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
 
 	drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
+
+	if (!panel->backlight.edp.vesa.info.aux_enable)
+		panel->backlight.pwm_funcs->disable(old_conn_state,
+						    intel_backlight_invert_pwm_level(connector, 0));
 }
 
 static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
@@ -321,6 +329,15 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
 	if (ret < 0)
 		return ret;
 
+	if (!panel->backlight.edp.vesa.info.aux_enable) {
+		ret = panel->backlight.pwm_funcs->setup(connector, pipe);
+		if (ret < 0) {
+			drm_err(&i915->drm,
+				"Failed to setup PWM backlight controls for eDP backlight: %d\n",
+				ret);
+			return ret;
+		}
+	}
 	panel->backlight.max = panel->backlight.edp.vesa.info.max;
 	panel->backlight.min = 0;
 	if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
@@ -340,12 +357,7 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
-	/* TODO: We currently only support AUX only backlight configurations, not backlights which
-	 * require a mix of PWM and AUX controls to work. In the mean time, these machines typically
-	 * work just fine using normal PWM controls anyway.
-	 */
-	if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
-	    drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
+	if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
 		drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
 		return true;
 	}
Signature · 1 line
2.31.1
author maintainer
#2 lore raw

PATCH v2 2/4 drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness

In reply to Lyude Paul

Since we don't support hybrid AUX/PWM backlights in nouveau right now, let's add some explicit checks so that we don't break nouveau once we enable support for these backlights in other drivers.

---
 drivers/gpu/drm/nouveau/nouveau_backlight.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/gpu/drm/nouveau/nouveau_backlight.c +4 -1
index 1cbd71abc80a..ae2f2abc8f5a 100644
@@ -308,7 +308,10 @@ nv50_backlight_init(struct nouveau_backlight *bl,
 		if (ret < 0)
 			return ret;
 
-		if (drm_edp_backlight_supported(edp_dpcd)) {
+		/* TODO: Add support for hybrid PWM/DPCD panels */
+		if (drm_edp_backlight_supported(edp_dpcd) &&
+		    (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+		    (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
 			NV_DEBUG(drm, "DPCD backlight controls supported on %s\n",
 				 nv_conn->base.name);
 
Signature · 1 line
2.31.1
author maintainer
#3 lore raw

PATCH v2 3/4 drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control

In reply to Lyude Paul

Now that we've added support to i915 for controlling panel backlights that need PWM to be enabled/disabled, let's finalize this and add support for controlling brightness levels via PWM as well. This should hopefully put us towards the path of supporting _ALL_ backlights via VESA's DPCD interface which would allow us to finally start trusting the DPCD again.

Note however that we still don't enable using this by default on i915 when it's not needed, primarily because I haven't yet had a chance to confirm if it's safe to do this on the one machine in Intel's CI that had an issue with this: samus-fi-bdw. I have done basic testing of this on other machines though, by manually patching i915 to force it into PWM-only mode on some of my laptops.

v2:
* Correct documentation (thanks Doug!)
* Get rid of backlight caps

Cc Rajeev Nandan <[email protected]>
Cc Doug Anderson <[email protected]>
Cc Satadru Pramanik <[email protected]>
---
 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++++------
 .../drm/i915/display/intel_dp_aux_backlight.c | 48 +++++++++---
 include/drm/drm_dp_helper.h                   |  7 +-
 3 files changed, 93 insertions(+), 37 deletions(-)
drivers/gpu/drm/drm_dp_helper.c +52 -23
index 4d0d1e8e51fa..f350e17a80e7 100644
@@ -3173,6 +3173,10 @@ int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_bac
 	int ret;
 	u8 buf[2] = { 0 };
 
+	/* The panel uses the PWM for controlling brightness levels */
+	if (!bl->aux_set)
+		return 0;
+
 	if (bl->lsb_reg_used) {
 		buf[0] = (level & 0xff00) >> 8;
 		buf[1] = (level & 0x00ff);
@@ -3199,7 +3203,7 @@ drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backli
 	int ret;
 	u8 buf;
 
-	/* The panel uses something other then DPCD for enabling its backlight */
+	/* This panel uses the EDP_BL_PWR GPIO for enablement */
 	if (!bl->aux_enable)
 		return 0;
 
@@ -3234,11 +3238,11 @@ drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backli
  * restoring any important backlight state such as the given backlight level, the brightness byte
  * count, backlight frequency, etc.
  *
- * Note that certain panels, while supporting brightness level controls over DPCD, may not support
- * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
- * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
- * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
- * implementation specific step for enabling the backlight after calling this function.
+ * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
+ * that the driver handle enabling/disabling the panel through implementation-specific means using
+ * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
+ * this function becomes a no-op, and the driver is expected to handle powering the panel on using
+ * the EDP_BL_PWR GPIO.
  *
  * Returns: %0 on success, negative error code on failure.
  */
@@ -3246,7 +3250,7 @@ int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backli
 			     const u16 level)
 {
 	int ret;
-	u8 dpcd_buf, new_dpcd_buf;
+	u8 dpcd_buf, new_dpcd_buf, new_mode;
 
 	ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
 	if (ret != 1) {
@@ -3256,10 +3260,14 @@ int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backli
 	}
 
 	new_dpcd_buf = dpcd_buf;
+	if (bl->aux_set)
+		new_mode = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+	else
+		new_mode = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
 
-	if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+	if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != new_mode) {
 		new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
-		new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+		new_dpcd_buf |= new_mode;
 
 		if (bl->pwmgen_bit_count) {
 			ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
@@ -3304,12 +3312,13 @@ EXPORT_SYMBOL(drm_edp_backlight_enable);
  * @aux: The DP AUX channel to use
  * @bl: Backlight capability info from drm_edp_backlight_init()
  *
- * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
- * panels have backlights that are enabled/disabled by other means, despite having their brightness
- * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
- * %false, this function will become a no-op (and we will skip updating
- * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
- * implementation specific step for disabling the backlight.
+ * This function handles disabling DPCD backlight controls on a panel over AUX.
+ *
+ * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
+ * that the driver handle enabling/disabling the panel through implementation-specific means using
+ * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
+ * this function becomes a no-op, and the driver is expected to handle powering the panel off using
+ * the EDP_BL_PWR GPIO.
  *
  * Returns: %0 on success or no-op, negative error code on failure.
  */
@@ -3333,6 +3342,9 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf
 	int ret;
 	u8 pn, pn_min, pn_max;
 
+	if (!bl->aux_set)
+		return 0;
+
 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
 	if (ret != 1) {
 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
@@ -3418,7 +3430,7 @@ drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_inf
 }
 
 static inline int
-drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
 			      u8 *current_mode)
 {
 	int ret;
@@ -3433,6 +3445,9 @@ drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_i
 	}
 
 	*current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
+	if (!bl->aux_set)
+		return 0;
+
 	if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
 		int size = 1 + bl->lsb_reg_used;
 
@@ -3463,7 +3478,7 @@ drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_i
  * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
  * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
  * @edp_dpcd: A cached copy of the eDP DPCD
- * @current_level: Where to store the probed brightness level
+ * @current_level: Where to store the probed brightness level, if any
  * @current_mode: Where to store the currently set backlight control mode
  *
  * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
@@ -3483,24 +3498,38 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl
 
 	if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
 		bl->aux_enable = true;
+	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
+		bl->aux_set = true;
 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
 		bl->lsb_reg_used = true;
 
+	/* Sanity check caps */
+	if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
+		drm_dbg_kms(aux->drm_dev,
+			    "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
+			    aux->name);
+		return -EINVAL;
+	}
+
 	ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
 	if (ret < 0)
 		return ret;
 
-	ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
+	ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
 	if (ret < 0)
 		return ret;
 	*current_level = ret;
 
 	drm_dbg_kms(aux->drm_dev,
-		    "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
-		    aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
-	drm_dbg_kms(aux->drm_dev,
-		    "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
-		    aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
+		    "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
+		    aux->name, bl->aux_set, bl->aux_enable, *current_mode);
+	if (bl->aux_set) {
+		drm_dbg_kms(aux->drm_dev,
+			    "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
+			    aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
+			    bl->lsb_reg_used);
+	}
+
 	return 0;
 }
 EXPORT_SYMBOL(drm_edp_backlight_init);
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +37 -11

73 lines not on this page · raw message

include/drm/drm_dp_helper.h +4 -3
index b52df4db3e8f..c8898a3a0c27 100644
@@ -1851,7 +1851,7 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  *
  * Note that currently this function will return %false for panels which support various DPCD
  * backlight features but which require the brightness be set through PWM, and don't support setting
- * the brightness level via the DPCD. This is a TODO.
+ * the brightness level via the DPCD.
  *
  * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
  * otherwise
@@ -1859,8 +1859,7 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 static inline bool
 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
 {
-	return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
-		(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
+	return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
 }
 
 /*
@@ -2221,6 +2220,7 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
  * @max: The maximum backlight level that may be set
  * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
  * @aux_enable: Does the panel support the AUX enable cap?
+ * @aux_set: Does the panel support setting the brightness through AUX?
  *
  * This structure contains various data about an eDP backlight, which can be populated by using
  * drm_edp_backlight_init().
@@ -2232,6 +2232,7 @@ struct drm_edp_backlight_info {
 
 	bool lsb_reg_used : 1;
 	bool aux_enable : 1;
+	bool aux_set : 1;
 };
 
 int
Signature · 1 line
2.31.1
author maintainer
#4 lore raw

PATCH v2 4/4 drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

In reply to Lyude Paul

Hooray! We've managed to hit enough bugs upstream that I've been able to come up with a pretty solid explanation for how backlight controls are actually supposed to be detected and used these days. As well, having the rest of the PWM bits in VESA's backlight interface implemented seems to have fixed all of the problematic brightness controls laptop panels that we've hit so far.

So, let's actually document this instead of just calling the laptop panels liars. As well, I would like to formally apologize to all of the laptop panels I called liars. I'm sorry laptop panels, hopefully you can all forgive me and we can move past this~

---
 .../drm/i915/display/intel_dp_aux_backlight.c    | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +11 -5
index 91daf9ab50e8..04a52d6a74ed 100644
@@ -455,11 +455,17 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
 	}
 
 	/*
-	 * A lot of eDP panels in the wild will report supporting both the
-	 * Intel proprietary backlight control interface, and the VESA
-	 * backlight control interface. Many of these panels are liars though,
-	 * and will only work with the Intel interface. So, always probe for
-	 * that first.
+	 * Since Intel has their own backlight control interface, the majority of machines out there
+	 * using DPCD backlight controls with Intel GPUs will be using this interface as opposed to
+	 * the VESA interface. However, other GPUs (such as Nvidia's) will always use the VESA
+	 * interface. This means that there's quite a number of panels out there that will advertise
+	 * support for both interfaces, primarily systems with Intel/Nvidia hybrid GPU setups.
+	 *
+	 * There's a catch to this though: on many panels that advertise support for both
+	 * interfaces, the VESA backlight interface will stop working once we've programmed the
+	 * panel with Intel's OUI - which is also required for us to be able to detect Intel's
+	 * backlight interface at all. This means that the only sensible way for us to detect both
+	 * interfaces is to probe for Intel's first, and VESA's second.
 	 */
 	if (try_intel_interface && intel_dp_aux_supports_hdr_backlight(connector)) {
 		drm_dbg_kms(dev, "Using Intel proprietary eDP backlight controls\n");
Signature · 1 line
2.31.1
#5 lore raw

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)

In reply to Lyude Paul
== Series Details ==

== Series Details ==

Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)
URL : https://patchwork.freedesktop.org/series/95127/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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+ 
+ 
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #def
#6 lore raw

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)

In reply to Lyude Paul
== Series Details ==

== Series Details ==

Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)
URL : https://patchwork.freedesktop.org/series/95127/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10680 -> Patchwork_21227
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/index.html

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_21227:

### IGT changes ###

#### Suppressed ####

The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.

* igt@i915_selftest@live@coherency:
- {fi-jsl-1}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/fi-jsl-1/igt@i915_selftest@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-jsl-1/igt@i915_selftest@[email protected]

* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-jsl-1/igt@i915_selftest@live@gt_pm.html

Known issues
------------

Here are the changes found in Patchwork_21227 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#109315])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@amdgpu/[email protected]

* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([fdo#109315] / [i915#2575]) +16 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@amdgpu/[email protected]

* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1155])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-bsw-n3050/igt@[email protected]

* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-bsw-n3050: NOTRUN -> [SKIP][13] ([fdo#109271]) +41 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-bsw-n3050/igt@[email protected]

* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3301])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-tgl-1115g4/igt@[email protected]

#### Possible fixes ####

* igt@gem_exec_suspend@basic-s3:
- fi-bsw-n3050: [INCOMPLETE][16] ([i915#2369] / [i915#3159]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/fi-bsw-n3050/igt@[email protected]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-bsw-n3050/igt@[email protected]

* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-bsw-kefka: [FAIL][18] ([i915#2122]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/fi-bsw-kefka/igt@kms_flip@[email protected]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/fi-bsw-kefka/igt@kms_flip@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103

Participating hosts (33 -> 28)
------------------------------

Additional (1): fi-tgl-1115g4
Missing (6): bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 bat-jsl-2 bat-jsl-1

Build changes
-------------

* Linux: CI_DRM_10680 -> Patchwork_21227

CI-20190529: 20190529
CI_DRM_10680: a5be335f84415ea2d1898be94f5c9a338520aaf5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6228: 22643ce4014a0b2dc52ce7916b2f657e2a7757c3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21227: 399cb4cc48b50563d2349428185e386d38ee31e2 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

399cb4cc48b5 drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs() 2bb3c612d1a9 drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control 9804e2417648 drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness 783db91a05b4 drm/i915: Add support for panels with VESA backlights with PWM enable/disable

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/index.html

#7 lore raw

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)

In reply to Lyude Paul
== Series Details ==

== Series Details ==

Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev3)
URL : https://patchwork.freedesktop.org/series/95127/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10680_full -> Patchwork_21227_full
====================================================

Summary
-------

**SUCCESS**

No regressions found.

Known issues
------------

Here are the changes found in Patchwork_21227_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#180]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl6/igt@gem_ctx_isolation@[email protected]

* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][2] ([i915#2846])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk7/igt@gem_exec_fair@[email protected]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk9/igt@gem_exec_fair@[email protected]

* igt@gem_exec_params@no-bsd:
- shard-iclb: NOTRUN -> [SKIP][5] ([fdo#109283])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#118] / [i915#95])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk7/igt@[email protected]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk7/igt@[email protected]

* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk8/igt@[email protected]

* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#3323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl3/igt@[email protected]

* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][10] ([i915#3318])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl8/igt@[email protected]

* igt@gem_workarounds@suspend-resume:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#456]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-tglb8/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb7/igt@[email protected]

* igt@gen7_exec_parse@load-register-reg:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109289])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@gen9_exec_parse@bb-start-out:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#2856])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1937])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl3/igt@i915_pm_lpsp@[email protected]

* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: NOTRUN -> [WARN][16] ([i915#1804] / [i915#2684])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271]) +236 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl7/igt@[email protected]

* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl6/igt@[email protected]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]

* igt@kms_async_flips@alternate-sync-async-flip:
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2521])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-tglb8/igt@[email protected]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb7/igt@[email protected]

* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#110725] / [fdo#111614])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]

* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111615])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +14 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +7 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

* igt@kms_chamelium@dp-crc-multiple:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +18 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl8/igt@[email protected]

* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +10 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][32] ([i915#1319])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][33] ([i915#2105])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]
- shard-apl: NOTRUN -> [FAIL][34] ([i915#2105])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl7/igt@[email protected]

* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109278] / [fdo#109279])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@kms_cursor_crc@pipe-d-cursor-dpms:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@kms_cursor_crc@pipe-d-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3359])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][38] -> [FAIL][39] ([i915#2346])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl3/igt@[email protected]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl4/igt@[email protected]

* igt@kms_flip@2x-flip-vs-panning:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109274])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@[email protected]

* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl1/igt@kms_flip@[email protected]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl1/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#79])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl1/igt@kms_flip@[email protected]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl1/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][45] -> [INCOMPLETE][46] ([i915#198])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl8/igt@kms_flip@[email protected]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl5/igt@kms_flip@[email protected]

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#2587])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [PASS][48] -> [SKIP][49] ([i915#3701])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb3/igt@[email protected]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb2/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111825]) +3 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html

* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109280]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html

* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl9/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][53] -> [DMESG-WARN][54] ([i915#180]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl4/igt@[email protected]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl1/igt@[email protected]

* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#1188])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl9/igt@[email protected]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl7/igt@[email protected]

* igt@kms_panel_fitting@legacy:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271]) +116 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533]) +4 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl8/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl3/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][60] ([i915#265])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl3/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl7/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][62] ([i915#265])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl3/igt@[email protected]

* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#3536])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#2920])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658]) +6 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]

* igt@kms_psr@psr2_dpms:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109441])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@kms_psr@psr2_dpms.html

* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][68] -> [SKIP][69] ([fdo#109441])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html

* igt@kms_psr@psr2_primary_render:
- shard-tglb: NOTRUN -> [FAIL][70] ([i915#132] / [i915#3467])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@kms_psr@psr2_primary_render.html

* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][71] ([IGT#2])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl3/igt@kms_sysfs_edid_timing.html

* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: [PASS][72] -> [INCOMPLETE][73] ([i915#198] / [i915#2828])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl5/igt@[email protected]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl10/igt@[email protected]

* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109291])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb6/igt@prime_nv_api@i915_nv_import_vs_close.html

* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]

#### Possible fixes ####

* igt@gem_eio@in-flight-suspend:
- shard-glk: [DMESG-WARN][76] -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk8/igt@[email protected]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk8/igt@[email protected]

* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][78] ([i915#2846]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk9/igt@[email protected]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk3/igt@[email protected]

* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][80] ([i915#2842]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-tglb3/igt@gem_exec_fair@[email protected]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb7/igt@gem_exec_fair@[email protected]
- shard-apl: [SKIP][82] ([fdo#109271]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl2/igt@gem_exec_fair@[email protected]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl1/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [FAIL][84] ([i915#2842]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk6/igt@gem_exec_fair@[email protected]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk5/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl1/igt@gem_exec_fair@[email protected]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@gem_exec_fair@[email protected]

* igt@gem_exec_nop@basic-series:
- shard-glk: [DMESG-WARN][88] ([i915#118] / [i915#95]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk6/igt@[email protected]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk5/igt@[email protected]

* igt@i915_query@query-regions-garbage-items:
- shard-skl: [DMESG-WARN][90] ([i915#1982]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl8/igt@[email protected]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl5/igt@[email protected]

* igt@i915_suspend@forcewake:
- shard-tglb: [INCOMPLETE][92] ([i915#2411] / [i915#456]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-tglb7/igt@[email protected]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-tglb5/igt@[email protected]

* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl2/igt@[email protected]

* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][96] ([i915#180] / [i915#1982]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl7/igt@[email protected]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl6/igt@[email protected]
- shard-kbl: [INCOMPLETE][98] ([i915#155] / [i915#636]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl4/igt@[email protected]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl7/igt@[email protected]

* igt@kms_flip@2x-plain-flip-ts-check@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][100] ([i915#2122]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk1/igt@kms_flip@[email protected]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk3/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][102] ([i915#79]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl1/igt@kms_flip@[email protected]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl1/igt@kms_flip@[email protected]

* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][104] ([i915#2122]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl1/igt@kms_flip@[email protected]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl9/igt@kms_flip@[email protected]

* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][106] ([i915#1188]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-skl4/igt@[email protected]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-skl6/igt@[email protected]

* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl2/igt@[email protected]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl7/igt@[email protected]

#### Warnings ####

* igt@gem_exec_fair@basic-none@vcs0:
- shard-iclb: [FAIL][110] -> [FAIL][111] ([i915#2842])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb8/igt@gem_exec_fair@[email protected]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb3/igt@gem_exec_fair@[email protected]

* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][112] ([i915#2680]) -> [WARN][113] ([i915#2684])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb3/igt@[email protected]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb2/igt@[email protected]

* igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
- shard-glk: [DMESG-FAIL][114] ([i915#118] / [i915#1888] / [i915#95]) -> [FAIL][115] ([i915#1888] / [i915#3451])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-glk6/igt@[email protected]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-glk2/igt@[email protected]

* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][116] ([i915#658]) -> [SKIP][117] ([i915#2920]) +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb3/igt@[email protected]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb2/igt@[email protected]

* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][118] ([i915#2920]) -> [SKIP][119] ([i915#658])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-iclb2/igt@[email protected]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-iclb5/igt@[email protected]

* igt@runner@aborted:
- shard-kbl: ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl1/igt@[email protected]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl3/igt@[email protected]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl1/igt@[email protected]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl7/igt@[email protected]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl6/igt@[email protected]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-kbl7/igt@[email protected]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl1/igt@[email protected]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl4/igt@[email protected]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl1/igt@[email protected]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl7/igt@[email protected]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl6/igt@[email protected]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl7/igt@[email protected]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl4/igt@[email protected]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl6/igt@[email protected]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl6/igt@[email protected]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-kbl4/igt@[email protected]
- shard-apl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#180] / [i915#3002] / [i915#3363])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl6/igt@[email protected]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl8/igt@[email protected]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl2/igt@[email protected]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl7/igt@[email protected]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl2/igt@[email protected]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl6/igt@[email protected]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10680/shard-apl1/igt@[email protected]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl1/igt@[email protected]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl6/igt@[email protected]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/shard-apl2/igt@[email protected]

[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freede

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21227/index.html

#8 lore raw
In reply to Lyude Paul

Hi Lyude,

Quoted 11 lines · Lyude Paul

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges.

Quoted 6 lines

So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well!

Backlight control is a topic which I'm reasonably familiar with, do you want me to review this series for you ?

Regards,

Hans

Quoted 20 lines

Changes:
* Fixup docs
* Add patch to stop us from breaking nouveau

Lyude Paul (4):
drm/i915: Add support for panels with VESA backlights with PWM
enable/disable
drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux
enable/brightness
drm/dp, drm/i915: Add support for VESA backlights using PWM for
brightness control
drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++------
 .../drm/i915/display/intel_dp_aux_backlight.c | 80 ++++++++++++++-----
 drivers/gpu/drm/nouveau/nouveau_backlight.c   |  5 +-
 include/drm/drm_dp_helper.h                   |  7 +-
 4 files changed, 122 insertions(+), 45 deletions(-)
author maintainer
#9 lore raw
Quoted 21 lines · Hans de Goede

Hi Lyude,

Quoted 11 lines · Lyude Paul

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges.

Quoted 6 lines

So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well!

Quoted 2 lines

Backlight control is a topic which I'm reasonably familiar with, do you want me to review this series for you ?

Possibly, although I definitely want to make sure that someone from Intel gets a chance to review this as well. I'm more curious if you might happen to have any systems that would be able to test this.

Quoted 28 lines

Regards,

Hans

Quoted 20 lines

Changes:
* Fixup docs
* Add patch to stop us from breaking nouveau

Lyude Paul (4):
  drm/i915: Add support for panels with VESA backlights with PWM enable/disable
  drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness
  drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control
  drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++------ .../drm/i915/display/intel_dp_aux_backlight.c | 80 ++++++++++++++----- drivers/gpu/drm/nouveau/nouveau_backlight.c   |  5 +- include/drm/drm_dp_helper.h                   |  7 +-

 4 files changed, 122 insertions(+), 45 deletions(-)
Signature · 3 lines
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat
Reviewed-by
#10 lore raw

Hi,

Quoted 22 lines · Lyude Paul
Quoted 21 lines · Hans de Goede

Hi Lyude,

Quoted 17 lines · Lyude Paul

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges.

So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well!

Quoted 5 lines
Quoted 2 lines

Backlight control is a topic which I'm reasonably familiar with, do you want me to review this series for you ?

Possibly, although I definitely want to make sure that someone from Intel gets a chance to review this as well.

I already expected you would also want someone from Intel to take a look as well :)

So to figure out if I have system to test this I ended up taking a close look at the code, which was a nice learning experience. Interesting how some panels use a combination of DCPD + pwm/gpio for enable/disable and/or pwm for brightness level control.

I wonder though what DCPD still does if pwm is used for both the enable/disable and brightness-level control ?

Since I was taking a close look already I decided to do turn this into a full, the entire set looks good to me:

Quoted 2 lines

I'm more curious if you might happen to have
any systems that would be able to test this.

I don't believe I have a system where I can test this, The only systems which I have which presumably (I did not check) use eDP / DCPD backlight control are boring ThinkPads with only i915 gfx.

Regards,

Hans

Quoted 21 lines
Quoted 20 lines
Quoted 19 lines

Changes:
* Fixup docs
* Add patch to stop us from breaking nouveau

Lyude Paul (4):
  drm/i915: Add support for panels with VESA backlights with PWM enable/disable
  drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness
  drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control
  drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++------ .../drm/i915/display/intel_dp_aux_backlight.c | 80 ++++++++++++++----- drivers/gpu/drm/nouveau/nouveau_backlight.c   |  5 +- include/drm/drm_dp_helper.h                   |  7 +-

 4 files changed, 122 insertions(+), 45 deletions(-)
Reviewed-by
#11 lore raw

Hi,

Quoted 45 lines · Hans de Goede

Hi,

Quoted 22 lines · Lyude Paul
Quoted 21 lines · Hans de Goede

Hi Lyude,

Quoted 17 lines · Lyude Paul

When I originally moved all of the VESA backlight code in i915 into DRM helpers, one of the things I didn't have the hardware or time for testing was machines that used a combination of PWM and DPCD in order to control their backlights. This has since then caused some breakages and resulted in us disabling DPCD backlight support on such machines. This works fine, unless you have a machine that actually needs this functionality for backlight controls to work at all. Additionally, we will need to support PWM for when we start adding support for VESA's product (as in the product of multiplication) control mode for better brightness ranges.

So - let's finally finish up implementing basic support for these types of backlights to solve these problems in our DP helpers, along with implementing support for this in i915. And since digging into this issue solved the last questions we really had about probing backlights in i915 for the most part, let's update some of the comments around that as well!

Quoted 5 lines
Quoted 2 lines

Backlight control is a topic which I'm reasonably familiar with, do you want me to review this series for you ?

Possibly, although I definitely want to make sure that someone from Intel gets a chance to review this as well.

I already expected you would also want someone from Intel to take a look as well :)

So to figure out if I have system to test this I ended up taking a close look at the code, which was a nice learning experience. Interesting how some panels use a combination of DCPD + pwm/gpio for enable/disable and/or pwm for brightness level control.

I wonder though what DCPD still does if pwm is used for both the enable/disable and brightness-level control ?

Since I was taking a close look already I decided to do turn this into a full, the entire set looks good to me:

Quoted 8 lines
Quoted 2 lines

I'm more curious if you might happen to have
any systems that would be able to test this.

I don't believe I have a system where I can test this, The only systems which I have which presumably (I did not check) use eDP / DCPD backlight control are boring ThinkPads with only i915 gfx.

Continuing with reading my email I see that you've also posted a v5 with 1 new patch:

[PATCH v3 3/5] drm/dp: Disable unsupported features in DP_EDP_BACKLIGHT_MODE_SET_REGISTER

That patch looks good to me too, so you may also add my:

To that one / to the entire v3 series.

Regards,

Hans

Quoted 21 lines
Quoted 21 lines
Quoted 20 lines
Quoted 19 lines

Changes:
* Fixup docs
* Add patch to stop us from breaking nouveau

Lyude Paul (4):
  drm/i915: Add support for panels with VESA backlights with PWM enable/disable
  drm/nouveau/kms/nv50-: Explicitly check DPCD backlights for aux enable/brightness
  drm/dp, drm/i915: Add support for VESA backlights using PWM for brightness control
  drm/i915: Clarify probing order in intel_dp_aux_init_backlight_funcs()

 drivers/gpu/drm/drm_dp_helper.c               | 75 +++++++++++------ .../drm/i915/display/intel_dp_aux_backlight.c | 80 ++++++++++++++----- drivers/gpu/drm/nouveau/nouveau_backlight.c   |  5 +- include/drm/drm_dp_helper.h                   |  7 +-

 4 files changed, 122 insertions(+), 45 deletions(-)