Add DT bindings and DT nodes for PCIe and PHY in SC7280
Subsystems (8)
v12 cover Add DT bindings and DT nodes for PCIe and PHY in SC7280
Changes added in v12:
* Sorted pipe_clk muxing changes in patch 4 & 5 as per the commit log. -Suggested by Bjorn.
Changes added in v11:
* Modified nvme_pwren name as nvme_pwren.
* Removed bias-pullup option in nvme_pwren entry [v11 Patch 3/5].
* Changed pcie1_default_state name to pcie1_clkreq_n.
* Added NULL pointer check for pcie_cfg.
Changes added in v10:
* v9 [Patch 4/4/] has been split into two separate patches
* Addressed all comments in IDP [Patch 3/4] file.
Changes added in v9:
* Added fixed regulator entry for nvme.suggested by Stephen Boyd
* Added NULL pointer check before accessing ops in pcie probe Suggested by Stephen Boyd
Changes added in v8:
* Added seperate pinctrl state for NVMe LDO enable pin [v8 P3/4]
* Removed pointer initialization for pcie_cfg [v8 P4/4]
* Replaced bool pcie_pipe_clk_src with unsigned int:1 [v8 P4/4]
* Changed gcc_pcie_1_pipe_clk_src to pipe_clk_src
Changes added in v7:
* Removed two fallbacks qcom,pcie-sm8250 and snps,dw-pcie.
* Replaced compatible method in get_resources_2_7_0 with flag approach suggested by Bjorn Helgaas .
* Setting gcc_pcie_1_clk_src as XO in init_2_7_0 for gdsc enable.
* Added specific NVMe GPIO entries for SKU1 and SKU2 support in idp.dts and idp2.dts respectively.
* Moved pcie_1 and pcie_1_phy board specific entries into common board file sc7280-idp.dtsi file.
Changes in v6:
* Removed platform check while setting gcc_pcie_1_pipe_clk_src as clk_set_parent will return 0 with nop if platform doesn't need to switch pipe clk source.
* Moved wake-n gpio to board specific file sc7280-idp.dtsi
* Sorted gpio.h header entry in sc7280.dtsi file
Changes in v5:
* Re ordered PCIe, PHY nodes in Soc and board specific dtsi files.
* Removed ref_clk entry in current patch [PATCH v4 P4/4].
* I will add ref clk entry in suspend/ resume commits.
* Added boolean flag in Soc specific dtsi file to differentiate SM8250 and SC7280 platforms. based on boolean flag, platforms will handle the pipe clk handling.
Changes in v4 as suggested by Bjorn:
* Changed pipe clk mux name as gcc_pcie_1_pipe_clk_src.
* Changed pipe_ext_src as phy_pipe_clk.
* Updated commit message for [PATCH v4 4/4].
Changes in v3:
* Changed pipe clock names in dt bindings as pipe_mux and phy_pipe.
* Moved reset and NVMe GPIO pin configs into board specific file.
* Updated pipe clk mux commit message.
Changes in v2:
* Moved pcie pin control settings into IDP file.
* Replaced pipe_clk_src with pipe_clk_mux in pcie driver
* Included pipe clk mux setting change set in this series
Prasad Malisetty (5):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Add a flag in match data along with ops
PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 95 +++++++++++++++-- 6 files changed, 285 insertions(+), 11 deletions(-)
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PATCH v12 1/5 dt-bindings: pci: qcom: Document PCIe bindings for SC7280
Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar to the one used on SM8250. Add the compatible for SC7280.
--- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
Documentation/devicetree/bindings/pci/qcom,pcie.txt +17 -0
@@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc7280" for sc7280 - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018
@@ -144,6 +145,22 @@ - "slave_bus" AXI Slave clock - clock-names: + Usage: required for sc7280 + Value type: <stringlist> + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_mux" PIPE MUX + - "phy_pipe" PIPE output clock + - "ref" REFERENCE clock + +- clock-names: Usage: required for sdm845 Value type: <stringlist> Definition: Should contain the following entries
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Re: [PATCH v12 1/5] dt-bindings: pci: qcom: Document PCIe bindings for SC7280
Quoting Prasad Malisetty (2021-10-07 10:48:39)
Quoted 7 lines
Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar to the one used on SM8250. Add the compatible for SC7280.
Signed-off-by Prasad Malisetty <[email protected]>Acked-by Rob Herring <[email protected]>Reviewed-by Stephen Boyd <[email protected]>---
I don't see this in linux-next still. Can it go through the pci tree?
PATCH v12 2/5 arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
In reply to Prasad MalisettyAdd PCIe controller and PHY nodes for sc7280 SOC.
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +118 -0
@@ -1563,6 +1563,117 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane 0>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>; + + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>; + + iommus = <&apps_smmu 0x1c80 0x1>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e200 { + reg = <0 0x01c0e200 0 0x170>, + <0 0x01c0e400 0 0x200>, + <0 0x01c0ea00 0 0x1f0>, + <0 0x01c0e600 0 0x170>, + <0 0x01c0e800 0 0x200>, + <0 0x01c0ee00 0 0xf4>; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + #clock-cells = <1>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sc7280-ipa";
@@ -2676,6 +2787,13 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + pcie1_clkreq_n: pcie1-clkreq-n { + pins = "gpio79"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk";
Signature · 2 lines
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Re: [PATCH v12 2/5] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
Quoted 38 lines · Prasad Malisetty
Add PCIe controller and PHY nodes for sc7280 SOC.
Signed-off-by Prasad Malisetty <[email protected]>Reviewed-by Stephen Boyd <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+)arch/arm64/boot/dts/qcom/sc7280.dtsi +22
-0@@ -1563,6 +1563,117 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi";
arch/arm64/boot/dts/qcom/sc7280.dtsi line 1597
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +10
-0+ #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane 0>,
This should be just <&pcie1_lane>, as the phy doesn't have clock cells.
Quoted 97 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +86
-0+ <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>; + + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>; + + iommus = <&apps_smmu 0x1c80 0x1>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e200 { + reg = <0 0x01c0e200 0 0x170>, + <0 0x01c0e400 0 0x200>, + <0 0x01c0ea00 0 0x1f0>, + <0 0x01c0e600 0 0x170>, + <0 0x01c0e800 0 0x200>, + <0 0x01c0ee00 0 0xf4>; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + #clock-cells = <1>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sc7280-ipa";@@ -2676,6 +2787,13 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + pcie1_clkreq_n: pcie1-clkreq-n { + pins = "gpio79"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk";
Signature · 2 lines
With best wishes Dmitry
PATCH v12 3/5 arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
In reply to Prasad MalisettyEnable PCIe controller and PHY for sc7280 IDP board. Add specific NVMe GPIO entries for SKU1 and SKU2 support.
--- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++ 3 files changed, 66 insertions(+)
arch/arm64/boot/dts/qcom/sc7280-idp.dts +8 -0
@@ -61,6 +61,14 @@ modem-init; }; +&nvme_pwren { + pins = "gpio19"; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>; +}; + &pmk8350_vadc { pmr735a_die_temp { reg = <PMR735A_ADC7_DIE_TEMP>;
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +50 -0
68 lines not on this page · raw message
arch/arm64/boot/dts/qcom/sc7280-idp2.dts +8 -0
@@ -21,3 +21,11 @@ stdout-path = "serial0:115200n8"; }; }; + +&nvme_pwren { + pins = "gpio51"; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +};
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v12 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
Quoting Prasad Malisetty (2021-10-07 10:48:41)
Quoted 5 lines
Enable PCIe controller and PHY for sc7280 IDP board. Add specific NVMe GPIO entries for SKU1 and SKU2 support.
Signed-off-by Prasad Malisetty <[email protected]>---
PATCH v12 4/5 PCI: qcom: Add a flag in match data along with ops
In reply to Prasad MalisettyAdd pipe_clk_need_muxing flag in match data and configure If the platform needs to switch pipe_clk_src.
--- drivers/pci/controller/dwc/pcie-qcom.c | 66 ++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 11 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +55 -11
@@ -189,6 +189,10 @@ struct qcom_pcie_ops {int (*config_sid)(struct qcom_pcie *pcie); }; +struct qcom_pcie_cfg { +const struct qcom_pcie_ops *ops; +}; +struct qcom_pcie {struct dw_pcie *pci;void __iomem *parf;/* DT parf */
@@ -1456,6 +1460,38 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .config_sid = qcom_pcie_config_sid_sm8250, }; +static const struct qcom_pcie_cfg apq8084_cfg = { + .ops = &ops_1_0_0, +}; + +static const struct qcom_pcie_cfg ipq8064_cfg = { + .ops = &ops_2_1_0, +}; + +static const struct qcom_pcie_cfg msm8996_cfg = { + .ops = &ops_2_3_2, +}; + +static const struct qcom_pcie_cfg ipq8074_cfg = { + .ops = &ops_2_3_3, +}; + +static const struct qcom_pcie_cfg ipq4019_cfg = { + .ops = &ops_2_4_0, +}; + +static const struct qcom_pcie_cfg sdm845_cfg = { + .ops = &ops_2_7_0, +}; + +static const struct qcom_pcie_cfg sm8250_cfg = { + .ops = &ops_1_9_0, +}; + +static const struct qcom_pcie_cfg sc7280_cfg = { + .ops = &ops_1_9_0, +}; +static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link,
@@ -1467,6 +1503,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)struct pcie_port *pp;struct dw_pcie *pci;struct qcom_pcie *pcie; +const struct qcom_pcie_cfg *pcie_cfg;int ret; pcie =devm_kzalloc (dev,sizeof (*pcie),GFP_KERNEL );
@@ -1488,7 +1525,13 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pci = pci; - pcie->ops =of_device_get_match_data (dev); + pcie_cfg =of_device_get_match_data (dev); +if (!pcie_cfg || !pcie_cfg->ops) { +dev_err (dev,"Invalid platform data\n" ); +return NULL ; + } + + pcie->ops = pcie_cfg->ops; pcie->reset =devm_gpiod_get_optional (dev,"perst" ,GPIOD_OUT_HIGH );if (IS_ERR (pcie->reset)) {
@@ -1545,16 +1588,17 @@ static int qcom_pcie_probe(struct platform_device *pdev) }static const struct of_device_id qcom_pcie_match[] = { - { .compatible ="qcom,pcie-apq8084" , .data = &ops_1_0_0 }, - { .compatible ="qcom,pcie-ipq8064" , .data = &ops_2_1_0 }, - { .compatible ="qcom,pcie-ipq8064-v2" , .data = &ops_2_1_0 }, - { .compatible ="qcom,pcie-apq8064" , .data = &ops_2_1_0 }, - { .compatible ="qcom,pcie-msm8996" , .data = &ops_2_3_2 }, - { .compatible ="qcom,pcie-ipq8074" , .data = &ops_2_3_3 }, - { .compatible ="qcom,pcie-ipq4019" , .data = &ops_2_4_0 }, - { .compatible ="qcom,pcie-qcs404" , .data = &ops_2_4_0 }, - { .compatible ="qcom,pcie-sdm845" , .data = &ops_2_7_0 }, - { .compatible ="qcom,pcie-sm8250" , .data = &ops_1_9_0 }, + { .compatible ="qcom,pcie-apq8084" , .data = &apq8084_cfg }, + { .compatible ="qcom,pcie-ipq8064" , .data = &ipq8064_cfg }, + { .compatible ="qcom,pcie-ipq8064-v2" , .data = &ipq8064_cfg }, + { .compatible ="qcom,pcie-apq8064" , .data = &ipq8064_cfg }, + { .compatible ="qcom,pcie-msm8996" , .data = &msm8996_cfg }, + { .compatible ="qcom,pcie-ipq8074" , .data = &ipq8074_cfg }, + { .compatible ="qcom,pcie-ipq4019" , .data = &ipq4019_cfg }, + { .compatible ="qcom,pcie-qcs404" , .data = &ipq4019_cfg }, + { .compatible ="qcom,pcie-sdm845" , .data = &sdm845_cfg }, + { .compatible ="qcom,pcie-sm8250" , .data = &sm8250_cfg }, + { .compatible ="qcom,pcie-sc7280" , .data = &sc7280_cfg }, { } };
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Re: [PATCH v12 4/5] PCI: qcom: Add a flag in match data along with ops
Quoting Prasad Malisetty (2021-10-07 10:48:42)
Quoted 1 line
Add
pipe_clk_need_muxingflag in match data and configure
This commit text isn't accurate. The flag isn't added in this patch anymore. Same goes for the commit title/subject. Can you please update it to say something like "Point match data to config struct"?
Quoted 4 lines
If the platform needs to switch
pipe_clk_src.Signed-off-by Prasad Malisetty <[email protected]>---
Otherwise code looks fine:
Re: [PATCH v12 4/5] PCI: qcom: Add a flag in match data along with ops
Quoted 7 lines · Stephen Boyd
Quoting Prasad Malisetty (2021-10-07 10:48:42)
Quoted 1 line
Add
pipe_clk_need_muxingflag in match data and configureThis commit text isn't accurate. The flag isn't added in this patch anymore. Same goes for the commit title/subject. Can you please update it to say something like "Point match data to config struct"?
Hi Bjorn,
Could you please update below commit text while taking this patch.
"PCI: qcom: Replace ops with struct pcie_cfg in pcie match data.
Add struct qcom_pcie_cfg as match data for all platforms. Assign appropriate platform ops into qcom_pcie_cfg and read Using of_device_is_compatible in pcie probe. "
Thanks
-Prasad
Quoted 8 lines
Quoted 4 lines
If the platform needs to switch
pipe_clk_src.Signed-off-by Prasad Malisetty <[email protected]>---
Otherwise code looks fine:
Reviewed-by Stephen Boyd <[email protected]>
Re: [PATCH v12 4/5] PCI: qcom: Add a flag in match data along with ops
Quoted 10 lines · Prasad Malisetty
Quoted 7 lines · Stephen Boyd
Quoting Prasad Malisetty (2021-10-07 10:48:42)
Quoted 1 line
Add
pipe_clk_need_muxingflag in match data and configureThis commit text isn't accurate. The flag isn't added in this patch anymore. Same goes for the commit title/subject. Can you please update it to say something like "Point match data to config struct"?
Hi Bjorn,
Quoted 7 lines
Could you please update below commit text while taking this patch.
"PCI: qcom: Replace ops with struct
pcie_cfgin pcie match data.Add struct
qcom_pcie_cfgas match data for all platforms. Assign appropriate platform ops intoqcom_pcie_cfgand read Usingof_device_is_compatiblein pcie probe. "
of_device_get_match_data() you mean ? I am confused, please let me know, I am applying patches 4-5.
Lorenzo
Quoted 12 lines
Thanks
-PrasadQuoted 8 lines
Quoted 4 lines
If the platform needs to switch
pipe_clk_src.Signed-off-by Prasad Malisetty <[email protected]>---
Otherwise code looks fine:
Reviewed-by Stephen Boyd <[email protected]>
Re: [PATCH v12 4/5] PCI: qcom: Add a flag in match data along with ops
Quoted 15 lines · Lorenzo Pieralisi
Quoted 14 lines · Prasad Malisetty
Quoted 7 lines · Stephen Boyd
Quoting Prasad Malisetty (2021-10-07 10:48:42)
Quoted 1 line
Add
pipe_clk_need_muxingflag in match data and configureThis commit text isn't accurate. The flag isn't added in this patch anymore. Same goes for the commit title/subject. Can you please update it to say something like "Point match data to config struct"?
Hi Bjorn,
Could you please update below commit text while taking this patch.
"PCI: qcom: Replace ops with struct
pcie_cfgin pcie match data.
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Add struct
qcom_pcie_cfgas match data for all platforms. Assign appropriate platform ops intoqcom_pcie_cfgand read Usingof_device_is_compatiblein pcie probe. "
of_device_get_match_data()you mean ? I am confused, please let me know, I am applying patches 4-5.Lorenzo
Quoted 1 line
Hi Lorenzo,
Sorry for the confusion. I was trying to add "of_device_get_match_data", you are right.
Quoted 11 lines
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Thanks
-PrasadQuoted 8 lines
Quoted 4 lines
If the platform needs to switch
pipe_clk_src.Signed-off-by Prasad Malisetty <[email protected]>---
Otherwise code looks fine:
Reviewed-by Stephen Boyd <[email protected]>
PATCH v12 5/5 PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
In reply to Prasad MalisettyOn the SC7280, the clock source for gcc_pcie_1_pipe_clk_src must be the TCXO while gdsc is enabled. After PHY init successful clock source should switch to pipe clock for gcc_pcie_1_pipe_clk_src.
--- drivers/pci/controller/dwc/pcie-qcom.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
drivers/pci/controller/dwc/pcie-qcom.c +29 -0
@@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {struct regulator_bulk_data supplies[2 ];struct reset_control *pci_reset;struct clk *pipe_clk; +struct clk *pipe_clk_src; +struct clk *phy_pipe_clk; +struct clk *ref_clk_src; };union qcom_pcie_resources {
@@ -191,6 +194,7 @@ struct qcom_pcie_ops {struct qcom_pcie_cfg {const struct qcom_pcie_ops *ops; +unsigned int pipe_clk_need_muxing:1 ; };struct qcom_pcie {
@@ -201,6 +205,7 @@ struct qcom_pcie {struct phy *phy;struct gpio_desc *reset;const struct qcom_pcie_ops *ops; + unsigned int pipe_clk_need_muxing:1; };#define to_qcom_pcie (x) dev_get_drvdata((x)->dev)
@@ -1171,6 +1176,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)if (ret <0 )return ret; +if (pcie->pipe_clk_need_muxing) { + res->pipe_clk_src =devm_clk_get (dev,"pipe_mux" ); +if (IS_ERR (res->pipe_clk_src)) +return PTR_ERR (res->pipe_clk_src); + + res->phy_pipe_clk =devm_clk_get (dev,"phy_pipe" ); +if (IS_ERR (res->phy_pipe_clk)) +return PTR_ERR (res->phy_pipe_clk); + + res->ref_clk_src =devm_clk_get (dev,"ref" ); +if (IS_ERR (res->ref_clk_src)) +return PTR_ERR (res->ref_clk_src); + } + res->pipe_clk =devm_clk_get (dev,"pipe" );return PTR_ERR_OR_ZERO (res->pipe_clk); }
@@ -1189,6 +1208,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)return ret; } +/* Set TCXO as clock source for pcie_pipe_clk_src */ +if (pcie->pipe_clk_need_muxing) +clk_set_parent (res->pipe_clk_src, res->ref_clk_src); + ret =clk_bulk_prepare_enable (res->num_clks, res->clks);if (ret <0 ) goto err_disable_regulators;
@@ -1260,6 +1283,10 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) {struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; +/* Set pipe clock as clock source for pcie_pipe_clk_src */ +if (pcie->pipe_clk_need_muxing) +clk_set_parent (res->pipe_clk_src, res->phy_pipe_clk); +return clk_prepare_enable (res->pipe_clk); }
@@ -1490,6 +1517,7 @@ static const struct qcom_pcie_cfg sm8250_cfg = {static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .pipe_clk_need_muxing = true, };static const struct dw_pcie_ops dw_pcie_ops = {
@@ -1532,6 +1560,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) } pcie->ops = pcie_cfg->ops; + pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; pcie->reset =devm_gpiod_get_optional (dev,"perst" ,GPIOD_OUT_HIGH );if (IS_ERR (pcie->reset)) {
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v12 5/5] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
Quoted 6 lines · Prasad Malisetty
On the SC7280, the clock source for
gcc_pcie_1_pipe_clk_srcmust be the TCXO while gdsc is enabled. After PHY init successful clock source should switch to pipe clock forgcc_pcie_1_pipe_clk_src.Signed-off-by Prasad Malisetty <[email protected]>Reviewed-by Stephen Boyd <[email protected]>
Thanks a lot for sorting out the patch 4/5 and 5/5 contents!
Quoted 97 lines
--- drivers/pci/controller/dwc/pcie-qcom.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)drivers/pci/controller/dwc/pcie-qcom.c +29
-0@@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {struct regulator_bulk_data supplies[2 ];struct reset_control *pci_reset;struct clk *pipe_clk; +struct clk *pipe_clk_src; +struct clk *phy_pipe_clk; +struct clk *ref_clk_src; };union qcom_pcie_resources {@@ -191,6 +194,7 @@ struct qcom_pcie_ops {struct qcom_pcie_cfg {const struct qcom_pcie_ops *ops; +unsigned int pipe_clk_need_muxing:1 ; };struct qcom_pcie {@@ -201,6 +205,7 @@ struct qcom_pcie {struct phy *phy;struct gpio_desc *reset;const struct qcom_pcie_ops *ops; + unsigned int pipe_clk_need_muxing:1; };#define to_qcom_pcie (x) dev_get_drvdata((x)->dev)@@ -1171,6 +1176,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)if (ret <0 )return ret; +if (pcie->pipe_clk_need_muxing) { + res->pipe_clk_src =devm_clk_get (dev,"pipe_mux" ); +if (IS_ERR (res->pipe_clk_src)) +return PTR_ERR (res->pipe_clk_src); + + res->phy_pipe_clk =devm_clk_get (dev,"phy_pipe" ); +if (IS_ERR (res->phy_pipe_clk)) +return PTR_ERR (res->phy_pipe_clk); + + res->ref_clk_src =devm_clk_get (dev,"ref" ); +if (IS_ERR (res->ref_clk_src)) +return PTR_ERR (res->ref_clk_src); + } + res->pipe_clk =devm_clk_get (dev,"pipe" );return PTR_ERR_OR_ZERO (res->pipe_clk); }@@ -1189,6 +1208,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)return ret; } +/* Set TCXO as clock source for pcie_pipe_clk_src */ +if (pcie->pipe_clk_need_muxing) +clk_set_parent (res->pipe_clk_src, res->ref_clk_src); + ret =clk_bulk_prepare_enable (res->num_clks, res->clks);if (ret <0 ) goto err_disable_regulators;@@ -1260,6 +1283,10 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) {struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; +/* Set pipe clock as clock source for pcie_pipe_clk_src */ +if (pcie->pipe_clk_need_muxing) +clk_set_parent (res->pipe_clk_src, res->phy_pipe_clk); +return clk_prepare_enable (res->pipe_clk); }@@ -1490,6 +1517,7 @@ static const struct qcom_pcie_cfg sm8250_cfg = {static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .pipe_clk_need_muxing = true, };static const struct dw_pcie_ops dw_pcie_ops = {@@ -1532,6 +1560,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) } pcie->ops = pcie_cfg->ops; + pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; pcie->reset =devm_gpiod_get_optional (dev,"perst" ,GPIOD_OUT_HIGH );if (IS_ERR (pcie->reset)) {Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Lorenzo Pieralisi
AppliedQuoted 81 lines · Prasad Malisetty
Changes added in v12:
* Sorted
pipe_clkmuxing changes in patch 4 & 5 as per the commit log. -Suggested by Bjorn.Changes added in v11:
* Modified
nvme_pwrenname asnvme_pwren.
* Removed bias-pullup option innvme_pwrenentry [v11 Patch 3/5].
* Changedpcie1_default_statename topcie1_clkreq_n.
* Added NULL pointer check forpcie_cfg.Changes added in v10:
* v9 [Patch 4/4/] has been split into two separate patches
* Addressed all comments in IDP [Patch 3/4] file.Changes added in v9:
* Added fixed regulator entry for nvme.suggested by Stephen Boyd
* Added NULL pointer check before accessing ops in pcie probe Suggested by Stephen BoydChanges added in v8:
* Added seperate pinctrl state for NVMe LDO enable pin [v8 P3/4]
* Removed pointer initialization forpcie_cfg[v8 P4/4]
* Replaced boolpcie_pipe_clk_srcwith unsigned int:1 [v8 P4/4]
* Changedgcc_pcie_1_pipe_clk_srctopipe_clk_srcChanges added in v7:
* Removed two fallbacks qcom,pcie-sm8250 and snps,dw-pcie.
* Replaced compatible method inget_resources_2_7_0with flag approach suggested by Bjorn Helgaas .
* Settinggcc_pcie_1_clk_srcas XO ininit_2_7_0for gdsc enable.
* Added specific NVMe GPIO entries for SKU1 and SKU2 support inidp.dtsandidp2.dtsrespectively.
* Movedpcie_1andpcie_1_phyboard specific entries into common board filesc7280-idp.dtsifile.Changes in v6:
* Removed platform check while setting
gcc_pcie_1_pipe_clk_srcasclk_set_parentwill return 0 with nop if platform doesn't need to switch pipe clk source.
* Moved wake-n gpio to board specific filesc7280-idp.dtsi
* Sortedgpio.hheader entry insc7280.dtsifileChanges in v5:
* Re ordered PCIe, PHY nodes in Soc and board specific dtsi files.
* Removedref_clkentry in current patch [PATCH v4 P4/4].
* I will add ref clk entry in suspend/ resume commits.
* Added boolean flag in Soc specific dtsi file to differentiate SM8250 and SC7280 platforms. based on boolean flag, platforms will handle the pipe clk handling.Changes in v4 as suggested by Bjorn:
* Changed pipe clk mux name as
gcc_pcie_1_pipe_clk_src.
* Changedpipe_ext_srcasphy_pipe_clk.
* Updated commit message for [PATCH v4 4/4].Changes in v3:
* Changed pipe clock names in dt bindings aspipe_muxandphy_pipe.
* Moved reset and NVMe GPIO pin configs into board specific file.
* Updated pipe clk mux commit message.Changes in v2:
* Moved pcie pin control settings into IDP file.
* Replacedpipe_clk_srcwithpipe_clk_muxin pcie driver
* Included pipe clk mux setting change set in this seriesPrasad Malisetty (5):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Add a flag in match data along with ops
PCI: qcom: Switchpcie_1_pipe_clk_srcafter PHY init in SC7280
Quoted 7 lines
.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 95 +++++++++++++++-- 6 files changed, 285 insertions(+), 11 deletions(-)
I applied patches [4-5] to pci/qcom for v5.16, thanks I expect other patches to go via the relevant trees.
Lorenzo
Quoted 99 lines · Lorenzo Pieralisi
Quoted 88 lines · Prasad Malisetty
Changes added in v12:
* Sorted
pipe_clkmuxing changes in patch 4 & 5 as per the commit
log.
-Suggested by Bjorn.Changes added in v11:
* Modified
nvme_pwrenname asnvme_pwren.
* Removed bias-pullup option innvme_pwrenentry [v11 Patch 3/5].
* Changedpcie1_default_statename topcie1_clkreq_n.
* Added NULL pointer check forpcie_cfg.Changes added in v10:
* v9 [Patch 4/4/] has been split into two separate patches
* Addressed all comments in IDP [Patch 3/4] file.Changes added in v9:
* Added fixed regulator entry for nvme.suggested by Stephen Boyd
* Added NULL pointer check before accessing ops in pcie probe Suggested by Stephen BoydChanges added in v8:
* Added seperate pinctrl state for NVMe LDO enable pin [v8 P3/4]
* Removed pointer initialization forpcie_cfg[v8 P4/4]
* Replaced boolpcie_pipe_clk_srcwith unsigned int:1 [v8 P4/4]
* Changedgcc_pcie_1_pipe_clk_srctopipe_clk_srcChanges added in v7:
* Removed two fallbacks qcom,pcie-sm8250 and snps,dw-pcie.
* Replaced compatible method inget_resources_2_7_0with flag approach suggested by Bjorn Helgaas .
* Settinggcc_pcie_1_clk_srcas XO ininit_2_7_0for gdsc enable.
* Added specific NVMe GPIO entries for SKU1 and SKU2 support inidp.dtsandidp2.dtsrespectively.
* Movedpcie_1andpcie_1_phyboard specific entries into
common
board filesc7280-idp.dtsifile.Changes in v6:
* Removed platform check while setting
gcc_pcie_1_pipe_clk_srcasclk_set_parentwill return 0 with nop if platform doesn't need to switch pipe clk source.
* Moved wake-n gpio to board specific filesc7280-idp.dtsi
* Sortedgpio.hheader entry insc7280.dtsifileChanges in v5:
* Re ordered PCIe, PHY nodes in Soc and board specific dtsi
files.
* Removedref_clkentry in current patch [PATCH v4 P4/4].
* I will add ref clk entry in suspend/ resume commits.
* Added boolean flag in Soc specific dtsi file to
differentiate
SM8250 and SC7280 platforms. based on boolean flag,
platforms will handle
the pipe clk handling.Changes in v4 as suggested by Bjorn:
* Changed pipe clk mux name as
gcc_pcie_1_pipe_clk_src.
* Changedpipe_ext_srcasphy_pipe_clk.
* Updated commit message for [PATCH v4 4/4].Changes in v3:
* Changed pipe clock names in dt bindings aspipe_muxandphy_pipe.
* Moved reset and NVMe GPIO pin configs into board specific
file.
* Updated pipe clk mux commit message.Changes in v2:
* Moved pcie pin control settings into IDP file.
* Replacedpipe_clk_srcwithpipe_clk_muxin pcie driver
* Included pipe clk mux setting change set in this seriesPrasad Malisetty (5):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Add a flag in match data along with ops
PCI: qcom: Switchpcie_1_pipe_clk_srcafter PHY init in SC7280Quoted 9 lines
.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 95 +++++++++++++++-- 6 files changed, 285 insertions(+), 11 deletions(-)
Quoted 4 lines
I applied patches [4-5] to pci/qcom for v5.16, thanks I expect other patches to go via the relevant trees.
Lorenzo
Thanks a lot Lorenzo for the update.
-Prasad
Quoting Lorenzo Pieralisi (2021-10-13 03:00:05)
Quoted 16 lines · Prasad Malisetty
Quoted 7 lines
Prasad Malisetty (5):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Add a flag in match data along with ops
PCI: qcom: Switchpcie_1_pipe_clk_srcafter PHY init in SC7280Quoted 7 lines
.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 95 +++++++++++++++-- 6 files changed, 285 insertions(+), 11 deletions(-)
Quoted 3 lines
I applied patches [4-5] to pci/qcom for v5.16, thanks I expect other patches to go via the relevant trees.
Lorenzo, can you pick up patch 1 too? It's the binding update for the compatible string used in patch 4-5.
Hi,
Quoted 18 lines · Stephen Boyd
Quoting Lorenzo Pieralisi (2021-10-13 03:00:05)
Quoted 16 lines · Prasad Malisetty
Quoted 14 lines
Prasad Malisetty (5):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Add a flag in match data along with ops
PCI: qcom: Switchpcie_1_pipe_clk_srcafter PHY init in SC7280.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 118 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 95 +++++++++++++++-- 6 files changed, 285 insertions(+), 11 deletions(-)
Quoted 6 lines
Quoted 3 lines
I applied patches [4-5] to pci/qcom for v5.16, thanks I expect other patches to go via the relevant trees.
Lorenzo, can you pick up patch 1 too? It's the binding update for the compatible string used in patch 4-5.
I think that means that patches 2-3 are ready to land in the Qualcomm tree assuming Bjorn Andersson is still accepting patches there for 5.16, right?
-Doug