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EDAC/synopsys: use the quirk for version instead of ddr version

PATCH In review Dinh Nguyen 2 participants 6 messages Oct 12, 2021 – Nov 20, 2021

Subsystems (4)
Device tree bindings Arm/Zynq architecture EDAC-core Memory controller drivers
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Dinh Nguyen

author
#0 lore raw

PATCH v4 1/4 EDAC/synopsys: use the quirk for version instead of ddr version

Version 2.40a supports DDR_ECC_INTR_SUPPORT for a quirk, so use that quirk to determine a call to setup_address_map().

Reviewed-by Michal Simek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v4: add Reviewed-by
v3: new patch

---
 drivers/edac/synopsys_edac.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/edac/synopsys_edac.c +1 -2
index 7e7146b22c16..bf237fccb444 100644
@@ -1352,8 +1352,7 @@ static int mc_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (of_device_is_compatible(pdev->dev.of_node,
-				    "xlnx,zynqmp-ddrc-2.40a"))
+	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
 		setup_address_map(priv);
 #endif
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH v4 2/4 EDAC/synopsys: add support for version 3 of the Synopsys EDAC DDR

Adds support for version 3.80a of the Synopsys DDR controller with EDAC. This version of the controller has the following differences:

- UE/CE are auto cleared
- Interrupts are supported by default

Reviewed-by Michal Simek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v4: Add Reviewed-by
v3: Address comments from Michal Simek
use bit macro
removed extra "cleared" word from comment section about v3.0
v2: remove "This patch" from commit message

---
 drivers/edac/synopsys_edac.c | 49 ++++++++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 7 deletions(-)
drivers/edac/synopsys_edac.c +42 -7
index bf237fccb444..66ee37ea0acc 100644
@@ -101,6 +101,7 @@
 /* DDR ECC Quirks */
 #define DDR_ECC_INTR_SUPPORT		BIT(0)
 #define DDR_ECC_DATA_POISON_SUPPORT	BIT(1)
+#define DDR_ECC_INTR_SELF_CLEAR		BIT(2)
 
 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
 /* ECC Configuration Registers */

@@ -171,6 +172,10 @@
 #define DDR_QOS_IRQ_EN_OFST		0x20208
 #define DDR_QOS_IRQ_DB_OFST		0x2020C
 
+/* DDR QOS Interrupt register definitions */
+#define DDR_UE_MASK			BIT(9)
+#define DDR_CE_MASK			BIT(8)
+
 /* ECC Corrected Error Register Mask and Shifts*/
 #define ECC_CEADDR0_RW_MASK		0x3FFFF
 #define ECC_CEADDR0_RNK_MASK		BIT(24)

@@ -533,10 +538,16 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
 	priv = mci->pvt_info;
 	p_data = priv->p_data;
 
-	regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
-	regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
-	if (!(regval & ECC_CE_UE_INTR_MASK))
-		return IRQ_NONE;
+	/*
+	 * v3.0 of the controller has the ce/ue bits cleared automatically,
+	 * so this condition does not apply.
+	 */
+	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
+		regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+		regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
+		if (!(regval & ECC_CE_UE_INTR_MASK))
+			return IRQ_NONE;
+	}
 
 	status = p_data->get_error_info(priv);
 	if (status)

@@ -548,7 +559,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
 
 	edac_dbg(3, "Total error count CE %d UE %d\n",
 		 priv->ce_cnt, priv->ue_cnt);
-	writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+	/* v3.0 of the controller does not have this register */
+	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
+		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
 	return IRQ_HANDLED;
 }
 

@@ -834,8 +847,13 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
 static void enable_intr(struct synps_edac_priv *priv)
 {
 	/* Enable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(DDR_UE_MASK | DDR_CE_MASK,
+		       priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
+
 }
 
 static void disable_intr(struct synps_edac_priv *priv)

@@ -890,6 +908,19 @@ static const struct synps_platform_data zynqmp_edac_def = {
 			  ),
 };
 
+static const struct synps_platform_data synopsys_edac_def = {
+	.get_error_info	= zynqmp_get_error_info,
+	.get_mtype	= zynqmp_get_mtype,
+	.get_dtype	= zynqmp_get_dtype,
+	.get_ecc_state	= zynqmp_get_ecc_state,
+	.quirks         = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR
+#ifdef CONFIG_EDAC_DEBUG
+			  | DDR_ECC_DATA_POISON_SUPPORT
+#endif
+			  ),
+};
+
+
 static const struct of_device_id synps_edac_match[] = {
 	{
 		.compatible = "xlnx,zynq-ddrc-a05",

@@ -899,6 +930,10 @@ static const struct of_device_id synps_edac_match[] = {
 		.compatible = "xlnx,zynqmp-ddrc-2.40a",
 		.data = (void *)&zynqmp_edac_def
 	},
+	{
+		.compatible = "snps,ddrc-3.80a",
+		.data = (void *)&synopsys_edac_def
+	},
 	{
 		/* end of table */
 	}
Signature · 1 line
2.25.1
author
#2 lore raw

PATCH v4 3/4 EDAC/synopsys: v3.80a of the synopsys edac contoller is also on the N5X

In reply to Dinh Nguyen

Intel's N5X platform is also using the Synopsys EDAC controller.

Acked-by Michal Simek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v4: Add Acked-by
v3: s/ARCH_N5X/ARCH_INTEL_SOCFPGA
v2: no changes

---
 drivers/edac/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/edac/Kconfig +1 -1
index 2fc4c3f91fd5..58ab63642e72 100644
@@ -484,7 +484,7 @@ config EDAC_ARMADA_XP
 
 config EDAC_SYNOPSYS
 	tristate "Synopsys DDR Memory Controller"
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA
 	help
 	  Support for error detection and correction on the Synopsys DDR
 	  memory controller.
Signature · 1 line
2.25.1
author
#3 lore raw

PATCH v4 4/4 dt-bindings: memory: add entry for version 3.80a

In reply to Dinh Nguyen

Add an entry for version 3.80a of the Synopsys DDR controller.

Acked-by Rob Herring <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>
---
 .../bindings/memory-controllers/synopsys,ddrc-ecc.yaml           | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml +1 -0
index a24588474625..fb7ae38a9c86 100644
@@ -26,6 +26,7 @@ properties:
     enum:
       - xlnx,zynq-ddrc-a05
       - xlnx,zynqmp-ddrc-2.40a
+      - snps,ddrc-3.80a
 
   interrupts:
     maxItems: 1
Signature · 1 line
2.25.1
author
#4 lore raw
In reply to Dinh Nguyen

Hi Boris,

can you please take this series through your tree?

Thanks,
Dinh

Quoted 27 lines · Dinh Nguyen

Version 2.40a supports DDR_ECC_INTR_SUPPORT for a quirk, so use that quirk to determine a call to setup_address_map().

Reviewed-by Michal Simek <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v4: add Reviewed-by
v3: new patch

---
  drivers/edac/synopsys_edac.c | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)
drivers/edac/synopsys_edac.c +1 -2
index 7e7146b22c16..bf237fccb444 100644
@@ -1352,8 +1352,7 @@ static int mc_probe(struct platform_device *pdev)
  		}
  	}
 
-	if (of_device_is_compatible(pdev->dev.of_node,
-				    "xlnx,zynqmp-ddrc-2.40a"))
+	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
  		setup_address_map(priv);
  #endif
maintainer
#5 lore raw
Quoted 3 lines · Dinh Nguyen

Hi Boris,

can you please take this series through your tree?

Sure, applied.

Thx.

Signature · 4 lines
Regards/Gruss,
    Boris.

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