clk: samsung: add common support for CPU clocks
Subsystems (3)
v4 cover clk: samsung: add common support for CPU clocks
These two patches were originally a part of the series [1]. They add support to the common samsung clock driver to parse and register the CPU clocks when provided. This allows for the samsung clock drivers to simply provide a struct samsung_cpu_clock to struct samsung_cmu_info and then call samsung_cmu_register_one(). With this new support, we can now get rid of the custom apollo and atlas CLK_OF_DECLARE init functions.
Since I don't have the hardware to test these, I'm including the RFT tag to try and get help testing and verifying these.
[1] https://lore.kernel.org/all/[email protected]/
Will McVicker (2):
[RFT] clk: samsung: add support for CPU clocks
[RFT] clk: samsung: exynos5433: update apollo and atlas clock probing
--
Changes in v4:
- Updated 'struct samsung_cpu_clock' to reference the parent and alt_parent hw clocks via ID instead of name
- Dropped __clk_lookup() in favor of ctx->clk_data.hw instead
Changes in v3:
- Same as v1-v2
- Tested-by: Marek Szyprowski <[email protected]>
drivers/clk/samsung/clk-cpu.c | 18 ++++ drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++---------------- drivers/clk/samsung/clk.c | 2 + drivers/clk/samsung/clk.h | 26 ++++++ 4 files changed, 94 insertions(+), 72 deletions(-)
Signature · 1 line
2.33.0.1079.g6e70778dc9-goog
PATCH v4 1/2 clk: samsung: add support for CPU clocks
Adds 'struct samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with the samsung_cmu_register_one() API.
Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom CLK_OF_DECLARE functions and directly call samsung_cmu_register_one().
Signed-off-by Will McVicker <[email protected]>
--- drivers/clk/samsung/clk-cpu.c | 18 ++++++++++++++++++ drivers/clk/samsung/clk.c | 2 ++ drivers/clk/samsung/clk.h | 26 ++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)
drivers/clk/samsung/clk-cpu.c +18 -0
@@ -469,3 +469,21 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,kfree (cpuclk);return ret; } + +void __init samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk) +{ +unsigned int idx; +unsigned int num_cfgs; +struct clk_hw **hws = ctx->clk_data.hws; + +for (idx =0 ; idx < nr_clk; idx++, list++) { +/* find count of configuration rates in cfg */ +for (num_cfgs =0 ; list->cfg[num_cfgs].prate !=0 ; ) + num_cfgs++; + +exynos_register_cpu_clock (ctx, list->id, list->name, hws[list->parent_id], + hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs, + list->flags); + } +}
drivers/clk/samsung/clk.c +2 -0
@@ -378,6 +378,8 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(samsung_clk_extended_sleep_init (reg_base, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); +if (cmu->cpu_clks) +samsung_clk_register_cpu (ctx, cmu->cpu_clks, cmu->nr_cpu_clks);samsung_clk_of_add_provider (np, ctx);
drivers/clk/samsung/clk.h +26 -0
@@ -271,6 +271,27 @@ struct samsung_pll_clock {__PLL (_typ, _id, _name, _pname,CLK_GET_RATE_NOCACHE , _lock, \ _con, _rtable) +struct samsung_cpu_clock { +unsigned int id; +const char *name; +unsigned int parent_id; +unsigned int alt_parent_id; +unsigned long flags; +int offset; +const struct exynos_cpuclk_cfg_data *cfg; +}; + +#define CPU_CLK (_id, _name, _pid, _apid, _flags, _offset, _cfg) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_id = _pid, \ + .alt_parent_id = _apid, \ + .flags = _flags, \ + .offset = _offset, \ + .cfg = _cfg, \ + } +struct samsung_clock_reg_cache {struct list_head node;void __iomem *reg_base;
@@ -301,6 +322,9 @@ struct samsung_cmu_info {unsigned int nr_fixed_factor_clks;/* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; +/* list of cpu clocks and respective count */ +const struct samsung_cpu_clock *cpu_clks; +unsigned int nr_cpu_clks;/* list and number of clocks registers */ const unsigned long *clk_regs;
@@ -350,6 +374,8 @@ extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,extern void __init samsung_clk_register_pll (struct samsung_clk_provider *ctx,const struct samsung_pll_clock *pll_list,unsigned int nr_clk,void __iomem *base); +extern void samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk); extern struct samsung_clk_provider __init *samsung_cmu_register_one( struct device_node *,
Signature · 1 line
2.33.0.1079.g6e70778dc9-goog
Re: [PATCH v4 1/2] [RFT] clk: samsung: add support for CPU clocks
Quoted 11 lines · Will McVicker
Adds 'struct
samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with thesamsung_cmu_register_one()API.Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom
CLK_OF_DECLAREfunctions and directly callsamsung_cmu_register_one().Signed-off-by Will McVicker <[email protected]>
Tested-by Marek Szyprowski <[email protected]>
Quoted 88 lines
--- drivers/clk/samsung/clk-cpu.c | 18 ++++++++++++++++++ drivers/clk/samsung/clk.c | 2 ++ drivers/clk/samsung/clk.h | 26 ++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)drivers/clk/samsung/clk-cpu.c +18
-0@@ -469,3 +469,21 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,kfree (cpuclk);return ret; } + +void __init samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk) +{ +unsigned int idx; +unsigned int num_cfgs; +struct clk_hw **hws = ctx->clk_data.hws; + +for (idx =0 ; idx < nr_clk; idx++, list++) { +/* find count of configuration rates in cfg */ +for (num_cfgs =0 ; list->cfg[num_cfgs].prate !=0 ; ) + num_cfgs++; + +exynos_register_cpu_clock (ctx, list->id, list->name, hws[list->parent_id], + hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs, + list->flags); + } +}drivers/clk/samsung/clk.c +2
-0@@ -378,6 +378,8 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(samsung_clk_extended_sleep_init (reg_base, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); +if (cmu->cpu_clks) +samsung_clk_register_cpu (ctx, cmu->cpu_clks, cmu->nr_cpu_clks);samsung_clk_of_add_provider (np, ctx);drivers/clk/samsung/clk.h +24
-0@@ -271,6 +271,27 @@ struct samsung_pll_clock {__PLL (_typ, _id, _name, _pname,CLK_GET_RATE_NOCACHE , _lock, \ _con, _rtable) +struct samsung_cpu_clock { +unsigned int id; +const char *name; +unsigned int parent_id; +unsigned int alt_parent_id; +unsigned long flags; +int offset; +const struct exynos_cpuclk_cfg_data *cfg; +}; + +#define CPU_CLK (_id, _name, _pid, _apid, _flags, _offset, _cfg) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_id = _pid, \ + .alt_parent_id = _apid, \ + .flags = _flags, \ + .offset = _offset, \ + .cfg = _cfg, \ + } +struct samsung_clock_reg_cache {struct list_head node;void __iomem *reg_base;@@ -301,6 +322,9 @@ struct samsung_cmu_info {unsigned int nr_fixed_factor_clks;/* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; +/* list of cpu clocks and respective count */ +const struct samsung_cpu_clock *cpu_clks; +unsigned int nr_cpu_clks;/* list and number of clocks registers */ const unsigned long *clk_regs;
drivers/clk/samsung/clk.h extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, · line 381
Quoted 8 lines
drivers/clk/samsung/clk.h +2
-0@@ -350,6 +374,8 @@ extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,extern void __init samsung_clk_register_pll (struct samsung_clk_provider *ctx,const struct samsung_pll_clock *pll_list,unsigned int nr_clk,void __iomem *base); +extern void samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk); extern struct samsung_clk_provider __init *samsung_cmu_register_one( struct device_node *,
Best regards
Signature · 2 lines
Marek Szyprowski, PhD Samsung R&D Institute Poland
Re: [PATCH v4 1/2] [RFT] clk: samsung: add support for CPU clocks
In reply to Will McVickerQuoted 10 lines · Will McVicker
Adds 'struct
samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with thesamsung_cmu_register_one()API.Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom
CLK_OF_DECLAREfunctions and directly callsamsung_cmu_register_one().
Quoted 7 lines
Signed-off-by Will McVicker <[email protected]>--- drivers/clk/samsung/clk-cpu.c | 18 ++++++++++++++++++ drivers/clk/samsung/clk.c | 2 ++ drivers/clk/samsung/clk.h | 26 ++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)
Best regards,
Krzysztof
Re: [PATCH v4 1/2] [RFT] clk: samsung: add support for CPU clocks
In reply to Will McVickerQuoted 11 lines · Will McVicker
Adds 'struct
samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with thesamsung_cmu_register_one()API.Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom
CLK_OF_DECLAREfunctions and directly callsamsung_cmu_register_one().Signed-off-by Will McVicker <[email protected]>
Patch applied, thank you.
Re: [PATCH v4 1/2] [RFT] clk: samsung: add support for CPU clocks
In reply to Will McVickerQuoted 100 lines · Will McVicker
Adds 'struct
samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with thesamsung_cmu_register_one()API.Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom
CLK_OF_DECLAREfunctions and directly callsamsung_cmu_register_one().Signed-off-by Will McVicker <[email protected]>--- drivers/clk/samsung/clk-cpu.c | 18 ++++++++++++++++++ drivers/clk/samsung/clk.c | 2 ++ drivers/clk/samsung/clk.h | 26 ++++++++++++++++++++++++++ 3 files changed, 46 insertions(+)drivers/clk/samsung/clk-cpu.c +18
-0@@ -469,3 +469,21 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,kfree (cpuclk);return ret; } + +void __init samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk) +{ +unsigned int idx; +unsigned int num_cfgs; +struct clk_hw **hws = ctx->clk_data.hws; + +for (idx =0 ; idx < nr_clk; idx++, list++) { +/* find count of configuration rates in cfg */ +for (num_cfgs =0 ; list->cfg[num_cfgs].prate !=0 ; ) + num_cfgs++; + +exynos_register_cpu_clock (ctx, list->id, list->name, hws[list->parent_id], + hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs, + list->flags); + } +}drivers/clk/samsung/clk.c +2
-0@@ -378,6 +378,8 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(samsung_clk_extended_sleep_init (reg_base, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); +if (cmu->cpu_clks) +samsung_clk_register_cpu (ctx, cmu->cpu_clks, cmu->nr_cpu_clks);samsung_clk_of_add_provider (np, ctx);drivers/clk/samsung/clk.h +24
-0@@ -271,6 +271,27 @@ struct samsung_pll_clock {__PLL (_typ, _id, _name, _pname,CLK_GET_RATE_NOCACHE , _lock, \ _con, _rtable) +struct samsung_cpu_clock { +unsigned int id; +const char *name; +unsigned int parent_id; +unsigned int alt_parent_id; +unsigned long flags; +int offset; +const struct exynos_cpuclk_cfg_data *cfg; +}; + +#define CPU_CLK (_id, _name, _pid, _apid, _flags, _offset, _cfg) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_id = _pid, \ + .alt_parent_id = _apid, \ + .flags = _flags, \ + .offset = _offset, \ + .cfg = _cfg, \ + } +struct samsung_clock_reg_cache {struct list_head node;void __iomem *reg_base;@@ -301,6 +322,9 @@ struct samsung_cmu_info {unsigned int nr_fixed_factor_clks;/* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; +/* list of cpu clocks and respective count */ +const struct samsung_cpu_clock *cpu_clks; +unsigned int nr_cpu_clks;/* list and number of clocks registers */ const unsigned long *clk_regs;
drivers/clk/samsung/clk.h extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, · line 381
Quoted 8 lines
drivers/clk/samsung/clk.h +2
-0@@ -350,6 +374,8 @@ extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,extern void __init samsung_clk_register_pll (struct samsung_clk_provider *ctx,const struct samsung_pll_clock *pll_list,unsigned int nr_clk,void __iomem *base); +extern void samsung_clk_register_cpu (struct samsung_clk_provider *ctx, +const struct samsung_cpu_clock *list,unsigned int nr_clk); extern struct samsung_clk_provider __init *samsung_cmu_register_one( struct device_node *,
Acked-by Chanwoo Choi <[email protected]>
Signature · 3 lines
Best Regards, Samsung Electronics Chanwoo Choi
PATCH v4 2/2 clk: samsung: exynos5433: update apollo and atlas clock probing
In reply to Will McVickerUse the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the samsung_cmu_register_one() instead.
Signed-off-by Will McVicker <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++---------------- 1 file changed, 48 insertions(+), 72 deletions(-)
drivers/clk/samsung/clk-exynos5433.c +48 -72
@@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 0 }, }; +static const struct samsung_cpu_clock apollo_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_APOLLO ,"apolloclk" ,CLK_MOUT_APOLLO_PLL , +CLK_MOUT_BUS_PLL_APOLLO_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_apolloclk_d), +}; + +static const struct samsung_cmu_info apollo_cmu_info__initconst = { + .pll_clks = apollo_pll_clks, + .nr_pll_clks =ARRAY_SIZE (apollo_pll_clks), + .mux_clks = apollo_mux_clks, + .nr_mux_clks =ARRAY_SIZE (apollo_mux_clks), + .div_clks = apollo_div_clks, + .nr_div_clks =ARRAY_SIZE (apollo_div_clks), + .gate_clks = apollo_gate_clks, + .nr_gate_clks =ARRAY_SIZE (apollo_gate_clks), + .cpu_clks = apollo_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (apollo_cpu_clks), + .nr_clk_ids =APOLLO_NR_CLK , + .clk_regs = apollo_clk_regs, + .nr_clk_regs =ARRAY_SIZE (apollo_clk_regs), +}; +static void __init exynos5433_cmu_apollo_init (struct device_node *np) { -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,APOLLO_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, apollo_pll_clks, -ARRAY_SIZE (apollo_pll_clks), reg_base); -samsung_clk_register_mux (ctx, apollo_mux_clks, -ARRAY_SIZE (apollo_mux_clks)); -samsung_clk_register_div (ctx, apollo_div_clks, -ARRAY_SIZE (apollo_div_clks)); -samsung_clk_register_gate (ctx, apollo_gate_clks, -ARRAY_SIZE (apollo_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_APOLLO ,"apolloclk" , - hws[CLK_MOUT_APOLLO_PLL ], hws[CLK_MOUT_BUS_PLL_APOLLO_USER ],0x200 , - exynos5433_apolloclk_d,ARRAY_SIZE (exynos5433_apolloclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); - -samsung_clk_sleep_init (reg_base, apollo_clk_regs, -ARRAY_SIZE (apollo_clk_regs)); - -samsung_clk_of_add_provider (np, ctx); +samsung_cmu_register_one (np, &apollo_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_apollo,"samsung,exynos5433-cmu-apollo" , exynos5433_cmu_apollo_init);
@@ -3932,44 +3920,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 0 }, }; -static void __init exynos5433_cmu_atlas_init (struct device_node *np) -{ -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,ATLAS_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, atlas_pll_clks, -ARRAY_SIZE (atlas_pll_clks), reg_base); -samsung_clk_register_mux (ctx, atlas_mux_clks, -ARRAY_SIZE (atlas_mux_clks)); -samsung_clk_register_div (ctx, atlas_div_clks, -ARRAY_SIZE (atlas_div_clks)); -samsung_clk_register_gate (ctx, atlas_gate_clks, -ARRAY_SIZE (atlas_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_ATLAS ,"atlasclk" , - hws[CLK_MOUT_ATLAS_PLL ], hws[CLK_MOUT_BUS_PLL_ATLAS_USER ],0x200 , - exynos5433_atlasclk_d,ARRAY_SIZE (exynos5433_atlasclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); +static const struct samsung_cpu_clock atlas_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_ATLAS ,"atlasclk" ,CLK_MOUT_ATLAS_PLL , +CLK_MOUT_BUS_PLL_ATLAS_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_atlasclk_d), +}; -samsung_clk_sleep_init (reg_base, atlas_clk_regs, -ARRAY_SIZE (atlas_clk_regs)); +static const struct samsung_cmu_info atlas_cmu_info__initconst = { + .pll_clks = atlas_pll_clks, + .nr_pll_clks =ARRAY_SIZE (atlas_pll_clks), + .mux_clks = atlas_mux_clks, + .nr_mux_clks =ARRAY_SIZE (atlas_mux_clks), + .div_clks = atlas_div_clks, + .nr_div_clks =ARRAY_SIZE (atlas_div_clks), + .gate_clks = atlas_gate_clks, + .nr_gate_clks =ARRAY_SIZE (atlas_gate_clks), + .cpu_clks = atlas_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (atlas_cpu_clks), + .nr_clk_ids =ATLAS_NR_CLK , + .clk_regs = atlas_clk_regs, + .nr_clk_regs =ARRAY_SIZE (atlas_clk_regs), +}; -samsung_clk_of_add_provider (np, ctx); +static void __init exynos5433_cmu_atlas_init (struct device_node *np) +{ +samsung_cmu_register_one (np, &atlas_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_atlas,"samsung,exynos5433-cmu-atlas" , exynos5433_cmu_atlas_init);
Signature · 1 line
2.33.0.1079.g6e70778dc9-goog
Re: [PATCH v4 2/2] [RFT] clk: samsung: exynos5433: update apollo and atlas clock probing
Quoted 5 lines · Will McVicker
Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the
samsung_cmu_register_one()instead.Signed-off-by Will McVicker <[email protected]>
Tested-by Marek Szyprowski <[email protected]>
Quoted 136 lines
--- drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++---------------- 1 file changed, 48 insertions(+), 72 deletions(-)drivers/clk/samsung/clk-exynos5433.c +43
-71@@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 0 }, }; +static const struct samsung_cpu_clock apollo_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_APOLLO ,"apolloclk" ,CLK_MOUT_APOLLO_PLL , +CLK_MOUT_BUS_PLL_APOLLO_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_apolloclk_d), +}; + +static const struct samsung_cmu_info apollo_cmu_info__initconst = { + .pll_clks = apollo_pll_clks, + .nr_pll_clks =ARRAY_SIZE (apollo_pll_clks), + .mux_clks = apollo_mux_clks, + .nr_mux_clks =ARRAY_SIZE (apollo_mux_clks), + .div_clks = apollo_div_clks, + .nr_div_clks =ARRAY_SIZE (apollo_div_clks), + .gate_clks = apollo_gate_clks, + .nr_gate_clks =ARRAY_SIZE (apollo_gate_clks), + .cpu_clks = apollo_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (apollo_cpu_clks), + .nr_clk_ids =APOLLO_NR_CLK , + .clk_regs = apollo_clk_regs, + .nr_clk_regs =ARRAY_SIZE (apollo_clk_regs), +}; +static void __init exynos5433_cmu_apollo_init (struct device_node *np) { -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,APOLLO_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, apollo_pll_clks, -ARRAY_SIZE (apollo_pll_clks), reg_base); -samsung_clk_register_mux (ctx, apollo_mux_clks, -ARRAY_SIZE (apollo_mux_clks)); -samsung_clk_register_div (ctx, apollo_div_clks, -ARRAY_SIZE (apollo_div_clks)); -samsung_clk_register_gate (ctx, apollo_gate_clks, -ARRAY_SIZE (apollo_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_APOLLO ,"apolloclk" , - hws[CLK_MOUT_APOLLO_PLL ], hws[CLK_MOUT_BUS_PLL_APOLLO_USER ],0x200 , - exynos5433_apolloclk_d,ARRAY_SIZE (exynos5433_apolloclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); - -samsung_clk_sleep_init (reg_base, apollo_clk_regs, -ARRAY_SIZE (apollo_clk_regs)); - -samsung_clk_of_add_provider (np, ctx); +samsung_cmu_register_one (np, &apollo_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_apollo,"samsung,exynos5433-cmu-apollo" , exynos5433_cmu_apollo_init);@@ -3932,44 +3920,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 0 }, }; -static void __init exynos5433_cmu_atlas_init (struct device_node *np) -{ -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,ATLAS_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, atlas_pll_clks, -ARRAY_SIZE (atlas_pll_clks), reg_base); -samsung_clk_register_mux (ctx, atlas_mux_clks, -ARRAY_SIZE (atlas_mux_clks)); -samsung_clk_register_div (ctx, atlas_div_clks, -ARRAY_SIZE (atlas_div_clks)); -samsung_clk_register_gate (ctx, atlas_gate_clks, -ARRAY_SIZE (atlas_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_ATLAS ,"atlasclk" , - hws[CLK_MOUT_ATLAS_PLL ], hws[CLK_MOUT_BUS_PLL_ATLAS_USER ],0x200 , - exynos5433_atlasclk_d,ARRAY_SIZE (exynos5433_atlasclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); +static const struct samsung_cpu_clock atlas_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_ATLAS ,"atlasclk" ,CLK_MOUT_ATLAS_PLL , +CLK_MOUT_BUS_PLL_ATLAS_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_atlasclk_d), +}; -samsung_clk_sleep_init (reg_base, atlas_clk_regs, -ARRAY_SIZE (atlas_clk_regs)); +static const struct samsung_cmu_info atlas_cmu_info__initconst = { + .pll_clks = atlas_pll_clks, + .nr_pll_clks =ARRAY_SIZE (atlas_pll_clks), + .mux_clks = atlas_mux_clks, + .nr_mux_clks =ARRAY_SIZE (atlas_mux_clks), + .div_clks = atlas_div_clks, + .nr_div_clks =ARRAY_SIZE (atlas_div_clks), + .gate_clks = atlas_gate_clks, + .nr_gate_clks =ARRAY_SIZE (atlas_gate_clks), + .cpu_clks = atlas_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (atlas_cpu_clks), + .nr_clk_ids =ATLAS_NR_CLK , + .clk_regs = atlas_clk_regs,
drivers/clk/samsung/clk-exynos5433.c static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = · line 3951
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +5
-1+ .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), +}; -samsung_clk_of_add_provider (np, ctx); +static void __init exynos5433_cmu_atlas_init (struct device_node *np) +{ +samsung_cmu_register_one (np, &atlas_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_atlas,"samsung,exynos5433-cmu-atlas" , exynos5433_cmu_atlas_init);
Best regards
Signature · 2 lines
Marek Szyprowski, PhD Samsung R&D Institute Poland
Re: [PATCH v4 2/2] [RFT] clk: samsung: exynos5433: update apollo and atlas clock probing
In reply to Will McVickerQuoted 14 lines · Will McVicker
Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the
samsung_cmu_register_one()instead.Signed-off-by Will McVicker <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++---------------- 1 file changed, 48 insertions(+), 72 deletions(-)drivers/clk/samsung/clk-exynos5433.c +0
-0
drivers/clk/samsung/clk-exynos5433.c static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst · line 3676
Quoted 2 lines
drivers/clk/samsung/clk-exynos5433.c +0
-0@@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 0 }, };
Best regards,
Krzysztof
Re: [PATCH v4 2/2] [RFT] clk: samsung: exynos5433: update apollo and atlas clock probing
In reply to Will McVickerQuoted 5 lines · Will McVicker
Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the
samsung_cmu_register_one()instead.Signed-off-by Will McVicker <[email protected]>
Patch applied, thank you.
Re: [PATCH v4 2/2] [RFT] clk: samsung: exynos5433: update apollo and atlas clock probing
In reply to Will McVickerQuoted 142 lines · Will McVicker
Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the
samsung_cmu_register_one()instead.Signed-off-by Will McVicker <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 120 +++++++++++---------------- 1 file changed, 48 insertions(+), 72 deletions(-)drivers/clk/samsung/clk-exynos5433.c +43
-71@@ -3675,44 +3675,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst { 0 }, }; +static const struct samsung_cpu_clock apollo_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_APOLLO ,"apolloclk" ,CLK_MOUT_APOLLO_PLL , +CLK_MOUT_BUS_PLL_APOLLO_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_apolloclk_d), +}; + +static const struct samsung_cmu_info apollo_cmu_info__initconst = { + .pll_clks = apollo_pll_clks, + .nr_pll_clks =ARRAY_SIZE (apollo_pll_clks), + .mux_clks = apollo_mux_clks, + .nr_mux_clks =ARRAY_SIZE (apollo_mux_clks), + .div_clks = apollo_div_clks, + .nr_div_clks =ARRAY_SIZE (apollo_div_clks), + .gate_clks = apollo_gate_clks, + .nr_gate_clks =ARRAY_SIZE (apollo_gate_clks), + .cpu_clks = apollo_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (apollo_cpu_clks), + .nr_clk_ids =APOLLO_NR_CLK , + .clk_regs = apollo_clk_regs, + .nr_clk_regs =ARRAY_SIZE (apollo_clk_regs), +}; +static void __init exynos5433_cmu_apollo_init (struct device_node *np) { -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,APOLLO_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, apollo_pll_clks, -ARRAY_SIZE (apollo_pll_clks), reg_base); -samsung_clk_register_mux (ctx, apollo_mux_clks, -ARRAY_SIZE (apollo_mux_clks)); -samsung_clk_register_div (ctx, apollo_div_clks, -ARRAY_SIZE (apollo_div_clks)); -samsung_clk_register_gate (ctx, apollo_gate_clks, -ARRAY_SIZE (apollo_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_APOLLO ,"apolloclk" , - hws[CLK_MOUT_APOLLO_PLL ], hws[CLK_MOUT_BUS_PLL_APOLLO_USER ],0x200 , - exynos5433_apolloclk_d,ARRAY_SIZE (exynos5433_apolloclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); - -samsung_clk_sleep_init (reg_base, apollo_clk_regs, -ARRAY_SIZE (apollo_clk_regs)); - -samsung_clk_of_add_provider (np, ctx); +samsung_cmu_register_one (np, &apollo_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_apollo,"samsung,exynos5433-cmu-apollo" , exynos5433_cmu_apollo_init);@@ -3932,44 +3920,32 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 0 }, }; -static void __init exynos5433_cmu_atlas_init (struct device_node *np) -{ -void __iomem *reg_base; -struct samsung_clk_provider *ctx; -struct clk_hw **hws; - - reg_base =of_iomap (np,0 ); -if (!reg_base) { -panic ("%s: failed to map registers\n" , __func__); -return ; - } - - ctx =samsung_clk_init (np, reg_base,ATLAS_NR_CLK ); -if (!ctx) { -panic ("%s: unable to allocate ctx\n" , __func__); -return ; - } - -samsung_clk_register_pll (ctx, atlas_pll_clks, -ARRAY_SIZE (atlas_pll_clks), reg_base); -samsung_clk_register_mux (ctx, atlas_mux_clks, -ARRAY_SIZE (atlas_mux_clks)); -samsung_clk_register_div (ctx, atlas_div_clks, -ARRAY_SIZE (atlas_div_clks)); -samsung_clk_register_gate (ctx, atlas_gate_clks, -ARRAY_SIZE (atlas_gate_clks)); - - hws = ctx->clk_data.hws; - -exynos_register_cpu_clock (ctx,CLK_SCLK_ATLAS ,"atlasclk" , - hws[CLK_MOUT_ATLAS_PLL ], hws[CLK_MOUT_BUS_PLL_ATLAS_USER ],0x200 , - exynos5433_atlasclk_d,ARRAY_SIZE (exynos5433_atlasclk_d), -CLK_CPU_HAS_E5433_REGS_LAYOUT ); +static const struct samsung_cpu_clock atlas_cpu_clks[]__initconst = { +CPU_CLK (CLK_SCLK_ATLAS ,"atlasclk" ,CLK_MOUT_ATLAS_PLL , +CLK_MOUT_BUS_PLL_ATLAS_USER , +CLK_CPU_HAS_E5433_REGS_LAYOUT ,0x200 , + exynos5433_atlasclk_d), +}; -samsung_clk_sleep_init (reg_base, atlas_clk_regs, -ARRAY_SIZE (atlas_clk_regs)); +static const struct samsung_cmu_info atlas_cmu_info__initconst = { + .pll_clks = atlas_pll_clks, + .nr_pll_clks =ARRAY_SIZE (atlas_pll_clks), + .mux_clks = atlas_mux_clks, + .nr_mux_clks =ARRAY_SIZE (atlas_mux_clks), + .div_clks = atlas_div_clks, + .nr_div_clks =ARRAY_SIZE (atlas_div_clks), + .gate_clks = atlas_gate_clks, + .nr_gate_clks =ARRAY_SIZE (atlas_gate_clks), + .cpu_clks = atlas_cpu_clks, + .nr_cpu_clks =ARRAY_SIZE (atlas_cpu_clks), + .nr_clk_ids =ATLAS_NR_CLK , + .clk_regs = atlas_clk_regs,
drivers/clk/samsung/clk-exynos5433.c static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = · line 3951
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +5
-1+ .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), +}; -samsung_clk_of_add_provider (np, ctx); +static void __init exynos5433_cmu_atlas_init (struct device_node *np) +{ +samsung_cmu_register_one (np, &atlas_cmu_info); }CLK_OF_DECLARE (exynos5433_cmu_atlas,"samsung,exynos5433-cmu-atlas" , exynos5433_cmu_atlas_init);
Looks good to me. Thanks for your work.
Acked-by Chanwoo Choi <[email protected]>
Signature · 3 lines
Best Regards, Samsung Electronics Chanwoo Choi