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arm64: dts: ti: k3-am642: Fix the L2 cache sets

PATCH Applied Nishanth Menon 3 participants 3 messages Nov 13, 2021 – Dec 6, 2021

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Device tree bindings Arm/Texas Instruments K3 architecture
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Nishanth Menon

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#0 lore raw

PATCH 1/1 arm64: dts: ti: k3-am642: Fix the L2 cache sets

A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure.

256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[2] https://www.ti.com/lit/pdf/spruim2

Fixes 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by Peng Fan <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/ti/k3-am642.dtsi +1 -1
index e2b397c88401..8a76f4821b11 100644
@@ -60,6 +60,6 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x40000>;
 		cache-line-size = <64>;
-		cache-sets = <512>;
+		cache-sets = <256>;
 	};
 };
Signature · 1 line
2.32.0
Reviewed-by on v1 1/1
#1 lore raw
Quoted 2 lines · Nishanth Menon

A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure.

This time the commit message is correct :-)

Reviewed-by Pratyush Yadav <[email protected]>
Quoted 28 lines

256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[2] https://www.ti.com/lit/pdf/spruim2

Fixes 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by Peng Fan <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/ti/k3-am642.dtsi +1 -1
index e2b397c88401..8a76f4821b11 100644
@@ -60,6 +60,6 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x40000>;
 		cache-line-size = <64>;
-		cache-sets = <512>;
+		cache-sets = <256>;
 	};
 };
Signature · 3 lines
Regards,
Pratyush Yadav
Texas Instruments Inc.
maintainer Applied
#2 lore raw
In reply to Nishanth Menon

Hi Nishanth Menon,

Quoted 9 lines · Nishanth Menon

A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure.

256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets

Fix the l2 cache-sets.

[...]

I have applied the following to branch ti-k3-dts-next on [1]. Thank you!

[1/1] arm64: dts: ti: k3-am642: Fix the L2 cache sets

      commit: a27a93bf70045be54b594fa8482959ffb84166d7

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh