Several fixes for event constraints on SKX and SNR platforms
Subsystems (2)
v2 cover Several fixes for event constraints on SKX and SNR platforms
From: Alexander Antonov <[email protected]>
Changes in this revision are:
v1 -> v2:
- Addressed comment from Peter Zijlstra:
- Fix coding style issue in skx_cha_hw_config()
This series contains the following fixes:
- Fix filter_tid mask for CHA events on Skylake Server
- Fix IIO event constraints for Skylake Server
- Fix IIO event constraints for Snowridge
Alexander Antonov (3):
Fix filter_tid mask for CHA events on Skylake Server Fix IIO event constraints for Skylake Server Fix IIO event constraints for Snowridge
arch/x86/events/intel/uncore_snbep.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
base-commit: 8ab774587903771821b59471cc723bba6d893942
Signature · 1 line
2.21.3
PATCH RESEND v2 1/3 Fix filter_tid mask for CHA events on Skylake Server
From: Alexander Antonov <[email protected]>
According Uncore Reference Manual: any of the CHA events may be filtered by Thread/Core-ID by using tid modifier in CHA Filter 0 Register. Update skx_cha_hw_config() to follow Uncore Guide.
--- arch/x86/events/intel/uncore_snbep.c | 3 +++ 1 file changed, 3 insertions(+)
arch/x86/events/intel/uncore_snbep.c +3 -0
@@ -3608,6 +3608,9 @@ static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *evstruct hw_perf_event_extra *reg1 = &event->hw.extra_reg;struct extra_reg *er;int idx =0 ; +/* Any of the CHA events may be filtered by Thread/Core-ID.*/ +if (event->hw.config &SNBEP_CBO_PMON_CTL_TID_EN ) + idx =SKX_CHA_MSR_PMON_BOX_FILTER_TID ;for (er = skx_uncore_cha_extra_regs; er->msr; er++) {if (er->event != (event->hw.config & er->config_mask))
Signature · 1 line
2.21.3
[tip: perf/urgent] perf/x86/intel/uncore: Fix filter_tid mask for CHA events on Skylake Server
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: e324234e0aa881b7841c7c713306403e12b069ff Gitweb: https://git.kernel.org/tip/e324234e0aa881b7841c7c713306403e12b069ff Author: Alexander Antonov <[email protected]> AuthorDate: Mon, 15 Nov 2021 12:03:32 +03:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Wed, 17 Nov 2021 14:48:43 +01:00
perf/x86/intel/uncore: Fix filter_tid mask for CHA events on Skylake Server
According Uncore Reference Manual: any of the CHA events may be filtered by Thread/Core-ID by using tid modifier in CHA Filter 0 Register. Update skx_cha_hw_config() to follow Uncore Guide.
--- arch/x86/events/intel/uncore_snbep.c | 3 +++ 1 file changed, 3 insertions(+)
arch/x86/events/intel/uncore_snbep.c +3 -0
@@ -3608,6 +3608,9 @@ static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *evstruct hw_perf_event_extra *reg1 = &event->hw.extra_reg;struct extra_reg *er;int idx =0 ; +/* Any of the CHA events may be filtered by Thread/Core-ID.*/ +if (event->hw.config &SNBEP_CBO_PMON_CTL_TID_EN ) + idx =SKX_CHA_MSR_PMON_BOX_FILTER_TID ;for (er = skx_uncore_cha_extra_regs; er->msr; er++) {if (er->event != (event->hw.config & er->config_mask))
PATCH RESEND v2 2/3 Fix IIO event constraints for Skylake Server
In reply to [email protected]From: Alexander Antonov <[email protected]>
According to the latest uncore document, COMP_BUF_OCCUPANCY (0xd5) event can be collected on 2-3 counters. Update uncore IIO event constraints for Skylake Server.
--- arch/x86/events/intel/uncore_snbep.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/uncore_snbep.c +1 -0
@@ -3678,6 +3678,7 @@ static struct event_constraint skx_uncore_iio_constraints[] = {UNCORE_EVENT_CONSTRAINT (0xc0 ,0xc ),UNCORE_EVENT_CONSTRAINT (0xc5 ,0xc ),UNCORE_EVENT_CONSTRAINT (0xd4 ,0xc ), +UNCORE_EVENT_CONSTRAINT (0xd5 ,0xc ), EVENT_CONSTRAINT_END };
Signature · 1 line
2.21.3
[tip: perf/urgent] perf/x86/intel/uncore: Fix IIO event constraints for Skylake Server
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 3866ae319c846a612109c008f43cba80b8c15e86 Gitweb: https://git.kernel.org/tip/3866ae319c846a612109c008f43cba80b8c15e86 Author: Alexander Antonov <[email protected]> AuthorDate: Mon, 15 Nov 2021 12:03:33 +03:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Wed, 17 Nov 2021 14:48:43 +01:00
perf/x86/intel/uncore: Fix IIO event constraints for Skylake Server
According to the latest uncore document, COMP_BUF_OCCUPANCY (0xd5) event can be collected on 2-3 counters. Update uncore IIO event constraints for Skylake Server.
--- arch/x86/events/intel/uncore_snbep.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/uncore_snbep.c +1 -0
@@ -3678,6 +3678,7 @@ static struct event_constraint skx_uncore_iio_constraints[] = {UNCORE_EVENT_CONSTRAINT (0xc0 ,0xc ),UNCORE_EVENT_CONSTRAINT (0xc5 ,0xc ),UNCORE_EVENT_CONSTRAINT (0xd4 ,0xc ), +UNCORE_EVENT_CONSTRAINT (0xd5 ,0xc ), EVENT_CONSTRAINT_END };
PATCH RESEND v2 3/3 Fix IIO event constraints for Snowridge
In reply to [email protected]From: Alexander Antonov <[email protected]>
According to the latest uncore document, DATA_REQ_OF_CPU (0x83), DATA_REQ_BY_CPU (0xc0) and COMP_BUF_OCCUPANCY (0xd5) events have constraints. Add uncore IIO constraints for Snowridge.
--- arch/x86/events/intel/uncore_snbep.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/x86/events/intel/uncore_snbep.c +8 -0
@@ -4529,6 +4529,13 @@ static void snr_iio_cleanup_mapping(struct intel_uncore_type *type)pmu_iio_cleanup_mapping (type, &snr_iio_mapping_group); } +static struct event_constraint snr_uncore_iio_constraints[] = { +UNCORE_EVENT_CONSTRAINT (0x83 ,0x3 ), +UNCORE_EVENT_CONSTRAINT (0xc0 ,0xc ), +UNCORE_EVENT_CONSTRAINT (0xd5 ,0xc ), +EVENT_CONSTRAINT_END +}; +static struct intel_uncore_type snr_uncore_iio = { .name ="iio" , .num_counters =4 ,
@@ -4540,6 +4547,7 @@ static struct intel_uncore_type snr_uncore_iio = { .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, .box_ctl = SNR_IIO_MSR_PMON_BOX_CTL, .msr_offset = SNR_IIO_MSR_OFFSET, + .constraints = snr_uncore_iio_constraints, .ops = &ivbep_uncore_msr_ops, .format_group = &snr_uncore_iio_format_group, .attr_update = snr_iio_attr_update,
Signature · 1 line
2.21.3
[tip: perf/urgent] perf/x86/intel/uncore: Fix IIO event constraints for Snowridge
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: bdc0feee05174418dec1fa68de2af19e1750b99f Gitweb: https://git.kernel.org/tip/bdc0feee05174418dec1fa68de2af19e1750b99f Author: Alexander Antonov <[email protected]> AuthorDate: Mon, 15 Nov 2021 12:03:34 +03:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Wed, 17 Nov 2021 14:48:43 +01:00
perf/x86/intel/uncore: Fix IIO event constraints for Snowridge
According to the latest uncore document, DATA_REQ_OF_CPU (0x83), DATA_REQ_BY_CPU (0xc0) and COMP_BUF_OCCUPANCY (0xd5) events have constraints. Add uncore IIO constraints for Snowridge.
--- arch/x86/events/intel/uncore_snbep.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/x86/events/intel/uncore_snbep.c +8 -0
@@ -4529,6 +4529,13 @@ static void snr_iio_cleanup_mapping(struct intel_uncore_type *type)pmu_iio_cleanup_mapping (type, &snr_iio_mapping_group); } +static struct event_constraint snr_uncore_iio_constraints[] = { +UNCORE_EVENT_CONSTRAINT (0x83 ,0x3 ), +UNCORE_EVENT_CONSTRAINT (0xc0 ,0xc ), +UNCORE_EVENT_CONSTRAINT (0xd5 ,0xc ), +EVENT_CONSTRAINT_END +}; +static struct intel_uncore_type snr_uncore_iio = { .name ="iio" , .num_counters =4 ,
@@ -4540,6 +4547,7 @@ static struct intel_uncore_type snr_uncore_iio = { .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, .box_ctl = SNR_IIO_MSR_PMON_BOX_CTL, .msr_offset = SNR_IIO_MSR_OFFSET, + .constraints = snr_uncore_iio_constraints, .ops = &ivbep_uncore_msr_ops, .format_group = &snr_uncore_iio_format_group, .attr_update = snr_iio_attr_update,