drivers/perf: CPU PMU driver for Apple M1

---
 Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
 1 file changed, 2 insertions(+)

Documentation/devicetree/bindings/arm/pmu.yaml +2 -0

index e17ac049e890..1a6986b4e552 100644
@@ -20,6 +20,8 @@ properties:
     items:
       - enum:
           - apm,potenza-pmu
+          - apple,firestorm-pmu
+          - apple,icestorm-pmu
           - arm,armv8-pmuv3 # Only for s/w models
           - arm,arm1136-pmu
           - arm,arm1176-pmu

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 1/8

2021-12-12 07:27 UTC #2 lore raw

Re: [PATCH v2 1/8] dt-bindings: arm-pmu: Document Apple PMU compatible strings

Quoted 15 lines · Marc Zyngier

As we are about to add support fur the Apple PMUs, document the compatible strings associated with the two micro-architectures present in the Apple M1.
Acked-by Rob Herring <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
  1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/arm/pmu.yaml +0 -0
index e17ac049e890..1a6986b4e552 100644

Documentation/devicetree/bindings/arm/pmu.yaml properties: · line 27

Quoted 8 lines

Documentation/devicetree/bindings/arm/pmu.yaml +2 -0

@@ -20,6 +20,8 @@ properties:
      items:
        - enum:
            - apm,potenza-pmu
+          - apple,firestorm-pmu
+          - apple,icestorm-pmu
            - arm,armv8-pmuv3 # Only for s/w models
            - arm,arm1136-pmu
            - arm,arm1176-pmu

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:49 UTC #3 lore raw

PATCH v2 2/8 dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts

Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC.

We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices.

Acked-by Rob Herring <[email protected]>

---
 .../devicetree/bindings/interrupt-controller/apple,aic.yaml     | 2 ++
 include/dt-bindings/interrupt-controller/apple-aic.h            | 2 ++
 2 files changed, 4 insertions(+)

Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +2 -0

index cf6c091a07b1..b95e41816953 100644
@@ -56,6 +56,8 @@ properties:
           - 1: virtual HV timer
           - 2: physical guest timer
           - 3: virtual guest timer
+          - 4: 'efficient' CPU PMU
+          - 5: 'performance' CPU PMU
 
       The 3rd cell contains the interrupt flags. This is normally
       IRQ_TYPE_LEVEL_HIGH (4).

include/dt-bindings/interrupt-controller/apple-aic.h +2 -0

index 604f2bb30ac0..bf3aac0e5491 100644
@@ -11,5 +11,7 @@
 #define AIC_TMR_HV_VIRT		1
 #define AIC_TMR_GUEST_PHYS	2
 #define AIC_TMR_GUEST_VIRT	3
+#define AIC_CPU_PMU_E		4
+#define AIC_CPU_PMU_P		5
 
 #endif

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 2/8

2021-12-12 07:27 UTC #4 lore raw

Re: [PATCH v2 2/8] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts

Quoted 33 lines · Marc Zyngier

Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC.
We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices.
Acked-by Rob Herring <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
  .../devicetree/bindings/interrupt-controller/apple,aic.yaml     | 2 ++
  include/dt-bindings/interrupt-controller/apple-aic.h            | 2 ++
  2 files changed, 4 insertions(+)
Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +2 -0
index cf6c091a07b1..b95e41816953 100644
@@ -56,6 +56,8 @@ properties:
            - 1: virtual HV timer
            - 2: physical guest timer
            - 3: virtual guest timer
+          - 4: 'efficient' CPU PMU
+          - 5: 'performance' CPU PMU
 
        The 3rd cell contains the interrupt flags. This is normally
        IRQ_TYPE_LEVEL_HIGH (4).
include/dt-bindings/interrupt-controller/apple-aic.h +0 -0
index 604f2bb30ac0..bf3aac0e5491 100644

include/dt-bindings/interrupt-controller/apple-aic.h line 17

Quoted 7 lines

include/dt-bindings/interrupt-controller/apple-aic.h +2 -0

@@ -11,5 +11,7 @@
  #define AIC_TMR_HV_VIRT		1
  #define AIC_TMR_GUEST_PHYS	2
  #define AIC_TMR_GUEST_VIRT	3
+#define AIC_CPU_PMU_E		4
+#define AIC_CPU_PMU_P		5
 
  #endif

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:50 UTC #5 lore raw

PATCH v2 3/8 irqchip/apple-aic: Add cpumasks for E and P cores

In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.

This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.

---
 drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

drivers/irqchip/irq-apple-aic.c +14 -0

index 3759dc36cc8f..30ca80ccda8b 100644
@@ -177,6 +177,8 @@ struct aic_irq_chip {
 	void __iomem *base;
 	struct irq_domain *hw_domain;
 	struct irq_domain *ipi_domain;
+	struct cpumask ecore_mask;
+	struct cpumask pcore_mask;
 	int nr_hw;
 	int ipi_hwirq;
 };

@@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val)
 	writel_relaxed(val, ic->base + reg);
 }
 
+static bool __is_pcore(u64 mpidr)
+{
+	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
+}
+
 /*
  * IRQ irqchip
  */

@@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
 		return -ENODEV;
 	}
 
+	for_each_possible_cpu(i) {
+		if (__is_pcore(cpu_logical_map(i)))
+			cpumask_set_cpu(i, &irqc->pcore_mask);
+		else
+			cpumask_set_cpu(i, &irqc->ecore_mask);
+	}
+
 	set_handle_irq(aic_handle_irq);
 	set_handle_fiq(aic_handle_fiq);

Signature · 1 line

2.30.2

Mark Rutland

maintainer

2021-12-01 16:08 UTC #6 lore raw

Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores

Quoted 6 lines · Marc Zyngier

In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.
This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.

... but may change at any arbitrary point in future?

Can we please put the affinity in the DT, like we do for other SoCs and devices?

I don't think we should treat this HW specially in this regard; we certaintly don't want other folk hard-coding system topology in their irqchip driver, and it should be possible to do something like the ppi-partitions binding, no?

Thanks,
Mark.

Quoted 47 lines

---
 drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

drivers/irqchip/irq-apple-aic.c +14 -0

index 3759dc36cc8f..30ca80ccda8b 100644
@@ -177,6 +177,8 @@ struct aic_irq_chip {
 	void __iomem *base;
 	struct irq_domain *hw_domain;
 	struct irq_domain *ipi_domain;
+	struct cpumask ecore_mask;
+	struct cpumask pcore_mask;
 	int nr_hw;
 	int ipi_hwirq;
 };

@@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val)
 	writel_relaxed(val, ic->base + reg);
 }
 
+static bool __is_pcore(u64 mpidr)
+{
+	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
+}
+
 /*
  * IRQ irqchip
  */

@@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
 		return -ENODEV;
 	}
 
+	for_each_possible_cpu(i) {
+		if (__is_pcore(cpu_logical_map(i)))
+			cpumask_set_cpu(i, &irqc->pcore_mask);
+		else
+			cpumask_set_cpu(i, &irqc->ecore_mask);
+	}
+
 	set_handle_irq(aic_handle_irq);
 	set_handle_fiq(aic_handle_fiq);

Signature · 1 line

2.30.2

Marc Zyngier

author

2021-12-03 16:32 UTC #7 lore raw

Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores

Quoted 10 lines · Mark Rutland

Quoted 6 lines · Marc Zyngier
In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.
This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.
... but may change at any arbitrary point in future?

Crystal balls are in short supply, sorry! ;-)

Quoted 6 lines

Can we please put the affinity in the DT, like we do for other SoCs and devices?
I don't think we should treat this HW specially in this regard; we certaintly don't want other folk hard-coding system topology in their irqchip driver, and it should be possible to do something like the ppi-partitions binding, no?

The PPI partition is totally overkill here. What it deals with is multiple devices sharing a single PPI across the system.

Here, we can invent our own interrupt number, so the sharing is avoided by construction (the joy of not having an interrupt controller the first place!).

I'm happy to stick the affinity in the DT (after all, it is likely that other devices on these systems have the same requirements) and have it consumed by the irqchip driver. I only need to find a way that doesn't completely invalidate the existing binding...

M.

Signature · 1 line

Without deviation from the norm, progress is not possible.

Hector Martin

2021-12-12 07:22 UTC #8 lore raw

Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores

Quoted 8 lines · Marc Zyngier

Quoted 6 lines · Mark Rutland
Quoted 4 lines · Marc Zyngier
In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.

Quoted 6 lines

Quoted 4 lines
Quoted 2 lines
This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.
... but may change at any arbitrary point in future?
Crystal balls are in short supply, sorry! ;-)

Considering Apple seem to rely on this all over the place, I think they probably won't be changing the meaning of Aff2 at least until they decide to come up with SoCs that have 3 types of cores, or something like that :)

But yeah, ultimately this is a guess.

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Hector Martin

2021-12-12 07:30 UTC #9 lore raw

Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores

Quoted 42 lines · Marc Zyngier

In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.

This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.

---
  drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++
  1 file changed, 14 insertions(+)

drivers/irqchip/irq-apple-aic.c +7 -0

index 3759dc36cc8f..30ca80ccda8b 100644
@@ -177,6 +177,8 @@ struct aic_irq_chip {
  	void __iomem *base;
  	struct irq_domain *hw_domain;
  	struct irq_domain *ipi_domain;
+	struct cpumask ecore_mask;
+	struct cpumask pcore_mask;
  	int nr_hw;
  	int ipi_hwirq;
  };

@@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val)
  	writel_relaxed(val, ic->base + reg);
  }
 
+static bool __is_pcore(u64 mpidr)
+{
+	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
+}
+
  /*
   * IRQ irqchip
   */

@@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
  		return -ENODEV;
  	}

drivers/irqchip/irq-apple-aic.c static int __init aic_of_ic_init(struct device_node *node, struct device_node *p · line 852

Quoted 10 lines

drivers/irqchip/irq-apple-aic.c +7 -0

+	for_each_possible_cpu(i) {
+		if (__is_pcore(cpu_logical_map(i)))
+			cpumask_set_cpu(i, &irqc->pcore_mask);
+		else
+			cpumask_set_cpu(i, &irqc->ecore_mask);
+	}
+
  	set_handle_irq(aic_handle_irq);
  	set_handle_fiq(aic_handle_fiq);

I'm okay with this approach, but if we want to be more explicit about the affinities, maybe something like apple,pmu-irq-index in the CPU nodes? Then we can either start at a higher FIQ offset for these (in case we need to add more FIQs in the future), or just make up a new AIC_PMU top level interrupt type and start at 0.

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-13 14:43 UTC #10 lore raw

Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores

Quoted 49 lines · Hector Martin

Quoted 47 lines · Marc Zyngier

In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, compute the cpumasks of the P and E cores at boot time.

This relies on the affinity scheme used by the vendor, which seems to work for the couple of SoCs that are out in the wild.

---
  drivers/irqchip/irq-apple-aic.c | 14 ++++++++++++++
  1 file changed, 14 insertions(+)

drivers/irqchip/irq-apple-aic.c +12 -0

index 3759dc36cc8f..30ca80ccda8b 100644
@@ -177,6 +177,8 @@ struct aic_irq_chip {
  	void __iomem *base;
  	struct irq_domain *hw_domain;
  	struct irq_domain *ipi_domain;
+	struct cpumask ecore_mask;
+	struct cpumask pcore_mask;
  	int nr_hw;
  	int ipi_hwirq;
  };

@@ -200,6 +202,11 @@ static void aic_ic_write(struct aic_irq_chip *ic, u32 reg, u32 val)
  	writel_relaxed(val, ic->base + reg);
  }
  +static bool __is_pcore(u64 mpidr)
+{
+	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
+}
+
  /*
   * IRQ irqchip
   */

@@ -833,6 +840,13 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
  		return -ENODEV;
  	}
  +	for_each_possible_cpu(i) {
+		if (__is_pcore(cpu_logical_map(i)))
+			cpumask_set_cpu(i, &irqc->pcore_mask);
+		else
+			cpumask_set_cpu(i, &irqc->ecore_mask);
+	}
+
  	set_handle_irq(aic_handle_irq);

Quoted 8 lines

drivers/irqchip/irq-apple-aic.c static int __init aic_of_ic_init(struct device_node *node, struct device_node *p · line 852
Quoted 2 lines
drivers/irqchip/irq-apple-aic.c +0 -0
  	set_handle_fiq(aic_handle_fiq);
 
I'm okay with this approach, but if we want to be more explicit about the affinities, maybe something like apple,pmu-irq-index in the CPU nodes? Then we can either start at a higher FIQ offset for these (in case we need to add more FIQs in the future), or just make up a new AIC_PMU top level interrupt type and start at 0.

I'm actually worried that we'll need more of these "asymmetric FIQs" in the future, and that the PMU-specific hack won't scale.

Do you know of any other per-CPU device that could differ between small and big cores? This would certainly help guiding my implementation between a device specific hack (the PMU irq index) or something more generic (interrupt specifier containing the affinity and following the AICv2 scheme).

Thanks,

M.

Signature · 1 line

Without deviation from the norm, progress is not possible.

Marc Zyngier

author

2021-12-01 13:49 UTC #11 lore raw

PATCH v2 4/8 irqchip/apple-aic: Wire PMU interrupts

Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt.

---
 drivers/irqchip/irq-apple-aic.c | 34 +++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

drivers/irqchip/irq-apple-aic.c +22 ~~-12~~

index 30ca80ccda8b..23f5f10e974e 100644
@@ -155,7 +155,7 @@
 #define SYS_IMP_APL_UPMSR_EL1		sys_reg(3, 7, 15, 6, 4)
 #define UPMSR_IACT			BIT(0)
 
-#define AIC_NR_FIQ		4
+#define AIC_NR_FIQ		6
 #define AIC_NR_SWIPI		32
 
 /*

@@ -207,6 +207,11 @@ static bool __is_pcore(u64 mpidr)
 	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
 }
 
+static bool is_pcore(void)
+{
+	return __is_pcore(read_cpuid_mpidr());
+}
+
 /*
  * IRQ irqchip
  */

@@ -420,16 +425,10 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
 						  aic_irqc->nr_hw + AIC_TMR_EL02_VIRT);
 	}
 
-	if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
-			(FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) {
-		/*
-		 * Not supported yet, let's figure out how to handle this when
-		 * we implement these proprietary performance counters. For now,
-		 * just mask it and move on.
-		 */
-		pr_err_ratelimited("PMC FIQ fired. Masking.\n");
-		sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
-				   FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));
+	if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {
+		int irq = is_pcore() ? AIC_CPU_PMU_P : AIC_CPU_PMU_E;
+		generic_handle_domain_irq(aic_irqc->hw_domain,
+					  aic_irqc->nr_hw + irq);
 	}
 
 	if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ &&

@@ -469,7 +468,18 @@ static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
 				    handle_fasteoi_irq, NULL, NULL);
 		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
 	} else {
-		irq_set_percpu_devid(irq);
+		switch (hw - ic->nr_hw) {
+		case AIC_CPU_PMU_P:
+			irq_set_percpu_devid_partition(irq, &ic->pcore_mask);
+			break;
+		case AIC_CPU_PMU_E:
+			irq_set_percpu_devid_partition(irq, &ic->ecore_mask);
+			break;
+		default:
+			irq_set_percpu_devid(irq);
+			break;
+		}
+
 		irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data,
 				    handle_percpu_devid_irq, NULL, NULL);
 	}

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 4/8

2021-12-12 07:25 UTC #12 lore raw

Re: [PATCH v2 4/8] irqchip/apple-aic: Wire PMU interrupts

Quoted 66 lines · Marc Zyngier

Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt.

---
  drivers/irqchip/irq-apple-aic.c | 34 +++++++++++++++++++++------------
  1 file changed, 22 insertions(+), 12 deletions(-)

drivers/irqchip/irq-apple-aic.c +15 ~~-12~~

index 30ca80ccda8b..23f5f10e974e 100644
@@ -155,7 +155,7 @@
  #define SYS_IMP_APL_UPMSR_EL1		sys_reg(3, 7, 15, 6, 4)
  #define UPMSR_IACT			BIT(0)
 
-#define AIC_NR_FIQ		4
+#define AIC_NR_FIQ		6
  #define AIC_NR_SWIPI		32
 
  /*

@@ -207,6 +207,11 @@ static bool __is_pcore(u64 mpidr)
  	return MPIDR_AFFINITY_LEVEL(mpidr, 2) == 1;
  }
 
+static bool is_pcore(void)
+{
+	return __is_pcore(read_cpuid_mpidr());
+}
+
  /*
   * IRQ irqchip
   */

@@ -420,16 +425,10 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
  						  aic_irqc->nr_hw + AIC_TMR_EL02_VIRT);
  	}
 
-	if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
-			(FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) {
-		/*
-		 * Not supported yet, let's figure out how to handle this when
-		 * we implement these proprietary performance counters. For now,
-		 * just mask it and move on.
-		 */
-		pr_err_ratelimited("PMC FIQ fired. Masking.\n");
-		sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
-				   FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));
+	if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {
+		int irq = is_pcore() ? AIC_CPU_PMU_P : AIC_CPU_PMU_E;
+		generic_handle_domain_irq(aic_irqc->hw_domain,
+					  aic_irqc->nr_hw + irq);
  	}
 
  	if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ &&

@@ -469,7 +468,18 @@ static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
  				    handle_fasteoi_irq, NULL, NULL);
  		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
  	} else {
-		irq_set_percpu_devid(irq);
+		switch (hw - ic->nr_hw) {
+		case AIC_CPU_PMU_P:
+			irq_set_percpu_devid_partition(irq, &ic->pcore_mask);
+			break;
+		case AIC_CPU_PMU_E:

drivers/irqchip/irq-apple-aic.c static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq, · line 485

Quoted 10 lines

drivers/irqchip/irq-apple-aic.c +7 -0

+			irq_set_percpu_devid_partition(irq, &ic->ecore_mask);
+			break;
+		default:
+			irq_set_percpu_devid(irq);
+			break;
+		}
+
  		irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data,
  				    handle_percpu_devid_irq, NULL, NULL);
  	}

I still find this idea that we need to split the IRQs virtually quite bizarre, but if that's how bit.LITTLE systems do it...

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:50 UTC #13 lore raw

PATCH v2 5/8 irqchip/apple-aic: Move PMU-specific registers to their own include file

As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file.

---
 arch/arm64/include/asm/apple_m1_pmu.h | 19 +++++++++++++++++++
 drivers/irqchip/irq-apple-aic.c       | 11 +----------
 2 files changed, 20 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h

arch/arm64/include/asm/apple_m1_pmu.h new file +19 -0

new file mode 100644
index 000000000000..b848af7faadc
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __ASM_APPLE_M1_PMU_h
+#define __ASM_APPLE_M1_PMU_h
+
+#include <linux/bits.h>
+#include <asm/sysreg.h>
+
+/* Core PMC control register */
+#define SYS_IMP_APL_PMCR0_EL1	sys_reg(3, 1, 15, 0, 0)
+#define PMCR0_IMODE		GENMASK(10, 8)
+#define PMCR0_IMODE_OFF		0
+#define PMCR0_IMODE_PMI		1
+#define PMCR0_IMODE_AIC		2
+#define PMCR0_IMODE_HALT	3
+#define PMCR0_IMODE_FIQ		4
+#define PMCR0_IACT		BIT(11)
+
+#endif /* __ASM_APPLE_M1_PMU_h */

drivers/irqchip/irq-apple-aic.c +1 ~~-10~~

index 23f5f10e974e..9663166fd97f 100644
@@ -55,6 +55,7 @@
 #include <linux/limits.h>
 #include <linux/of_address.h>
 #include <linux/slab.h>
+#include <asm/apple_m1_pmu.h>
 #include <asm/exception.h>
 #include <asm/sysreg.h>
 #include <asm/virt.h>

@@ -109,16 +110,6 @@
  * Note: sysreg-based IPIs are not supported yet.
  */
 
-/* Core PMC control register */
-#define SYS_IMP_APL_PMCR0_EL1		sys_reg(3, 1, 15, 0, 0)
-#define PMCR0_IMODE			GENMASK(10, 8)
-#define PMCR0_IMODE_OFF			0
-#define PMCR0_IMODE_PMI			1
-#define PMCR0_IMODE_AIC			2
-#define PMCR0_IMODE_HALT		3
-#define PMCR0_IMODE_FIQ			4
-#define PMCR0_IACT			BIT(11)
-
 /* IPI request registers */
 #define SYS_IMP_APL_IPI_RR_LOCAL_EL1	sys_reg(3, 5, 15, 0, 0)
 #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1	sys_reg(3, 5, 15, 0, 1)

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 5/8

2021-12-12 07:23 UTC #14 lore raw

Re: [PATCH v2 5/8] irqchip/apple-aic: Move PMU-specific registers to their own include file

Quoted 55 lines · Marc Zyngier

As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file.

---
  arch/arm64/include/asm/apple_m1_pmu.h | 19 +++++++++++++++++++
  drivers/irqchip/irq-apple-aic.c       | 11 +----------
  2 files changed, 20 insertions(+), 10 deletions(-)

create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h

arch/arm64/include/asm/apple_m1_pmu.h new file +19 -0

new file mode 100644
index 000000000000..b848af7faadc
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __ASM_APPLE_M1_PMU_h
+#define __ASM_APPLE_M1_PMU_h
+
+#include <linux/bits.h>
+#include <asm/sysreg.h>
+
+/* Core PMC control register */
+#define SYS_IMP_APL_PMCR0_EL1	sys_reg(3, 1, 15, 0, 0)
+#define PMCR0_IMODE		GENMASK(10, 8)
+#define PMCR0_IMODE_OFF		0
+#define PMCR0_IMODE_PMI		1
+#define PMCR0_IMODE_AIC		2
+#define PMCR0_IMODE_HALT	3
+#define PMCR0_IMODE_FIQ		4
+#define PMCR0_IACT		BIT(11)
+
+#endif /* __ASM_APPLE_M1_PMU_h */

drivers/irqchip/irq-apple-aic.c +1 -3

index 23f5f10e974e..9663166fd97f 100644
@@ -55,6 +55,7 @@
  #include <linux/limits.h>
  #include <linux/of_address.h>
  #include <linux/slab.h>
+#include <asm/apple_m1_pmu.h>
  #include <asm/exception.h>
  #include <asm/sysreg.h>
  #include <asm/virt.h>

@@ -109,16 +110,6 @@
   * Note: sysreg-based IPIs are not supported yet.
   */
 
-/* Core PMC control register */
-#define SYS_IMP_APL_PMCR0_EL1		sys_reg(3, 1, 15, 0, 0)
-#define PMCR0_IMODE			GENMASK(10, 8)

drivers/irqchip/irq-apple-aic.c line 115

Quoted 10 lines

drivers/irqchip/irq-apple-aic.c +0 -7

-#define PMCR0_IMODE_OFF			0
-#define PMCR0_IMODE_PMI			1
-#define PMCR0_IMODE_AIC			2
-#define PMCR0_IMODE_HALT		3
-#define PMCR0_IMODE_FIQ			4
-#define PMCR0_IACT			BIT(11)
-
  /* IPI request registers */
  #define SYS_IMP_APL_IPI_RR_LOCAL_EL1	sys_reg(3, 5, 15, 0, 0)
  #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1	sys_reg(3, 5, 15, 0, 1)

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:49 UTC #15 lore raw

PATCH v2 6/8 arm64: apple: t8301: Add PMU nodes

Advertise the two PMU nodes for the t8103 SoC.

---
 arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/apple/t8103.dtsi +12 -0

index fc8b2bb06ffe..d2e9afde3729 100644
@@ -96,6 +96,18 @@ timer {
 			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	pmu-e {
+		compatible = "apple,icestorm-pmu";
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu-p {
+		compatible = "apple,firestorm-pmu";
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	clk24: clock-24m {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 6/8

2021-12-12 07:26 UTC #16 lore raw

Re: [PATCH v2 6/8] arm64: apple: t8301: Add PMU nodes

Quoted 21 lines · Marc Zyngier

Advertise the two PMU nodes for the t8103 SoC.

---
  arch/arm64/boot/dts/apple/t8103.dtsi | 12 ++++++++++++
  1 file changed, 12 insertions(+)

arch/arm64/boot/dts/apple/t8103.dtsi +5 -0

index fc8b2bb06ffe..d2e9afde3729 100644
@@ -96,6 +96,18 @@ timer {
  			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
  	};
 
+	pmu-e {
+		compatible = "apple,icestorm-pmu";
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
+	};

arch/arm64/boot/dts/apple/t8103.dtsi timer { · line 113

Quoted 10 lines

arch/arm64/boot/dts/apple/t8103.dtsi +7 -0

+
+	pmu-p {
+		compatible = "apple,firestorm-pmu";
+		interrupt-parent = <&aic>;
+		interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
+	};
+
  	clk24: clock-24m {
  		compatible = "fixed-clock";
  		#clock-cells = <0>;

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:50 UTC #17 lore raw

PATCH v2 7/8 drivers/perf: arm_pmu: Handle 47 bit counters

The current ARM PMU framework can only deal with 32 or 64bit counters. Teach it about a 47bit flavour.

Yes, this is odd.

---
 drivers/perf/arm_pmu.c       | 2 ++
 include/linux/perf/arm_pmu.h | 2 ++
 2 files changed, 4 insertions(+)

drivers/perf/arm_pmu.c +2 -0

index 295cc7952d0e..0a9ed1a061ac 100644
@@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_event *event)
 {
 	if (event->hw.flags & ARMPMU_EVT_64BIT)
 		return GENMASK_ULL(63, 0);
+	else if (event->hw.flags & ARMPMU_EVT_47BIT)
+		return GENMASK_ULL(46, 0);
 	else
 		return GENMASK_ULL(31, 0);
 }

include/linux/perf/arm_pmu.h +2 -0

index 2512e2f9cd4e..0407a38b470a 100644
@@ -26,6 +26,8 @@
  */
 /* Event uses a 64bit counter */
 #define ARMPMU_EVT_64BIT		1
+/* Event uses a 47bit counter */
+#define ARMPMU_EVT_47BIT		2
 
 #define HW_OP_UNSUPPORTED		0xFFFF
 #define C(_x)				PERF_COUNT_HW_CACHE_##_x

Signature · 1 line

2.30.2

Hector Martin

Reviewed-by on v2 7/8

2021-12-12 07:26 UTC #18 lore raw

Re: [PATCH v2 7/8] drivers/perf: arm_pmu: Handle 47 bit counters

Quoted 30 lines · Marc Zyngier

The current ARM PMU framework can only deal with 32 or 64bit counters. Teach it about a 47bit flavour.

Yes, this is odd.

---
  drivers/perf/arm_pmu.c       | 2 ++
  include/linux/perf/arm_pmu.h | 2 ++
  2 files changed, 4 insertions(+)

drivers/perf/arm_pmu.c +2 -0

index 295cc7952d0e..0a9ed1a061ac 100644
@@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_event *event)
  {
  	if (event->hw.flags & ARMPMU_EVT_64BIT)
  		return GENMASK_ULL(63, 0);
+	else if (event->hw.flags & ARMPMU_EVT_47BIT)
+		return GENMASK_ULL(46, 0);
  	else
  		return GENMASK_ULL(31, 0);
  }

include/linux/perf/arm_pmu.h +0 -0

index 2512e2f9cd4e..0407a38b470a 100644

include/linux/perf/arm_pmu.h line 33

Quoted 8 lines

include/linux/perf/arm_pmu.h +2 -0

@@ -26,6 +26,8 @@
   */
  /* Event uses a 64bit counter */
  #define ARMPMU_EVT_64BIT		1
+/* Event uses a 47bit counter */
+#define ARMPMU_EVT_47BIT		2
 
  #define HW_OP_UNSUPPORTED		0xFFFF
  #define C(_x)				PERF_COUNT_HW_CACHE_##_x

Signature · 2 lines

Hector Martin ([email protected])
Public Key: https://mrcn.st/pub

Marc Zyngier

author

2021-12-01 13:49 UTC #19 lore raw

PATCH v2 8/8 drivers/perf: Add Apple icestorm/firestorm CPU PMU driver

Add a new, weird and wonderful driver for the equally weird Apple PMU HW. Although the PMU itself is functional, we don't know much about the events yet, so this can be considered as yet another random number generator...

Nonetheless, it can reliably count at least cycles and instructions in the usually wonky big-little way. For anything else, it of course supports raw event numbers.