coresight: Fix TRCCONFIGR.QE sysfs interface
v2 cover coresight: Fix TRCCONFIGR.QE sysfs interface
Changes since v1:
* Add Mike's reviewed by tag
* Also make it impossible to write the reserved value of 0b10, regardless of what is supplied by the user.
James Clark (1):
coresight: Fix TRCCONFIGR.QE sysfs interface
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Signature · 1 line
2.28.0
PATCH v2 1/1 coresight: Fix TRCCONFIGR.QE sysfs interface
It's impossible to program a valid value for TRCCONFIGR.QE when TRCIDR0.QSUPP==0b10. In that case the following is true:
Q element support is implemented, and only supports Q elements without instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11.
Currently the low bit of QSUPP is checked to see if the low bit of QE can be written to, but as you can see when QSUPP==0b10 the low bit is cleared making it impossible to ever write the only valid value of 0b11 to QE. 0b10 would be written instead, which is a reserved QE value even for all values of QSUPP.
The fix is to allow writing the low bit of QE for any non zero value of QSUPP.
This change also ensures that the low bit is always set, even when the user attempts to only set the high bit.
--- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +6 -2
@@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, mode =ETM_MODE_QELEM (config->mode);/* start by clearing QE bits */ config->cfg &= ~(BIT (13 ) |BIT (14 )); -/* if supported, Q elements with instruction counts are enabled */ -if ((mode &BIT (0 )) && (drvdata->q_support &BIT (0 ))) +/* +* if supported, Q elements with instruction counts are enabled. +* Always set the low bit for any requested mode. Valid combos are +* 0b00, 0b01 and 0b11. +*/ +if (mode && drvdata->q_support) config->cfg |=BIT (13 );/* * if supported, Q elements with and without instruction
Signature · 1 line
2.28.0
Quoted 31 lines · James Clark
It's impossible to program a valid value for TRCCONFIGR.QE when TRCIDR0.QSUPP==0b10. In that case the following is true:
Q element support is implemented, and only supports Q elements without instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11.
Currently the low bit of QSUPP is checked to see if the low bit of QE can be written to, but as you can see when QSUPP==0b10 the low bit is cleared making it impossible to ever write the only valid value of 0b11 to QE. 0b10 would be written instead, which is a reserved QE value even for all values of QSUPP.
The fix is to allow writing the low bit of QE for any non zero value of QSUPP.
This change also ensures that the low bit is always set, even when the user attempts to only set the high bit.
Signed-off-by James Clark <[email protected]>Reviewed-by Mike Leach <[email protected]>--- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +0
-0@@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, mode =ETM_MODE_QELEM (config->mode);/* start by clearing QE bits */
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c static ssize_t mode_store(struct device *dev, · line 376
Quoted 10 lines
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +6
-2config->cfg &= ~(BIT (13 ) |BIT (14 )); -/* if supported, Q elements with instruction counts are enabled */ -if ((mode &BIT (0 )) && (drvdata->q_support &BIT (0 ))) +/* +* if supported, Q elements with instruction counts are enabled. +* Always set the low bit for any requested mode. Valid combos are +* 0b00, 0b01 and 0b11. +*/ +if (mode && drvdata->q_support) config->cfg |=BIT (13 );
Interesting brain gymnastic - applied.
Thanks,
Mathieu
Quoted 5 lines
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +0
-0/* * if supported, Q elements with and without instruction Signature · 1 line
2.28.0