ARM: mstar: cpupll

PATCH Superseded Romain Perier 2 participants 12 messages Jan 21, 2022 – Jan 23, 2022

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Device tree bindings Common clk Arm/MStar/Sigmastar Armv7 SoC support

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Romain Perier

author maintainer

2022-01-21 19:35 UTC #0 lore raw

v3 cover ARM: mstar: cpupll

This series adds a basic driver for the PLL that generates the cpu clock on MStar/SigmaStar ARMv7 SoCs.

Unfortunately there isn't much documentation for this thing so there are few magic values and guesses.

This needs to come after the MPLL DT changes.

Changes since v2:
- Re-ordered Kconfig by name
- Re-ordered includes alphabetically and removed useless ones
- Used timeout for cpu_relax
- Returned DIV_ROUND_DOWN_ULL() directly in msc313_cpupll_frequencyforreg()
- Returned DIV_ROUND_DOWN_ULL() directly in msc313_cpupll_regforfrequecy()
- Reduced the number of lines for msc313_cpupll_of_match
- Removed CLK_IS_CRITICAL

Changes since v1:
- Re-worked the series and ensure that 'make dt_binding_check' passes. The required commit is merged now, so it is okay.
- Fixed coding style issues in the driver and makes check_patch.pl happy
- Added one more commit for extending the opp_table for infinity2m.

Daniel Palmer (8):
dt-bindings: clk: mstar msc313 cpupll binding description
clk: mstar: msc313 cpupll clk driver
ARM: mstar: Add cpupll to base dtsi
ARM: mstar: Link cpupll to cpu
ARM: mstar: Link cpupll to second core
ARM: mstar: Add OPP table for infinity
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for mercury5

Romain Perier (1):
ARM: mstar: Extend opp_table for infinity2m

 .../bindings/clock/mstar,msc313-cpupll.yaml   |  45 ++++
 arch/arm/boot/dts/mstar-infinity.dtsi         |  34 +++
 arch/arm/boot/dts/mstar-infinity2m.dtsi       |  17 ++
 arch/arm/boot/dts/mstar-infinity3.dtsi        |  58 +++++
 arch/arm/boot/dts/mstar-mercury5.dtsi         |  36 +++
 arch/arm/boot/dts/mstar-v7.dtsi               |   9 +
 drivers/clk/mstar/Kconfig                     |   8 +
 drivers/clk/mstar/Makefile                    |   2 +-
 drivers/clk/mstar/clk-msc313-cpupll.c         | 221 ++++++++++++++++++
 9 files changed, 429 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml
 create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:35 UTC #1 lore raw

PATCH v3 1/9 dt-bindings: clk: mstar msc313 cpupll binding description

From: Daniel Palmer <[email protected]>

Add a binding description for the MStar/SigmaStar CPU PLL block.

Signed-off-by Daniel Palmer <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 .../bindings/clock/mstar,msc313-cpupll.yaml   | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml

Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file +45 -0

new file mode 100644
index 000000000000..a9ad7ab5230c
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar/Sigmastar MSC313 CPU PLL
+
+maintainers:
+  - Daniel Palmer <[email protected]>
+
+description: |
+  The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
+  PLL that can be used as the clock source for the CPU(s).
+
+properties:
+  compatible:
+    const: mstar,msc313-cpupll
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mstar-msc313-mpll.h>
+    cpupll: cpupll@206400 {
+        compatible = "mstar,msc313-cpupll";
+        reg = <0x206400 0x200>;
+        #clock-cells = <1>;
+        clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
+    };

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:35 UTC #2 lore raw

PATCH v3 2/9 clk: mstar: msc313 cpupll clk driver

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs.

Currently there is no documentation for this block so it's possible this driver isn't entirely correct.

Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs.

Co-authored-by Willy Tarreau <[email protected]>

Signed-off-by Daniel Palmer <[email protected]>

---
 drivers/clk/mstar/Kconfig             |   8 +
 drivers/clk/mstar/Makefile            |   2 +-
 drivers/clk/mstar/clk-msc313-cpupll.c | 221 ++++++++++++++++++++++++++
 3 files changed, 230 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c

drivers/clk/mstar/Kconfig +8 -0

index de37e1bce2d2..146eeb637318 100644
@@ -1,4 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-only
+config MSTAR_MSC313_CPUPLL
+	bool "MStar CPUPLL driver"
+	depends on ARCH_MSTARV7 || COMPILE_TEST
+	default ARCH_MSTARV7
+	help
+	  Support for the CPU PLL present on MStar/Sigmastar SoCs.
+
 config MSTAR_MSC313_MPLL
 	bool "MStar MPLL driver"
 	depends on ARCH_MSTARV7 || COMPILE_TEST

@@ -7,3 +14,4 @@ config MSTAR_MSC313_MPLL
 	help
 	  Support for the MPLL PLL and dividers block present on
 	  MStar/Sigmastar SoCs.
+

drivers/clk/mstar/Makefile +1 -1

index f8dcd25ede1d..21296a04e65a 100644
@@ -2,5 +2,5 @@
 #
 # Makefile for mstar specific clk
 #
-
+obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o
 obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o

drivers/clk/mstar/clk-msc313-cpupll.c new file +221 -0

221 lines not on this page · raw message

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:35 UTC #3 lore raw

PATCH v3 3/9 ARM: mstar: Add cpupll to base dtsi

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

arch/arm/boot/dts/mstar-v7.dtsi +7 -0

index 89ebfe4f29da..2249faaa3aa7 100644
@@ -155,6 +155,13 @@ mpll: mpll@206000 {
 				clocks = <&xtal>;
 			};
 
+			cpupll: cpupll@206400 {
+				compatible = "mstar,msc313-cpupll";
+				reg = <0x206400 0x200>;
+				#clock-cells = <0>;
+				clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
+			};
+
 			gpio: gpio@207800 {
 				#gpio-cells = <2>;
 				reg = <0x207800 0x200>;

Signature · 1 line

2.34.1

Daniel Palmer

2022-01-23 05:10 UTC #4 lore raw

Re: [PATCH v3 3/9] ARM: mstar: Add cpupll to base dtsi

Hi Romain,

Quoted 30 lines · Romain Perier

From: Daniel Palmer <[email protected]>

All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

arch/arm/boot/dts/mstar-v7.dtsi +7 -1

index 89ebfe4f29da..2249faaa3aa7 100644
@@ -155,6 +155,13 @@ mpll: mpll@206000 {
                                clocks = <&xtal>;
                        };
 
+                       cpupll: cpupll@206400 {
+                               compatible = "mstar,msc313-cpupll";
+                               reg = <0x206400 0x200>;
+                               #clock-cells = <0>;
+                               clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
+                       };
+
                        gpio: gpio@207800 {
                                #gpio-cells = <2>;
                                reg = <0x207800 0x200>;
--

Quoted 2 lines

2.34.1

I guess I can't add a reviewed by for my own commit but this looks good to me. The same CPUPLL is present on all of the chips seen so far so this is the right place for this.

Cheers,

Daniel

Romain Perier

author maintainer

2022-01-21 19:35 UTC #5 lore raw

PATCH v3 4/9 ARM: mstar: Link cpupll to cpu

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

The CPU clock is sourced from the CPU PLL.
Link cpupll to the cpu so that frequency scaling can happen.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-v7.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/boot/dts/mstar-v7.dtsi +2 -0

index 2249faaa3aa7..c26ba9b7b6dd 100644
@@ -21,6 +21,8 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
+			clocks = <&cpupll>;
+			clock-names = "cpuclk";
 		};
 	};

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:35 UTC #6 lore raw

PATCH v3 5/9 ARM: mstar: Link cpupll to second core

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

The second core also sources it's clock from the CPU PLL.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/boot/dts/mstar-infinity2m.dtsi +2 -0

index 6d4d1d224e96..dc339cd29778 100644
@@ -11,6 +11,8 @@ cpu1: cpu@1 {
 		device_type = "cpu";
 		compatible = "arm,cortex-a7";
 		reg = <0x1>;
+		clocks = <&cpupll>;
+		clock-names = "cpuclk";
 	};
 };

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:36 UTC #7 lore raw

PATCH v3 6/9 ARM: mstar: Add OPP table for infinity

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

Add an OPP table for the inifinity chips so
that cpu frequency scaling can happen.

Co-authored-by Willy Tarreau <[email protected]>

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

arch/arm/boot/dts/mstar-infinity.dtsi +34 -0

index 0bee517797f4..441a917b88ba 100644
@@ -8,6 +8,40 @@
 
 #include <dt-bindings/gpio/msc313-gpio.h>
 
+/ {
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-240000000 {
+			opp-hz = /bits/ 64 <240000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu0_opp_table>;
+};
+
 &imi {
 	reg = <0xa0000000 0x16000>;
 };

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:36 UTC #8 lore raw

PATCH v3 7/9 ARM: mstar: Add OPP table for infinity3

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

The infinity3 has a slightly higher max frequency
compared to the infinity so extend the OPP table.

Co-authored-by Willy Tarreau <[email protected]>

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-infinity3.dtsi | 58 ++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

arch/arm/boot/dts/mstar-infinity3.dtsi +58 -0

index 9857e2a9934d..a56cf29e5d82 100644
@@ -6,6 +6,64 @@
 
 #include "mstar-infinity.dtsi"
 
+&cpu0_opp_table {
+	opp-1008000000 {
+		opp-hz = /bits/ 64 <1008000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+	};
+
+	// overclock frequencies below, shown to work fine up to 1.3 GHz
+	opp-108000000 {
+		opp-hz = /bits/ 64 <1080000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1188000000 {
+		opp-hz = /bits/ 64 <1188000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1296000000 {
+		opp-hz = /bits/ 64 <1296000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1350000000 {
+		opp-hz = /bits/ 64 <1350000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1404000000 {
+		opp-hz = /bits/ 64 <1404000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1458000000 {
+		opp-hz = /bits/ 64 <1458000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+
+	opp-1512000000 {
+		opp-hz = /bits/ 64 <1512000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <300000>;
+		turbo-mode;
+	};
+};
+
 &imi {
 	reg = <0xa0000000 0x20000>;
 };

Signature · 1 line

2.34.1

Romain Perier

author maintainer

2022-01-21 19:36 UTC #9 lore raw

PATCH v3 8/9 ARM: mstar: Add OPP table for mercury5

In reply to Romain Perier

From: Daniel Palmer <[email protected]>

Add an OPP table for mercury5 so that cpu frequency scaling can happen.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

arch/arm/boot/dts/mstar-mercury5.dtsi +36 -0

index a7d0dd9d6132..80a19bd23c9c 100644
@@ -6,6 +6,42 @@
 
 #include "mstar-v7.dtsi"
 
+/ {
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <800000 800000 850000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <850000 850000 880000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <880000 880000 890000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <900000 900000 1000000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <900000 900000 1000000>;
+			clock-latency-ns = <300000>;
+		};
+	};
+};
+
 &imi {
 	reg = <0xa0000000 0x20000>;
 };

Signature · 1 line

2.34.1

Daniel Palmer

2022-01-23 05:12 UTC #10 lore raw

Re: [PATCH v3 8/9] ARM: mstar: Add OPP table for mercury5

Hi Romain,

Quoted 59 lines · Romain Perier

From: Daniel Palmer <[email protected]>

Add an OPP table for mercury5 so that cpu frequency scaling can happen.

Signed-off-by Daniel Palmer <[email protected]>

---
 arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

arch/arm/boot/dts/mstar-mercury5.dtsi +36 -1

index a7d0dd9d6132..80a19bd23c9c 100644
@@ -6,6 +6,42 @@
 
 #include "mstar-v7.dtsi"
 
+/ {
+       cpu0_opp_table: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-100000000 {
+                       opp-hz = /bits/ 64 <100000000>;
+                       opp-microvolt = <800000 800000 850000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-microvolt = <850000 850000 880000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <880000 880000 890000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <900000 900000 1000000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <900000 900000 1000000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+};
+
 &imi {
        reg = <0xa0000000 0x20000>;
 };
--

Quoted 2 lines

2.34.1

I think we should drop this one when applying as the frequencies need to be checked on the hardware again.
I think they should probably match the msc313e settings that Willy verified.

Cheers,

Daniel

Romain Perier

author maintainer

2022-01-21 19:36 UTC #11 lore raw

PATCH v3 9/9 ARM: mstar: Extend opp_table for infinity2m

In reply to Romain Perier

infinity2m are running up to 1.2Ghz, this extends opp_table with the corresponding frequencies and enable operating-points table for cpu1

Signed-off-by Romain Perier <[email protected]>

---
 arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/boot/dts/mstar-infinity2m.dtsi +15 -0

index dc339cd29778..1b485efd7156 100644
@@ -6,10 +6,25 @@
 
 #include "mstar-infinity.dtsi"
 
+&cpu0_opp_table {
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <300000>;
+		};
+};
+
 &cpus {
 	cpu1: cpu@1 {
 		device_type = "cpu";
 		compatible = "arm,cortex-a7";
+		operating-points-v2 = <&cpu0_opp_table>;
 		reg = <0x1>;
 		clocks = <&cpupll>;
 		clock-names = "cpuclk";

Signature · 1 line

2.34.1