Second round of i915_reg.h splitting
Subsystems (4)
v2 cover Second round of i915_reg.h splitting
Let's continue to split our giant i915_reg.h file into more logical domain-specific headers. In addition to a bunch of register definition segregation, the final patch of this series ensures that i915_reg.h is only #include'd from .c files that truly need its definitions (and removes all of the places it was included by other headers). This significantly reduces how much of the driver code gets rebuilt after a modifications to i915_reg.h.
There's still more work to do after this series (especially moving display registers to their own header(s)). We'll also need to do a lot of cleanup of the definitions themselves in a future series --- for now the definitions have mostly been moved to new locations as-is without modification to order, coding-style, etc.
v2:
- Drop 'inline' from reg_in_range_table()
- Add missing #include to intel_pxp_irq.c
Matt Roper (6):
drm/i915/perf: Move OA regs to their own header drm/i915/perf: Express OA register ranges with i915_range drm/i915: Parameterize R_PWR_CLK_STATE register definition drm/i915: Parameterize MI_PREDICATE registers drm/i915: Move GT registers to their own header file drm/i915: Only include i915_reg.h from .c files
drivers/gpu/drm/i915/display/g4x_hdmi.h | 2 +- drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_bios.c | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 1 + drivers/gpu/drm/i915/display/intel_crt.h | 2 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 +- drivers/gpu/drm/i915/display/intel_de.h | 1 - .../drm/i915/display/intel_display_power.h | 1 - drivers/gpu/drm/i915/display/intel_dmc.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 2 - drivers/gpu/drm/i915/display/intel_dsb.h | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 2 - drivers/gpu/drm/i915/display/intel_lvds.h | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +- drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 + .../i915/gem/selftests/i915_gem_client_blt.c | 3 +- .../drm/i915/gem/selftests/i915_gem_context.c | 3 +- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine.h | 1 - drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_engine_regs.h | 26 + .../drm/i915/gt/intel_execlists_submission.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 2 + drivers/gpu/drm/i915/gt/intel_gt.c | 3 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 2 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 + drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1542 +++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/gt/intel_llc.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 + drivers/gpu/drm/i915/gt/intel_rc6.h | 2 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 2 + .../gpu/drm/i915/gt/intel_ring_submission.c | 1 + drivers/gpu/drm/i915/gt/intel_rps.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + .../gpu/drm/i915/gt/intel_workarounds_types.h | 2 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 1 + drivers/gpu/drm/i915/gvt/edid.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/gtt.c | 2 + drivers/gpu/drm/i915/gvt/handlers.c | 2 + drivers/gpu/drm/i915/gvt/interrupt.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.h | 2 +- drivers/gpu/drm/i915/gvt/mmio.c | 3 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.h | 1 - drivers/gpu/drm/i915/gvt/scheduler.c | 2 + drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 134 +- drivers/gpu/drm/i915/i915_perf_oa_regs.h | 137 ++ drivers/gpu/drm/i915/i915_perf_types.h | 2 +- drivers/gpu/drm/i915/i915_pmu.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2056 ----------------- drivers/gpu/drm/i915/i915_reg_defs.h | 4 + drivers/gpu/drm/i915/i915_sysfs.c | 1 + drivers/gpu/drm/i915/intel_dram.c | 1 + drivers/gpu/drm/i915/intel_pcode.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + drivers/gpu/drm/i915/intel_pm.h | 1 - drivers/gpu/drm/i915/intel_sbi.c | 1 + drivers/gpu/drm/i915/intel_uncore.c | 1 + drivers/gpu/drm/i915/intel_uncore.h | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 + drivers/gpu/drm/i915/vlv_sideband.c | 1 + drivers/gpu/drm/i915/vlv_suspend.c | 2 + 97 files changed, 1896 insertions(+), 2140 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_regs.h create mode 100644 drivers/gpu/drm/i915/i915_perf_oa_regs.h
Signature · 1 line
2.34.1
PATCH v2 1/6 drm/i915/perf: Move OA regs to their own header
The OA unit registers are only used by the perf code; move them to their own header file.
--- drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_perf_oa_regs.h | 497 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 485 ---------------------- 4 files changed, 499 insertions(+), 485 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_perf_oa_regs.h
drivers/gpu/drm/i915/gvt/scheduler.c +1 -0
@@ -43,6 +43,7 @@#include "i915_drv.h" #include "i915_gem_gtt.h" +#include "i915_perf_oa_regs.h" #include "gvt.h" #define RING_CTX_OFF (x) \
drivers/gpu/drm/i915/i915_perf.c +1 -0
@@ -208,6 +208,7 @@#include "i915_drv.h" #include "i915_perf.h" +#include "i915_perf_oa_regs.h" /* HW requires this to be a power of two, between 128k and 16M, though driver * is currently generally designed assuming the largest 16M size is used such
drivers/gpu/drm/i915/i915_perf_oa_regs.h new file +497 -0
497 lines not on this page · raw message
drivers/gpu/drm/i915/i915_reg.h +0 -485
512 lines not on this page · raw message
Signature · 1 line
2.34.1
Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header
Quoted 7 lines · Matt Roper
The OA unit registers are only used by the perf code; move them to their own header file.
Cc Jani Nikula <[email protected]>Cc Umesh Nerlige Ramappa <[email protected]>Cc Lionel Landwerlin <[email protected]>Signed-off-by Matt Roper <[email protected]>
I checked the output from git show --color-moved to help and indeed this is just moving the registers. Also, looking at the register names, they all seem to be OA/perf related.
Lucas De Marchi
PATCH v2 2/6 drm/i915/perf: Express OA register ranges with i915_range
In reply to Matt RoperLet's use 'struct i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity.
v2: Drop 'inline' from reg_in_range_table(). (Jani)
--- drivers/gpu/drm/i915/i915_perf.c | 120 +++++--- drivers/gpu/drm/i915/i915_perf_oa_regs.h | 360 ----------------------- 2 files changed, 77 insertions(+), 403 deletions(-)
drivers/gpu/drm/i915/i915_perf.c +77 -43
@@ -3864,80 +3864,114 @@ static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)return false; } -#define ADDR_IN_RANGE (addr, start, end) \ - ((addr) >= (start) && \ - (addr) <= (end)) +static bool reg_in_range_table (u32 addr,const struct i915_range *table) { +while (table->start || table->end) { +if (addr >= table->start && addr <= table->end) +return true; + + table++; + } -#define REG_IN_RANGE (addr, start, end) \ - ((addr) >= i915_mmio_reg_offset(start) && \ - (addr) <= i915_mmio_reg_offset(end)) +return false; +}#define REG_EQUAL (addr, mmio) \ ((addr) == i915_mmio_reg_offset(mmio)) -static bool gen7_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) -{ -return REG_IN_RANGE (addr,OASTARTTRIG1 ,OASTARTTRIG8 ) || -REG_IN_RANGE (addr,OAREPORTTRIG1 ,OAREPORTTRIG8 ) || -REG_IN_RANGE (addr,OACEC0_0 ,OACEC7_1 ); -} +static const struct i915_range gen7_oa_b_counters[] = { + { .start =0x2710 , .end =0x272c },/* OASTARTTRIG[1-8] */ + { .start =0x2740 , .end =0x275c },/* OAREPORTTRIG[1-8] */ + { .start =0x2770 , .end =0x27ac },/* OACEC[0-7][0-1] */ + {} +}; + +static const struct i915_range gen12_oa_b_counters[] = { + { .start =0x2b2c , .end =0x2b2c },/* GEN12_OAG_OA_PESS */ + { .start =0xd900 , .end =0xd91c },/* GEN12_OAG_OASTARTTRIG[1-8] */ + { .start =0xd920 , .end =0xd93c },/* GEN12_OAG_OAREPORTTRIG1[1-8] */ + { .start =0xd940 , .end =0xd97c },/* GEN12_OAG_CEC[0-7][0-1] */ + { .start =0xdc00 , .end =0xdc3c },/* GEN12_OAG_SCEC[0-7][0-1] */ + { .start =0xdc40 , .end =0xdc40 },/* GEN12_OAG_SPCTR_CNF */ + { .start =0xdc44 , .end =0xdc44 },/* GEN12_OAA_DBG_REG */ + {} +}; + +static const struct i915_range gen7_oa_mux_regs[] = { + { .start =0x91b8 , .end =0x91cc },/* OA_PERFCNT[1-2], OA_PERFMATRIX */ + { .start =0x9800 , .end =0x9888 },/* MICRO_BP0_0 - NOA_WRITE */ + { .start =0xe180 , .end =0xe180 },/* HALF_SLICE_CHICKEN2 */ + {} +}; -static bool gen7_is_valid_mux_addr (struct i915_perf *perf,u32 addr) +static const struct i915_range hsw_oa_mux_regs[] = { + { .start =0x09e80 , .end =0x09ea4 },/* HSW_MBVID2_NOA[0-9] */ + { .start =0x09ec0 , .end =0x09ec0 },/* HSW_MBVID2_MISR0 */ + { .start =0x25100 , .end =0x2ff90 }, + {} +}; + +static const struct i915_range chv_oa_mux_regs[] = { + { .start =0x182300 , .end =0x1823a4 }, + {} +}; + +static const struct i915_range gen8_oa_mux_regs[] = { + { .start =0x0d00 , .end =0x0d2c },/* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */ + { .start =0x20cc , .end =0x20cc },/* WAIT_FOR_RC6_EXIT */ + {} +}; + +static const struct i915_range gen11_oa_mux_regs[] = { + { .start =0x91c8 , .end =0x91dc },/* OA_PERFCNT[3-4] */ + {} +}; + +static const struct i915_range gen12_oa_mux_regs[] = { + { .start =0x0d00 , .end =0x0d2c },/* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */ + { .start =0x9840 , .end =0x9840 },/* GDT_CHICKEN_BITS */ + { .start =0x9884 , .end =0x9888 },/* NOA_WRITE */ + { .start =0x20cc , .end =0x20cc },/* WAIT_FOR_RC6_EXIT */ + {} +}; + +static bool gen7_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) { -return REG_EQUAL (addr,HALF_SLICE_CHICKEN2 ) || -REG_IN_RANGE (addr,MICRO_BP0_0 ,NOA_WRITE ) || -REG_IN_RANGE (addr,OA_PERFCNT1_LO ,OA_PERFCNT2_HI ) || -REG_IN_RANGE (addr,OA_PERFMATRIX_LO ,OA_PERFMATRIX_HI ); +return reg_in_range_table (addr, gen7_oa_b_counters); }static bool gen8_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -REG_EQUAL (addr,WAIT_FOR_RC6_EXIT ) || -REG_IN_RANGE (addr,RPM_CONFIG0 ,NOA_CONFIG (8 )); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, gen8_oa_mux_regs); }static bool gen11_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen8_is_valid_mux_addr (perf, addr) || -REG_EQUAL (addr,GEN10_NOA_WRITE_HIGH ) || -REG_IN_RANGE (addr,OA_PERFCNT3_LO ,OA_PERFCNT4_HI ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, gen8_oa_mux_regs) || +reg_in_range_table (addr, gen11_oa_mux_regs); }static bool hsw_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -ADDR_IN_RANGE (addr,0x25100 ,0x2FF90 ) || -REG_IN_RANGE (addr,HSW_MBVID2_NOA0 ,HSW_MBVID2_NOA9 ) || -REG_EQUAL (addr,HSW_MBVID2_MISR0 ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, hsw_oa_mux_regs); }static bool chv_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -ADDR_IN_RANGE (addr,0x182300 ,0x1823A4 ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, chv_oa_mux_regs); }static bool gen12_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) { -return REG_IN_RANGE (addr,GEN12_OAG_OASTARTTRIG1 ,GEN12_OAG_OASTARTTRIG8 ) || -REG_IN_RANGE (addr,GEN12_OAG_OAREPORTTRIG1 ,GEN12_OAG_OAREPORTTRIG8 ) || -REG_IN_RANGE (addr,GEN12_OAG_CEC0_0 ,GEN12_OAG_CEC7_1 ) || -REG_IN_RANGE (addr,GEN12_OAG_SCEC0_0 ,GEN12_OAG_SCEC7_1 ) || -REG_EQUAL (addr,GEN12_OAA_DBG_REG ) || -REG_EQUAL (addr,GEN12_OAG_OA_PESS ) || -REG_EQUAL (addr,GEN12_OAG_SPCTR_CNF ); +return reg_in_range_table (addr, gen12_oa_b_counters); }static bool gen12_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return REG_EQUAL (addr,NOA_WRITE ) || -REG_EQUAL (addr,GEN10_NOA_WRITE_HIGH ) || -REG_EQUAL (addr,GDT_CHICKEN_BITS ) || -REG_EQUAL (addr,WAIT_FOR_RC6_EXIT ) || -REG_EQUAL (addr,RPM_CONFIG0 ) || -REG_EQUAL (addr,RPM_CONFIG1 ) || -REG_IN_RANGE (addr,NOA_CONFIG (0 ),NOA_CONFIG (8 )); +return reg_in_range_table (addr, gen12_oa_mux_regs); }static u32 mask_reg_value (u32 reg,u32 val)
drivers/gpu/drm/i915/i915_perf_oa_regs.h +0 -360
367 lines not on this page · raw message
Signature · 1 line
2.34.1
Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range
Quoted 8 lines · Matt Roper
Let's use 'struct
i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity.
Quoted 6 lines
v2: Drop 'inline' from
reg_in_range_table(). (Jani)Cc Jani Nikula <[email protected]>Cc Umesh Nerlige Ramappa <[email protected]>Cc Lionel Landwerlin <[email protected]>Signed-off-by Matt Roper <[email protected]>
I didn't come up with an idea to review the table ranges, but agree with the change:
Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range
In reply to Matt RoperQuoted 94 lines · Matt Roper
Let's use 'struct
i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity.v2: Drop 'inline' from
reg_in_range_table(). (Jani)Cc Jani Nikula <[email protected]>Cc Umesh Nerlige Ramappa <[email protected]>Cc Lionel Landwerlin <[email protected]>Signed-off-by Matt Roper <[email protected]>---
drivers/gpu/drm/i915/i915_perf.c| 120 +++++---drivers/gpu/drm/i915/i915_perf_oa_regs.h| 360 -----------------------2 files changed, 77 insertions(+), 403 deletions(-)drivers/gpu/drm/i915/i915_perf.c +48
-13@@ -3864,80 +3864,114 @@ static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)return false; } -#define ADDR_IN_RANGE (addr, start, end) \ - ((addr) >= (start) && \ - (addr) <= (end)) +static bool reg_in_range_table (u32 addr,const struct i915_range *table) { +while (table->start || table->end) { +if (addr >= table->start && addr <= table->end) +return true; + + table++; + } -#define REG_IN_RANGE (addr, start, end) \ - ((addr) >= i915_mmio_reg_offset(start) && \ - (addr) <= i915_mmio_reg_offset(end)) +return false; +}#define REG_EQUAL (addr, mmio) \ ((addr) == i915_mmio_reg_offset(mmio)) -static bool gen7_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) -{ -return REG_IN_RANGE (addr,OASTARTTRIG1 ,OASTARTTRIG8 ) || -REG_IN_RANGE (addr,OAREPORTTRIG1 ,OAREPORTTRIG8 ) || -REG_IN_RANGE (addr,OACEC0_0 ,OACEC7_1 ); -} +static const struct i915_range gen7_oa_b_counters[] = { + { .start =0x2710 , .end =0x272c },/* OASTARTTRIG[1-8] */ + { .start =0x2740 , .end =0x275c },/* OAREPORTTRIG[1-8] */ + { .start =0x2770 , .end =0x27ac },/* OACEC[0-7][0-1] */ + {} +}; + +static const struct i915_range gen12_oa_b_counters[] = { + { .start =0x2b2c , .end =0x2b2c },/* GEN12_OAG_OA_PESS */ + { .start =0xd900 , .end =0xd91c },/* GEN12_OAG_OASTARTTRIG[1-8] */ + { .start =0xd920 , .end =0xd93c },/* GEN12_OAG_OAREPORTTRIG1[1-8] */ + { .start =0xd940 , .end =0xd97c },/* GEN12_OAG_CEC[0-7][0-1] */ + { .start =0xdc00 , .end =0xdc3c },/* GEN12_OAG_SCEC[0-7][0-1] */ + { .start =0xdc40 , .end =0xdc40 },/* GEN12_OAG_SPCTR_CNF */ + { .start =0xdc44 , .end =0xdc44 },/* GEN12_OAA_DBG_REG */ + {} +}; + +static const struct i915_range gen7_oa_mux_regs[] = { + { .start =0x91b8 , .end =0x91cc },/* OA_PERFCNT[1-2], OA_PERFMATRIX */ + { .start =0x9800 , .end =0x9888 },/* MICRO_BP0_0 - NOA_WRITE */ + { .start =0xe180 , .end =0xe180 },/* HALF_SLICE_CHICKEN2 */ + {} +}; -static bool gen7_is_valid_mux_addr (struct i915_perf *perf,u32 addr) +static const struct i915_range hsw_oa_mux_regs[] = { + { .start =0x09e80 , .end =0x09ea4 },/* HSW_MBVID2_NOA[0-9] */ + { .start =0x09ec0 , .end =0x09ec0 },/* HSW_MBVID2_MISR0 */ + { .start =0x25100 , .end =0x2ff90 }, + {} +}; + +static const struct i915_range chv_oa_mux_regs[] = { + { .start =0x182300 , .end =0x1823a4 }, + {} +}; + +static const struct i915_range gen8_oa_mux_regs[] = { + { .start =0x0d00 , .end =0x0d2c },/* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */ + { .start =0x20cc , .end =0x20cc },/* WAIT_FOR_RC6_EXIT */
drivers/gpu/drm/i915/i915_perf.c static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr) · line 3930
Quoted 10 lines
drivers/gpu/drm/i915/i915_perf.c +10
-0+ {} +}; + +static const struct i915_range gen11_oa_mux_regs[] = { + { .start =0x91c8 , .end =0x91dc },/* OA_PERFCNT[3-4] */ + {} +}; + +static const struct i915_range gen12_oa_mux_regs[] = { + { .start =0x0d00 , .end =0x0d2c },/* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
The earlier code does not whitelist 0xd08, so I think we need to split the above.
{ .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
{ .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */Everything else lgtm, With the above, this is
Thanks,
Umesh
Quoted 452 lines
drivers/gpu/drm/i915/i915_perf.c +19
-30+ { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */ + { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */ + { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */ + {} +}; + +static bool gen7_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) { -return REG_EQUAL (addr,HALF_SLICE_CHICKEN2 ) || -REG_IN_RANGE (addr,MICRO_BP0_0 ,NOA_WRITE ) || -REG_IN_RANGE (addr,OA_PERFCNT1_LO ,OA_PERFCNT2_HI ) || -REG_IN_RANGE (addr,OA_PERFMATRIX_LO ,OA_PERFMATRIX_HI ); +return reg_in_range_table (addr, gen7_oa_b_counters); }static bool gen8_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -REG_EQUAL (addr,WAIT_FOR_RC6_EXIT ) || -REG_IN_RANGE (addr,RPM_CONFIG0 ,NOA_CONFIG (8 )); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, gen8_oa_mux_regs); }static bool gen11_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen8_is_valid_mux_addr (perf, addr) || -REG_EQUAL (addr,GEN10_NOA_WRITE_HIGH ) || -REG_IN_RANGE (addr,OA_PERFCNT3_LO ,OA_PERFCNT4_HI ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, gen8_oa_mux_regs) || +reg_in_range_table (addr, gen11_oa_mux_regs); }static bool hsw_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -ADDR_IN_RANGE (addr,0x25100 ,0x2FF90 ) || -REG_IN_RANGE (addr,HSW_MBVID2_NOA0 ,HSW_MBVID2_NOA9 ) || -REG_EQUAL (addr,HSW_MBVID2_MISR0 ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, hsw_oa_mux_regs); }static bool chv_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return gen7_is_valid_mux_addr (perf, addr) || -ADDR_IN_RANGE (addr,0x182300 ,0x1823A4 ); +return reg_in_range_table (addr, gen7_oa_mux_regs) || +reg_in_range_table (addr, chv_oa_mux_regs); }static bool gen12_is_valid_b_counter_addr (struct i915_perf *perf,u32 addr) { -return REG_IN_RANGE (addr,GEN12_OAG_OASTARTTRIG1 ,GEN12_OAG_OASTARTTRIG8 ) || -REG_IN_RANGE (addr,GEN12_OAG_OAREPORTTRIG1 ,GEN12_OAG_OAREPORTTRIG8 ) || -REG_IN_RANGE (addr,GEN12_OAG_CEC0_0 ,GEN12_OAG_CEC7_1 ) || -REG_IN_RANGE (addr,GEN12_OAG_SCEC0_0 ,GEN12_OAG_SCEC7_1 ) || -REG_EQUAL (addr,GEN12_OAA_DBG_REG ) || -REG_EQUAL (addr,GEN12_OAG_OA_PESS ) || -REG_EQUAL (addr,GEN12_OAG_SPCTR_CNF ); +return reg_in_range_table (addr, gen12_oa_b_counters); }static bool gen12_is_valid_mux_addr (struct i915_perf *perf,u32 addr) { -return REG_EQUAL (addr,NOA_WRITE ) || -REG_EQUAL (addr,GEN10_NOA_WRITE_HIGH ) || -REG_EQUAL (addr,GDT_CHICKEN_BITS ) || -REG_EQUAL (addr,WAIT_FOR_RC6_EXIT ) || -REG_EQUAL (addr,RPM_CONFIG0 ) || -REG_EQUAL (addr,RPM_CONFIG1 ) || -REG_IN_RANGE (addr,NOA_CONFIG (0 ),NOA_CONFIG (8 )); +return reg_in_range_table (addr, gen12_oa_mux_regs); }static u32 mask_reg_value (u32 reg,u32 val)drivers/gpu/drm/i915/i915_perf_oa_regs.h +0
-360@@ -131,367 +131,7 @@#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) -/* -* OA Boolean state -*/ - -#define OASTARTTRIG1 _MMIO(0x2710) -#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 -#define OASTARTTRIG1_THRESHOLD_MASK 0xffff - -#define OASTARTTRIG2 _MMIO(0x2714) -#define OASTARTTRIG2_INVERT_A_0 (1 << 0) -#define OASTARTTRIG2_INVERT_A_1 (1 << 1) -#define OASTARTTRIG2_INVERT_A_2 (1 << 2) -#define OASTARTTRIG2_INVERT_A_3 (1 << 3) -#define OASTARTTRIG2_INVERT_A_4 (1 << 4) -#define OASTARTTRIG2_INVERT_A_5 (1 << 5) -#define OASTARTTRIG2_INVERT_A_6 (1 << 6) -#define OASTARTTRIG2_INVERT_A_7 (1 << 7) -#define OASTARTTRIG2_INVERT_A_8 (1 << 8) -#define OASTARTTRIG2_INVERT_A_9 (1 << 9) -#define OASTARTTRIG2_INVERT_A_10 (1 << 10) -#define OASTARTTRIG2_INVERT_A_11 (1 << 11) -#define OASTARTTRIG2_INVERT_A_12 (1 << 12) -#define OASTARTTRIG2_INVERT_A_13 (1 << 13) -#define OASTARTTRIG2_INVERT_A_14 (1 << 14) -#define OASTARTTRIG2_INVERT_A_15 (1 << 15) -#define OASTARTTRIG2_INVERT_B_0 (1 << 16) -#define OASTARTTRIG2_INVERT_B_1 (1 << 17) -#define OASTARTTRIG2_INVERT_B_2 (1 << 18) -#define OASTARTTRIG2_INVERT_B_3 (1 << 19) -#define OASTARTTRIG2_INVERT_C_0 (1 << 20) -#define OASTARTTRIG2_INVERT_C_1 (1 << 21) -#define OASTARTTRIG2_INVERT_D_0 (1 << 22) -#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) -#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) -#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) -#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) -#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) -#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) - -#define OASTARTTRIG3 _MMIO(0x2718) -#define OASTARTTRIG3_NOA_SELECT_MASK 0xf -#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 -#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 -#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 -#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 -#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 -#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 -#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 -#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 - -#define OASTARTTRIG4 _MMIO(0x271c) -#define OASTARTTRIG4_NOA_SELECT_MASK 0xf -#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 -#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 -#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 -#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 -#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 -#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 -#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 -#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 - -#define OASTARTTRIG5 _MMIO(0x2720) -#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 -#define OASTARTTRIG5_THRESHOLD_MASK 0xffff - -#define OASTARTTRIG6 _MMIO(0x2724) -#define OASTARTTRIG6_INVERT_A_0 (1 << 0) -#define OASTARTTRIG6_INVERT_A_1 (1 << 1) -#define OASTARTTRIG6_INVERT_A_2 (1 << 2) -#define OASTARTTRIG6_INVERT_A_3 (1 << 3) -#define OASTARTTRIG6_INVERT_A_4 (1 << 4) -#define OASTARTTRIG6_INVERT_A_5 (1 << 5) -#define OASTARTTRIG6_INVERT_A_6 (1 << 6) -#define OASTARTTRIG6_INVERT_A_7 (1 << 7) -#define OASTARTTRIG6_INVERT_A_8 (1 << 8) -#define OASTARTTRIG6_INVERT_A_9 (1 << 9) -#define OASTARTTRIG6_INVERT_A_10 (1 << 10) -#define OASTARTTRIG6_INVERT_A_11 (1 << 11) -#define OASTARTTRIG6_INVERT_A_12 (1 << 12) -#define OASTARTTRIG6_INVERT_A_13 (1 << 13) -#define OASTARTTRIG6_INVERT_A_14 (1 << 14) -#define OASTARTTRIG6_INVERT_A_15 (1 << 15) -#define OASTARTTRIG6_INVERT_B_0 (1 << 16) -#define OASTARTTRIG6_INVERT_B_1 (1 << 17) -#define OASTARTTRIG6_INVERT_B_2 (1 << 18) -#define OASTARTTRIG6_INVERT_B_3 (1 << 19) -#define OASTARTTRIG6_INVERT_C_0 (1 << 20) -#define OASTARTTRIG6_INVERT_C_1 (1 << 21) -#define OASTARTTRIG6_INVERT_D_0 (1 << 22) -#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) -#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) -#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) -#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) -#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) -#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) - -#define OASTARTTRIG7 _MMIO(0x2728) -#define OASTARTTRIG7_NOA_SELECT_MASK 0xf -#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 -#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 -#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 -#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 -#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 -#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 -#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 -#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 - -#define OASTARTTRIG8 _MMIO(0x272c) -#define OASTARTTRIG8_NOA_SELECT_MASK 0xf -#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 -#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 -#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 -#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 -#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 -#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 -#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 -#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 - -#define OAREPORTTRIG1 _MMIO(0x2740) -#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000/* 0=level */ - -#define OAREPORTTRIG2 _MMIO(0x2744) -#define OAREPORTTRIG2_INVERT_A_0 (1 << 0) -#define OAREPORTTRIG2_INVERT_A_1 (1 << 1) -#define OAREPORTTRIG2_INVERT_A_2 (1 << 2) -#define OAREPORTTRIG2_INVERT_A_3 (1 << 3) -#define OAREPORTTRIG2_INVERT_A_4 (1 << 4) -#define OAREPORTTRIG2_INVERT_A_5 (1 << 5) -#define OAREPORTTRIG2_INVERT_A_6 (1 << 6) -#define OAREPORTTRIG2_INVERT_A_7 (1 << 7) -#define OAREPORTTRIG2_INVERT_A_8 (1 << 8) -#define OAREPORTTRIG2_INVERT_A_9 (1 << 9) -#define OAREPORTTRIG2_INVERT_A_10 (1 << 10) -#define OAREPORTTRIG2_INVERT_A_11 (1 << 11) -#define OAREPORTTRIG2_INVERT_A_12 (1 << 12) -#define OAREPORTTRIG2_INVERT_A_13 (1 << 13) -#define OAREPORTTRIG2_INVERT_A_14 (1 << 14) -#define OAREPORTTRIG2_INVERT_A_15 (1 << 15) -#define OAREPORTTRIG2_INVERT_B_0 (1 << 16) -#define OAREPORTTRIG2_INVERT_B_1 (1 << 17) -#define OAREPORTTRIG2_INVERT_B_2 (1 << 18) -#define OAREPORTTRIG2_INVERT_B_3 (1 << 19) -#define OAREPORTTRIG2_INVERT_C_0 (1 << 20) -#define OAREPORTTRIG2_INVERT_C_1 (1 << 21) -#define OAREPORTTRIG2_INVERT_D_0 (1 << 22) -#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) -#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) - -#define OAREPORTTRIG3 _MMIO(0x2748) -#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG4 _MMIO(0x274c) -#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 - -#define OAREPORTTRIG5 _MMIO(0x2750) -#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000/* 0=level */ - -#define OAREPORTTRIG6 _MMIO(0x2754) -#define OAREPORTTRIG6_INVERT_A_0 (1 << 0) -#define OAREPORTTRIG6_INVERT_A_1 (1 << 1) -#define OAREPORTTRIG6_INVERT_A_2 (1 << 2) -#define OAREPORTTRIG6_INVERT_A_3 (1 << 3) -#define OAREPORTTRIG6_INVERT_A_4 (1 << 4) -#define OAREPORTTRIG6_INVERT_A_5 (1 << 5) -#define OAREPORTTRIG6_INVERT_A_6 (1 << 6) -#define OAREPORTTRIG6_INVERT_A_7 (1 << 7) -#define OAREPORTTRIG6_INVERT_A_8 (1 << 8) -#define OAREPORTTRIG6_INVERT_A_9 (1 << 9) -#define OAREPORTTRIG6_INVERT_A_10 (1 << 10) -#define OAREPORTTRIG6_INVERT_A_11 (1 << 11) -#define OAREPORTTRIG6_INVERT_A_12 (1 << 12) -#define OAREPORTTRIG6_INVERT_A_13 (1 << 13) -#define OAREPORTTRIG6_INVERT_A_14 (1 << 14) -#define OAREPORTTRIG6_INVERT_A_15 (1 << 15) -#define OAREPORTTRIG6_INVERT_B_0 (1 << 16) -#define OAREPORTTRIG6_INVERT_B_1 (1 << 17) -#define OAREPORTTRIG6_INVERT_B_2 (1 << 18) -#define OAREPORTTRIG6_INVERT_B_3 (1 << 19) -#define OAREPORTTRIG6_INVERT_C_0 (1 << 20) -#define OAREPORTTRIG6_INVERT_C_1 (1 << 21) -#define OAREPORTTRIG6_INVERT_D_0 (1 << 22) -#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) -#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) - -#define OAREPORTTRIG7 _MMIO(0x2758) -#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG8 _MMIO(0x275c) -#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 - -/* Same layout as OASTARTTRIGX */ -#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900) -#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904) -#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908) -#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c) -#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910) -#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914) -#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918) -#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c) - -/* Same layout as OAREPORTTRIGX */ -#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920) -#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924) -#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928) -#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c) -#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930) -#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934) -#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938) -#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c) - -/* CECX_0 */ -#define OACEC_COMPARE_LESS_OR_EQUAL 6 -#define OACEC_COMPARE_NOT_EQUAL 5 -#define OACEC_COMPARE_LESS_THAN 4 -#define OACEC_COMPARE_GREATER_OR_EQUAL 3 -#define OACEC_COMPARE_EQUAL 2 -#define OACEC_COMPARE_GREATER_THAN 1 -#define OACEC_COMPARE_ANY_EQUAL 0 - -#define OACEC_COMPARE_VALUE_MASK 0xffff -#define OACEC_COMPARE_VALUE_SHIFT 3 - -#define OACEC_SELECT_NOA (0 << 19) -#define OACEC_SELECT_PREV (1 << 19) -#define OACEC_SELECT_BOOLEAN (2 << 19) - -/* 11-bit array 0: pass-through, 1: negated */ -#define GEN12_OASCEC_NEGATE_MASK 0x7ff -#define GEN12_OASCEC_NEGATE_SHIFT 21 - -/* CECX_1 */ -#define OACEC_MASK_MASK 0xffff -#define OACEC_CONSIDERATIONS_MASK 0xffff -#define OACEC_CONSIDERATIONS_SHIFT 16 - -#define OACEC0_0 _MMIO(0x2770) -#define OACEC0_1 _MMIO(0x2774) -#define OACEC1_0 _MMIO(0x2778) -#define OACEC1_1 _MMIO(0x277c) -#define OACEC2_0 _MMIO(0x2780) -#define OACEC2_1 _MMIO(0x2784) -#define OACEC3_0 _MMIO(0x2788) -#define OACEC3_1 _MMIO(0x278c) -#define OACEC4_0 _MMIO(0x2790) -#define OACEC4_1 _MMIO(0x2794) -#define OACEC5_0 _MMIO(0x2798) -#define OACEC5_1 _MMIO(0x279c) -#define OACEC6_0 _MMIO(0x27a0) -#define OACEC6_1 _MMIO(0x27a4) -#define OACEC7_0 _MMIO(0x27a8) -#define OACEC7_1 _MMIO(0x27ac) - -/* Same layout as CECX_Y */ -#define GEN12_OAG_CEC0_0 _MMIO(0xd940) -#define GEN12_OAG_CEC0_1 _MMIO(0xd944) -#define GEN12_OAG_CEC1_0 _MMIO(0xd948) -#define GEN12_OAG_CEC1_1 _MMIO(0xd94c) -#define GEN12_OAG_CEC2_0 _MMIO(0xd950) -#define GEN12_OAG_CEC2_1 _MMIO(0xd954) -#define GEN12_OAG_CEC3_0 _MMIO(0xd958) -#define GEN12_OAG_CEC3_1 _MMIO(0xd95c) -#define GEN12_OAG_CEC4_0 _MMIO(0xd960) -#define GEN12_OAG_CEC4_1 _MMIO(0xd964) -#define GEN12_OAG_CEC5_0 _MMIO(0xd968) -#define GEN12_OAG_CEC5_1 _MMIO(0xd96c) -#define GEN12_OAG_CEC6_0 _MMIO(0xd970) -#define GEN12_OAG_CEC6_1 _MMIO(0xd974) -#define GEN12_OAG_CEC7_0 _MMIO(0xd978) -#define GEN12_OAG_CEC7_1 _MMIO(0xd97c) - -/* Same layout as CECX_Y + negate 11-bit array */ -#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00) -#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04) -#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08) -#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c) -#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10) -#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14) -#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18) -#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c) -#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20) -#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24) -#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28) -#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c) -#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30) -#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34) -#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38) -#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c) - -/* OA perf counters */ -#define OA_PERFCNT1_LO _MMIO(0x91B8) -#define OA_PERFCNT1_HI _MMIO(0x91BC) -#define OA_PERFCNT2_LO _MMIO(0x91C0) -#define OA_PERFCNT2_HI _MMIO(0x91C4) -#define OA_PERFCNT3_LO _MMIO(0x91C8) -#define OA_PERFCNT3_HI _MMIO(0x91CC) -#define OA_PERFCNT4_LO _MMIO(0x91D8) -#define OA_PERFCNT4_HI _MMIO(0x91DC) - -#define OA_PERFMATRIX_LO _MMIO(0x91C8) -#define OA_PERFMATRIX_HI _MMIO(0x91CC) - -/* NOA (HSW) */ -#define HSW_MBVID2_NOA0 _MMIO(0x9E80) -#define HSW_MBVID2_NOA1 _MMIO(0x9E84) -#define HSW_MBVID2_NOA2 _MMIO(0x9E88) -#define HSW_MBVID2_NOA3 _MMIO(0x9E8C) -#define HSW_MBVID2_NOA4 _MMIO(0x9E90) -#define HSW_MBVID2_NOA5 _MMIO(0x9E94) -#define HSW_MBVID2_NOA6 _MMIO(0x9E98) -#define HSW_MBVID2_NOA7 _MMIO(0x9E9C) -#define HSW_MBVID2_NOA8 _MMIO(0x9EA0) -#define HSW_MBVID2_NOA9 _MMIO(0x9EA4) - -#define HSW_MBVID2_MISR0 _MMIO(0x9EC0) - -/* NOA (Gen8+) */ -#define NOA_CONFIG (i) _MMIO(0x0D0C + (i) * 4) - -#define GEN12_OAA_DBG_REG _MMIO(0xdc44) -#define GEN12_OAG_OA_PESS _MMIO(0x2b2c) -#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40) -#define GDT_CHICKEN_BITS _MMIO(0x9840)#define GT_NOA_ENABLE 0x00000080 -#define NOA_DATA _MMIO(0x986C) -#define NOA_WRITE _MMIO(0x9888) -#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) -#endif /* __INTEL_PERF_OA_REGS__ */ Signature · 1 line
2.34.1
PATCH v2 3/6 drm/i915: Parameterize R_PWR_CLK_STATE register definition
In reply to Matt RoperAt the moment we only use R_PWR_CLK_STATE in the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header.
--- .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 ++- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 15 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 15 --------------- 5 files changed, 20 insertions(+), 19 deletions(-)
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +2 -1
@@ -8,6 +8,7 @@#include "gem/i915_gem_pm.h" #include "gt/intel_engine_pm.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" #include "gt/intel_reset.h"
@@ -894,7 +895,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vreturn PTR_ERR (cmd); *cmd++ =MI_STORE_REGISTER_MEM_GEN8 ; - *cmd++ =i915_mmio_reg_offset (GEN8_R_PWR_CLK_STATE ); + *cmd++ =i915_mmio_reg_offset (GEN8_R_PWR_CLK_STATE (RENDER_RING_BASE )); *cmd++ =lower_32_bits (vma->node.start); *cmd++ =upper_32_bits (vma->node.start); *cmd =MI_BATCH_BUFFER_END ;
drivers/gpu/drm/i915/gt/intel_engine_regs.h +15 -0
@@ -77,6 +77,21 @@#define RING_INSTPM (base) _MMIO((base) + 0xc0)#define RING_CMD_CCTL (base) _MMIO((base) + 0xc4)#define ACTHD (base) _MMIO((base) + 0xc8) +#define GEN8_R_PWR_CLK_STATE (base) _MMIO((base) + 0xc8) +#define GEN8_RPCS_ENABLE (1 << 31) +#define GEN8_RPCS_S_CNT_ENABLE (1 << 18) +#define GEN8_RPCS_S_CNT_SHIFT 15 +#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) +#define GEN11_RPCS_S_CNT_SHIFT 12 +#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) +#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) +#define GEN8_RPCS_SS_CNT_SHIFT 8 +#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) +#define GEN8_RPCS_EU_MAX_SHIFT 4 +#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) +#define GEN8_RPCS_EU_MIN_SHIFT 0 +#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) +#define RING_RESET_CTL (base) _MMIO((base) + 0xd0)#define RESET_CTL_CAT_ERROR REG_BIT(2)#define RESET_CTL_READY_TO_RESET REG_BIT(1)
drivers/gpu/drm/i915/gt/intel_sseu.c +1 -1
@@ -4,7 +4,7 @@*/ #include "i915_drv.h" -#include "intel_lrc_reg.h" +#include "intel_engine_regs.h" #include "intel_sseu.h" void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
drivers/gpu/drm/i915/i915_perf.c +2 -2
@@ -2420,7 +2420,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream, {struct flex regs[] = { { -GEN8_R_PWR_CLK_STATE , +GEN8_R_PWR_CLK_STATE (RENDER_RING_BASE ),CTX_R_PWR_CLK_STATE , }, };
@@ -2440,7 +2440,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream,#define ctx_flexeuN (N ) (ctx_flexeu0 + 2 * (N) + 1)struct flex regs[] = { { -GEN8_R_PWR_CLK_STATE , +GEN8_R_PWR_CLK_STATE (RENDER_RING_BASE ),CTX_R_PWR_CLK_STATE , }, {
drivers/gpu/drm/i915/i915_reg.h +0 -15
@@ -272,21 +272,6 @@#define GEN12_SFC_DONE (n) _MMIO(0x1cc000 + (n) * 0x1000)#define GEN12_SFC_DONE_MAX 4 -#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) -#define GEN8_RPCS_ENABLE (1 << 31) -#define GEN8_RPCS_S_CNT_ENABLE (1 << 18) -#define GEN8_RPCS_S_CNT_SHIFT 15 -#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) -#define GEN11_RPCS_S_CNT_SHIFT 12 -#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) -#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) -#define GEN8_RPCS_SS_CNT_SHIFT 8 -#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) -#define GEN8_RPCS_EU_MAX_SHIFT 4 -#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) -#define GEN8_RPCS_EU_MIN_SHIFT 0 -#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) -#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)/* HSW only */ #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
Signature · 1 line
2.34.1
Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition
Quoted 7 lines · Matt Roper
At the moment we only use
R_PWR_CLK_STATEin the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header.Cc Jani Nikula <[email protected]>Signed-off-by Matt Roper <[email protected]>
Lucas De Marchi
PATCH v2 4/6 drm/i915: Parameterize MI_PREDICATE registers
In reply to Matt RoperThe various MI_PREDICATE registers have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward.
Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in the driver today in HSW-specific code. It turns out that the bspec (page 94) lists two different offsets for this register on HSW; one is in the standard location shared by all other platforms (base + 0x3bc) and the other is an unusual location (0x2214). We're using the second, non-standard offset in i915 today; that offset doesn't exist on any other platforms (and it's not even 100% clear that it's correct for HSW) so I've renamed the current non-standard definition to HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro (which is still unused at the moment) uses the standard offset.
--- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/i915_perf.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 11 +---------- 5 files changed, 19 insertions(+), 17 deletions(-)
drivers/gpu/drm/i915/gt/intel_engine_regs.h +11 -0
@@ -142,6 +142,17 @@ (REG_FIELD_PREP (CMD_CCTL_WRITE_OVERRIDE_MASK , (write) <<1 ) | \ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) +#define MI_PREDICATE_RESULT_2 (base) _MMIO((base) + 0x3bc) +#define LOWER_SLICE_ENABLED (1 << 0) +#define LOWER_SLICE_DISABLED (0 << 0) +#define MI_PREDICATE_SRC0 (base) _MMIO((base) + 0x400) +#define MI_PREDICATE_SRC0_UDW (base) _MMIO((base) + 0x400 + 4) +#define MI_PREDICATE_SRC1 (base) _MMIO((base) + 0x408) +#define MI_PREDICATE_SRC1_UDW (base) _MMIO((base) + 0x408 + 4) +#define MI_PREDICATE_DATA (base) _MMIO((base) + 0x410) +#define MI_PREDICATE_RESULT (base) _MMIO((base) + 0x418) +#define MI_PREDICATE_RESULT_1 (base) _MMIO((base) + 0x41c) +#define RING_PP_DIR_DCLV (base) _MMIO((base) + 0x220)#define PP_DIR_DCLV_2G 0xffffffff#define RING_PP_DIR_BASE (base) _MMIO((base) + 0x228)
drivers/gpu/drm/i915/gt/intel_gt.c +1 -1
@@ -209,7 +209,7 @@ int intel_gt_init_hw(struct intel_gt *gt)if (IS_HASWELL (i915))intel_uncore_write (uncore, -MI_PREDICATE_RESULT_2 , +HSW_MI_PREDICATE_RESULT_2 ,IS_HSW_GT3 (i915) ?LOWER_SLICE_ENABLED :LOWER_SLICE_DISABLED );
drivers/gpu/drm/i915/i915_cmd_parser.c +2 -2
@@ -611,8 +611,8 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {REG64 (PS_INVOCATION_COUNT ),REG64 (PS_DEPTH_COUNT ),REG64_IDX (RING_TIMESTAMP ,RENDER_RING_BASE ), -REG64 (MI_PREDICATE_SRC0 ), -REG64 (MI_PREDICATE_SRC1 ), +REG64_IDX (MI_PREDICATE_SRC0 ,RENDER_RING_BASE ), +REG64_IDX (MI_PREDICATE_SRC1 ,RENDER_RING_BASE ),REG32 (GEN7_3DPRIM_END_OFFSET ),REG32 (GEN7_3DPRIM_START_VERTEX ), REG32(GEN7_3DPRIM_VERTEX_COUNT),
drivers/gpu/drm/i915/i915_perf.c +4 -4
@@ -1684,7 +1684,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) stream, cs, true/* save */ ,CS_GPR (i), INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2); cs =save_restore_register ( - stream, cs, true/* save */ ,MI_PREDICATE_RESULT_1 , + stream, cs, true/* save */ ,MI_PREDICATE_RESULT_1 (RENDER_RING_BASE ),INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 ,1 );/* First timestamp snapshot location. */
@@ -1738,7 +1738,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)*/ *cs++ =MI_LOAD_REGISTER_REG | (3 -2 ); *cs++ =i915_mmio_reg_offset (CS_GPR (JUMP_PREDICATE )); - *cs++ =i915_mmio_reg_offset (MI_PREDICATE_RESULT_1 ); + *cs++ =i915_mmio_reg_offset (MI_PREDICATE_RESULT_1 (RENDER_RING_BASE ));/* Restart from the beginning if we had timestamps roll over. */ *cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1775,7 +1775,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)*/ *cs++ =MI_LOAD_REGISTER_REG | (3 -2 ); *cs++ =i915_mmio_reg_offset (CS_GPR (JUMP_PREDICATE )); - *cs++ =i915_mmio_reg_offset (MI_PREDICATE_RESULT_1 ); + *cs++ =i915_mmio_reg_offset (MI_PREDICATE_RESULT_1 (RENDER_RING_BASE ));/* Predicate the jump. */ *cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1791,7 +1791,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream) stream, cs, false/* restore */ ,CS_GPR (i), INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2); cs =save_restore_register ( - stream, cs, false/* restore */ ,MI_PREDICATE_RESULT_1 , + stream, cs, false/* restore */ ,MI_PREDICATE_RESULT_1 (RENDER_RING_BASE ),INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 ,1 );/* And return to the ring. */
drivers/gpu/drm/i915/i915_reg.h +1 -10
@@ -398,16 +398,7 @@#define VGA_CR_INDEX_CGA 0x3d4#define VGA_CR_DATA_CGA 0x3d5 -#define MI_PREDICATE_SRC0 _MMIO(0x2400) -#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) -#define MI_PREDICATE_SRC1 _MMIO(0x2408) -#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) -#define MI_PREDICATE_DATA _MMIO(0x2410) -#define MI_PREDICATE_RESULT _MMIO(0x2418) -#define MI_PREDICATE_RESULT_1 _MMIO(0x241c) -#define MI_PREDICATE_RESULT_2 _MMIO(0x2214) -#define LOWER_SLICE_ENABLED (1 << 0) -#define LOWER_SLICE_DISABLED (0 << 0) +#define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)/* * Registers used only by the command parser
Signature · 1 line
2.34.1
Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers
Quoted 16 lines · Matt Roper
The various
MI_PREDICATEregisters have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward.Of special note is
MI_PREDICATE_RESULT_2; we only use it in one place in the driver today in HSW-specific code. It turns out that the bspec (page 94) lists two different offsets for this register on HSW; one is in the standard location shared by all other platforms (base +0x3bc) and the other is an unusual location (0x2214). We're using the second, non-standard offset in i915 today; that offset doesn't exist on any other platforms (and it's not even 100% clear that it's correct for HSW) so I've renamed the current non-standard definition toHSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro (which is still unused at the moment) uses the standard offset.
Quoted 2 lines
Cc Jani Nikula <[email protected]>Signed-off-by Matt Roper <[email protected]>
Lucas De Marchi
PATCH v2 5/6 drm/i915: Move GT registers to their own header file
In reply to Matt RoperThis is a huge, chaotic mass of registers copied over as-is without any real cleanup. We'll come back and organize these better, align on consistent coding style, remove dead code, etc. in separate patches later that will be easier to review.
v2:
- Add missing include in intel_pxp_irq.c
--- .../i915/gem/selftests/i915_gem_client_blt.c | 3 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + .../drm/i915/gt/intel_execlists_submission.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 1 + .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1542 ++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 2 + .../gpu/drm/i915/gt/intel_ring_submission.c | 1 + drivers/gpu/drm/i915/gt/intel_rps.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 1 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/gtt.c | 2 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/gvt/mmio.c | 2 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 1544 ----------------- drivers/gpu/drm/i915/i915_sysfs.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + drivers/gpu/drm/i915/intel_uncore.c | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 + drivers/gpu/drm/i915/vlv_suspend.c | 2 + 47 files changed, 1593 insertions(+), 1548 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +2 -1
@@ -7,8 +7,9 @@#include "gt/intel_context.h" #include "gt/intel_engine_user.h" -#include "gt/intel_gt.h" #include "gt/intel_gpu_commands.h" +#include "gt/intel_gt.h" +#include "gt/intel_gt_regs.h" #include "gem/i915_gem_lmem.h" #include "selftests/igt_flush_test.h"
drivers/gpu/drm/i915/gt/gen6_ppgtt.c +1 -0
@@ -9,6 +9,7 @@#include "i915_scatterlist.h" #include "i915_trace.h" #include "i915_vgpu.h" +#include "intel_gt_regs.h" #include "intel_engine_regs.h" #include "intel_gt.h"
drivers/gpu/drm/i915/gt/gen7_renderclear.c +1 -0
@@ -6,6 +6,7 @@#include "gen7_renderclear.h" #include "i915_drv.h" #include "intel_gpu_commands.h" +#include "intel_gt_regs.h" #define GT3_INLINE_DATA_DELAYS 0x1E00#define batch_advance (Y ,CS ) GEM_BUG_ON((Y)->end != (CS))
drivers/gpu/drm/i915/gt/gen8_engine_cs.c +2 -1
@@ -5,8 +5,9 @@#include "gen8_engine_cs.h" #include "i915_drv.h" -#include "intel_lrc.h" #include "intel_gpu_commands.h" +#include "intel_gt_regs.h" +#include "intel_lrc.h" #include "intel_ring.h" int gen8_emit_flush_rcs (struct i915_request *rq,u32 mode)
drivers/gpu/drm/i915/gt/intel_engine_cs.c +1 -0
@@ -6,6 +6,7 @@#include <drm/drm_print.h> #include "gem/i915_gem_context.h" +#include "gt/intel_gt_regs.h" #include "i915_cmd_parser.h" #include "i915_drv.h"
drivers/gpu/drm/i915/gt/intel_execlists_submission.c +1 -0
@@ -122,6 +122,7 @@#include "intel_gt.h" #include "intel_gt_irq.h" #include "intel_gt_pm.h" +#include "intel_gt_regs.h" #include "intel_gt_requests.h" #include "intel_lrc.h" #include "intel_lrc_reg.h"
drivers/gpu/drm/i915/gt/intel_ggtt.c +1 -0
@@ -15,6 +15,7 @@#include "gem/i915_gem_lmem.h" #include "intel_gt.h" +#include "intel_gt_regs.h" #include "i915_drv.h" #include "i915_scatterlist.h" #include "i915_vgpu.h"
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +1 -0
@@ -7,6 +7,7 @@#include "i915_scatterlist.h" #include "i915_pvinfo.h" #include "i915_vgpu.h" +#include "intel_gt_regs.h" /** * DOC: fence register handling
drivers/gpu/drm/i915/gt/intel_gt.c +1 -0
@@ -16,6 +16,7 @@#include "intel_gt_buffer_pool.h" #include "intel_gt_clock_utils.h" #include "intel_gt_pm.h" +#include "intel_gt_regs.h" #include "intel_gt_requests.h" #include "intel_migrate.h" #include "intel_mocs.h"
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +1 -0
@@ -6,6 +6,7 @@#include "i915_drv.h" #include "intel_gt.h" #include "intel_gt_clock_utils.h" +#include "intel_gt_regs.h" static u32 read_reference_ts_freq (struct intel_uncore *uncore) {
drivers/gpu/drm/i915/gt/intel_gt_irq.c +1 -1
@@ -10,7 +10,7 @@#include "intel_breadcrumbs.h" #include "intel_gt.h" #include "intel_gt_irq.h" -#include "intel_lrc_reg.h" +#include "intel_gt_regs.h" #include "intel_uncore.h" #include "intel_rps.h" #include "pxp/intel_pxp_irq.h"
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +1 -0
@@ -12,6 +12,7 @@#include "intel_gt_debugfs.h" #include "intel_gt_pm.h" #include "intel_gt_pm_debugfs.h" +#include "intel_gt_regs.h" #include "intel_llc.h" #include "intel_pcode.h" #include "intel_rc6.h"
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c +1 -0
@@ -8,6 +8,7 @@#include "intel_gt.h" #include "intel_gt_irq.h" #include "intel_gt_pm_irq.h" +#include "intel_gt_regs.h" static void write_pm_imr (struct intel_gt *gt) {
drivers/gpu/drm/i915/gt/intel_gt_regs.h new file +1542 -0
1,542 lines not on this page · raw message
drivers/gpu/drm/i915/gt/intel_gtt.c +1 -0
@@ -13,6 +13,7 @@#include "gem/i915_gem_lmem.h" #include "i915_trace.h" #include "intel_gt.h" +#include "intel_gt_regs.h" #include "intel_gtt.h" struct drm_i915_gem_object *alloc_pt_lmem (struct i915_address_space *vm,int sz)
drivers/gpu/drm/i915/gt/intel_lrc.c +1 -0
@@ -12,6 +12,7 @@#include "intel_engine_regs.h" #include "intel_gpu_commands.h" #include "intel_gt.h" +#include "intel_gt_regs.h" #include "intel_lrc.h" #include "intel_lrc_reg.h" #include "intel_ring.h"
drivers/gpu/drm/i915/gt/intel_mocs.c +1 -1
@@ -7,7 +7,7 @@#include "intel_engine.h" #include "intel_gt.h" -#include "intel_lrc_reg.h" +#include "intel_gt_regs.h" #include "intel_mocs.h" #include "intel_ring.h"
drivers/gpu/drm/i915/gt/intel_rc6.c +1 -0
@@ -10,6 +10,7 @@#include "intel_engine_regs.h" #include "intel_gt.h" #include "intel_gt_pm.h" +#include "intel_gt_regs.h" #include "intel_pcode.h" #include "intel_rc6.h"
drivers/gpu/drm/i915/gt/intel_reset.c +2 -0
@@ -11,6 +11,8 @@#include "gem/i915_gem_context.h" +#include "gt/intel_gt_regs.h" +#include "i915_drv.h" #include "i915_gpu_error.h" #include "i915_irq.h"
drivers/gpu/drm/i915/gt/intel_ring_submission.c +1 -0
@@ -14,6 +14,7 @@#include "intel_engine_regs.h" #include "intel_gt.h" #include "intel_gt_irq.h" +#include "intel_gt_regs.h" #include "intel_reset.h" #include "intel_ring.h" #include "shmem_utils.h"
drivers/gpu/drm/i915/gt/intel_rps.c +1 -0
@@ -12,6 +12,7 @@#include "intel_gt_clock_utils.h" #include "intel_gt_irq.h" #include "intel_gt_pm_irq.h" +#include "intel_gt_regs.h" #include "intel_pcode.h" #include "intel_rps.h" #include "vlv_sideband.h"
drivers/gpu/drm/i915/gt/intel_sseu.c +1 -0
@@ -5,6 +5,7 @@#include "i915_drv.h" #include "intel_engine_regs.h" +#include "intel_gt_regs.h" #include "intel_sseu.h" void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +1 -0
@@ -6,6 +6,7 @@#include "i915_drv.h" #include "intel_gt_debugfs.h" +#include "intel_gt_regs.h" #include "intel_sseu_debugfs.h" static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
drivers/gpu/drm/i915/gt/intel_workarounds.c +1 -0
@@ -9,6 +9,7 @@#include "intel_engine_regs.h" #include "intel_gpu_commands.h" #include "intel_gt.h" +#include "intel_gt_regs.h" #include "intel_ring.h" #include "intel_workarounds.h"
drivers/gpu/drm/i915/gt/uc/intel_guc.c +1 -0
@@ -7,6 +7,7 @@#include "gt/intel_gt.h" #include "gt/intel_gt_irq.h" #include "gt/intel_gt_pm_irq.h" +#include "gt/intel_gt_regs.h" #include "intel_guc.h" #include "intel_guc_slpc.h" #include "intel_guc_ads.h"
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +1 -0
@@ -7,6 +7,7 @@#include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/shmem_utils.h" #include "intel_guc_ads.h"
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c +1 -0
@@ -10,6 +10,7 @@*/ #include "gt/intel_gt.h" +#include "gt/intel_gt_regs.h" #include "intel_guc_fw.h" #include "i915_drv.h"
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +1 -0
@@ -6,6 +6,7 @@#include "i915_drv.h" #include "intel_guc_slpc.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_regs.h" static inline struct intel_guc *slpc_to_guc (struct intel_guc_slpc *slpc) {
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +1 -0
@@ -17,6 +17,7 @@#include "gt/intel_gt_clock_utils.h" #include "gt/intel_gt_irq.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_gt_requests.h" #include "gt/intel_lrc.h" #include "gt/intel_lrc_reg.h"
drivers/gpu/drm/i915/gvt/cmd_parser.c +1 -0
@@ -39,6 +39,7 @@#include "i915_drv.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gpu_commands.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/intel_ring.h" #include "gt/intel_gt_requests.h"
drivers/gpu/drm/i915/gvt/gtt.c +2 -0
@@ -38,6 +38,8 @@#include "i915_pvinfo.h" #include "trace.h" +#include "gt/intel_gt_regs.h" +#if defined(VERBOSE_DEBUG ) #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)#else
drivers/gpu/drm/i915/gvt/handlers.c +1 -0
@@ -41,6 +41,7 @@#include "i915_pvinfo.h" #include "display/intel_display_types.h" #include "display/intel_fbc.h" +#include "gt/intel_gt_regs.h" /* XXX FIXME i915 has changed PP_XXX definition */ #define PCH_PP_STATUS _MMIO(0xc7200)
drivers/gpu/drm/i915/gvt/mmio.c +2 -0
@@ -36,6 +36,8 @@#include "i915_drv.h" #include "gvt.h" +#include "gt/intel_gt_regs.h" +/** * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset * @vgpu: a vGPU
drivers/gpu/drm/i915/gvt/mmio_context.c +1 -0
@@ -37,6 +37,7 @@#include "gt/intel_context.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gpu_commands.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_ring.h" #include "gvt.h" #include "trace.h"
drivers/gpu/drm/i915/gvt/scheduler.c +1 -0
@@ -38,6 +38,7 @@#include "gem/i915_gem_pm.h" #include "gt/intel_context.h" #include "gt/intel_execlists_submission.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/intel_ring.h"
drivers/gpu/drm/i915/i915_cmd_parser.c +1 -0
@@ -28,6 +28,7 @@#include "gt/intel_engine.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gpu_commands.h" +#include "gt/intel_gt_regs.h" #include "i915_cmd_parser.h" #include "i915_drv.h"
drivers/gpu/drm/i915/i915_debugfs.c +1 -0
@@ -38,6 +38,7 @@#include "gt/intel_gt_debugfs.h" #include "gt/intel_gt_pm.h" #include "gt/intel_gt_pm_debugfs.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_gt_requests.h" #include "gt/intel_rc6.h" #include "gt/intel_reset.h"
drivers/gpu/drm/i915/i915_gpu_error.c +1 -0
@@ -44,6 +44,7 @@#include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "i915_drv.h" #include "i915_gpu_error.h"
drivers/gpu/drm/i915/i915_irq.c +1 -0
@@ -46,6 +46,7 @@#include "gt/intel_gt.h" #include "gt/intel_gt_irq.h" #include "gt/intel_gt_pm_irq.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_rps.h" #include "i915_drv.h"
drivers/gpu/drm/i915/i915_perf.c +1 -0
@@ -203,6 +203,7 @@#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "gt/intel_gt_clock_utils.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/intel_ring.h"
drivers/gpu/drm/i915/i915_pmu.c +1 -0
@@ -11,6 +11,7 @@#include "gt/intel_engine_regs.h" #include "gt/intel_engine_user.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_rc6.h" #include "gt/intel_rps.h"
drivers/gpu/drm/i915/i915_reg.h +0 -1544
1,167 lines not on this page · raw message
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +1 -0
Lines of this file are not shown. View the raw message.
The rest of this diff is not shown. View the raw message.
Signature · 1 line
2.34.1
Part of the diff is not shown here. View the raw message.
Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Move GT registers to their own header file
drivers/gpu/drm/i915/gt/intel_gt_regs.h line 595
Quoted 11 lines · Matt Roper
drivers/gpu/drm/i915/gt/intel_gt_regs.h new file +11
-0+#define MEMSWCTL _MMIO(0x11170)/* Ironlake only */ +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1 << 12)/* write 1 triggers command, clears +when command complete */
formatting issue here
drivers/gpu/drm/i915/gt/intel_gt_regs.h line 1376
Quoted 3 lines
drivers/gpu/drm/i915/gt/intel_gt_regs.h new file +3
-0+#define GEN9_SLICE_PGCTL_ACK (slice) _MMIO(0x804c + (slice) * 0x4) +#define GEN10_SLICE_PGCTL_ACK (slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ +((slice) % 3) * 0x4)
and here
drivers/gpu/drm/i915/gt/intel_gt_regs.h line 1383
Quoted 7 lines
drivers/gpu/drm/i915/gt/intel_gt_regs.h new file +7
-0+#define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS_ACK (subslice) (1 << (2 + (subslice) * 2)) +#define GEN10_PGCTL_VALID_SS_MASK (slice) ((slice) == 0 ? 0x7F : 0x1F) + +#define GEN9_SS01_EU_PGCTL_ACK (slice) _MMIO(0x805c + (slice) * 0x8) +#define GEN10_SS01_EU_PGCTL_ACK (slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8)
and here
drivers/gpu/drm/i915/gt/intel_gt_regs.h line 1386
Quoted 3 lines
drivers/gpu/drm/i915/gt/intel_gt_regs.h new file +3
-0+#define GEN9_SS23_EU_PGCTL_ACK (slice) _MMIO(0x8060 + (slice) * 0x8) +#define GEN10_SS23_EU_PGCTL_ACK (slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8)
and here.
Rest looks sane. There's already a conflict in this patch, although following "this should be just code move", it's easy to solve.
I wonder what is the strategy going to be for merging this because it will conflict badly between drm-intel-next and drm-intel-gt-next.
Lucas De Marchi
PATCH v2 6/6 drm/i915: Only include i915_reg.h from .c files
In reply to Matt RoperSeveral of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and include an explicit include from the .c files that truly need the register definitions; those that need a definition of i915_reg_t for a function definition can get it from i915_reg_defs.h instead.
We also remove two non-register #define's (VLV_DISPLAY_BASE and GEN12_SFC_DONE_MAX) into i915_reg_defs.h to allow us to drop the i915_reg.h include from a couple of headers.
There's probably a lot more header dependency optimization possible, but the changes here roughly cut the number of files compiled after 'touch i915_reg.h' in half --- a good first step.
--- drivers/gpu/drm/i915/display/g4x_hdmi.h | 2 +- drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_bios.c | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 1 + drivers/gpu/drm/i915/display/intel_crt.h | 2 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 +- drivers/gpu/drm/i915/display/intel_de.h | 1 - drivers/gpu/drm/i915/display/intel_display_power.h | 1 - drivers/gpu/drm/i915/display/intel_dmc.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 2 -- drivers/gpu/drm/i915/display/intel_dsb.h | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 2 -- drivers/gpu/drm/i915/display/intel_lvds.h | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +- drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 + drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 - drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_llc.c | 1 + drivers/gpu/drm/i915/gt/intel_rc6.c | 1 + drivers/gpu/drm/i915/gt/intel_rc6.h | 2 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds_types.h | 2 +- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 1 + drivers/gpu/drm/i915/gvt/edid.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.h | 2 +- drivers/gpu/drm/i915/gvt/mmio.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.h | 1 - drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf_types.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 3 --- drivers/gpu/drm/i915/i915_reg_defs.h | 4 ++++ drivers/gpu/drm/i915/intel_dram.c | 1 + drivers/gpu/drm/i915/intel_pcode.c | 1 + drivers/gpu/drm/i915/intel_pm.h | 1 - drivers/gpu/drm/i915/intel_sbi.c | 1 + drivers/gpu/drm/i915/intel_uncore.h | 2 +- drivers/gpu/drm/i915/vlv_sideband.c | 1 + 56 files changed, 49 insertions(+), 29 deletions(-)
drivers/gpu/drm/i915/display/g4x_hdmi.h +1 -1
@@ -8,7 +8,7 @@#include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" enum port ;struct drm_i915_private ;
drivers/gpu/drm/i915/display/intel_atomic.c +1 -0
@@ -35,6 +35,7 @@#include <drm/drm_plane_helper.h> #include "i915_drv.h" +#include "i915_reg.h" #include "intel_atomic.h" #include "intel_cdclk.h" #include "intel_display_types.h"
drivers/gpu/drm/i915/display/intel_bios.c +1 -0
@@ -32,6 +32,7 @@#include "display/intel_gmbus.h" #include "i915_drv.h" +#include "i915_reg.h" #define _INTEL_BIOS_PRIVATE#include "intel_vbt_defs.h"
drivers/gpu/drm/i915/display/intel_bw.c +1 -0
@@ -5,6 +5,7 @@#include <drm/drm_atomic_state_helper.h> +#include "i915_reg.h" #include "intel_atomic.h" #include "intel_bw.h" #include "intel_cdclk.h"
drivers/gpu/drm/i915/display/intel_crt.h +1 -1
@@ -6,7 +6,7 @@#ifndef __INTEL_CRT_H__#define __INTEL_CRT_H__ -#include "i915_reg.h" +#include "i915_reg_defs.h" enum pipe ;struct drm_encoder ;
drivers/gpu/drm/i915/display/intel_ddi.h +1 -1
@@ -6,7 +6,7 @@#ifndef __INTEL_DDI_H__#define __INTEL_DDI_H__ -#include "i915_reg.h" +#include "i915_reg_defs.h" struct drm_connector_state ;struct drm_i915_private ;
drivers/gpu/drm/i915/display/intel_de.h +0 -1
@@ -7,7 +7,6 @@#define __INTEL_DE_H__#include "i915_drv.h" -#include "i915_reg.h" #include "i915_trace.h" #include "intel_uncore.h"
drivers/gpu/drm/i915/display/intel_display_power.h +0 -1
@@ -7,7 +7,6 @@#define __INTEL_DISPLAY_POWER_H__#include "intel_runtime_pm.h" -#include "i915_reg.h" enum dpio_channel ;enum dpio_phy ;
drivers/gpu/drm/i915/display/intel_dmc.h +1 -1
@@ -6,7 +6,7 @@#ifndef __INTEL_DMC_H__#define __INTEL_DMC_H__ -#include "i915_reg.h" +#include "i915_reg_defs.h" #include "intel_wakeref.h" #include <linux/workqueue.h>
drivers/gpu/drm/i915/display/intel_dp.h +0 -2
@@ -8,8 +8,6 @@#include <linux/types.h> -#include "i915_reg.h" -enum intel_output_format ;enum pipe ;enum port ;
drivers/gpu/drm/i915/display/intel_dsb.h +1 -1
@@ -8,7 +8,7 @@#include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" struct intel_crtc_state ;struct i915_vma ;
drivers/gpu/drm/i915/display/intel_dsi_vbt.c +1 -0
@@ -39,6 +39,7 @@#include <video/mipi_display.h> #include "i915_drv.h" +#include "i915_reg.h" #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h"
drivers/gpu/drm/i915/display/intel_dvo_dev.h +1 -1
@@ -27,7 +27,7 @@#include <drm/drm_crtc.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" struct intel_dvo_device {const char *name;
drivers/gpu/drm/i915/display/intel_hdmi.h +0 -2
@@ -9,8 +9,6 @@#include <linux/hdmi.h> #include <linux/types.h> -#include "i915_reg.h" -struct drm_connector ;struct drm_encoder ;struct drm_i915_private ;
drivers/gpu/drm/i915/display/intel_lvds.h +1 -1
@@ -8,7 +8,7 @@#include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" enum pipe ;struct drm_i915_private ;
drivers/gpu/drm/i915/display/intel_sdvo.h +1 -1
@@ -8,7 +8,7 @@#include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" struct drm_i915_private ;enum pipe ;
drivers/gpu/drm/i915/display/intel_tc.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_display.h" #include "intel_display_types.h" #include "intel_dp_mst.h"
drivers/gpu/drm/i915/gem/i915_gem_stolen.c +1 -0
@@ -14,6 +14,7 @@#include "gem/i915_gem_region.h" #include "i915_drv.h" #include "i915_gem_stolen.h" +#include "i915_reg.h" #include "i915_vgpu.h" /*
drivers/gpu/drm/i915/gem/i915_gem_tiling.c +1 -0
@@ -13,6 +13,7 @@#include "i915_gem_mman.h" #include "i915_gem_object.h" #include "i915_gem_tiling.h" +#include "i915_reg.h" /** * DOC: buffer object tiling
drivers/gpu/drm/i915/gt/gen2_engine_cs.c +1 -0
@@ -5,6 +5,7 @@#include "gen2_engine_cs.h" #include "i915_drv.h" +#include "i915_reg.h" #include "intel_engine.h" #include "intel_engine_regs.h" #include "intel_gpu_commands.h"
drivers/gpu/drm/i915/gt/intel_engine.h +0 -1
@@ -11,7 +11,6 @@#include <linux/seqlock.h> #include "i915_pmu.h" -#include "i915_reg.h" #include "i915_request.h" #include "i915_selftest.h" #include "intel_engine_types.h"
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "i915_scatterlist.h" #include "i915_pvinfo.h" #include "i915_vgpu.h"
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_gt.h" #include "intel_gt_clock_utils.h" #include "intel_gt_regs.h"
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +1 -0
@@ -7,6 +7,7 @@#include <linux/seq_file.h> #include "i915_drv.h" +#include "i915_reg.h" #include "intel_gt.h" #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h"
drivers/gpu/drm/i915/gt/intel_llc.c +1 -0
@@ -7,6 +7,7 @@#include <linux/cpufreq.h> #include "i915_drv.h" +#include "i915_reg.h" #include "intel_gt.h" #include "intel_llc.h" #include "intel_pcode.h"
drivers/gpu/drm/i915/gt/intel_rc6.c +1 -0
@@ -6,6 +6,7 @@#include <linux/pm_runtime.h> #include "i915_drv.h" +#include "i915_reg.h" #include "i915_vgpu.h" #include "intel_engine_regs.h" #include "intel_gt.h"
drivers/gpu/drm/i915/gt/intel_rc6.h +1 -1
@@ -6,7 +6,7 @@#ifndef INTEL_RC6_H #define INTEL_RC6_H -#include "i915_reg.h" +#include "i915_reg_defs.h" struct intel_engine_cs ;struct intel_rc6 ;
drivers/gpu/drm/i915/gt/intel_region_lmem.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_memory_region.h" #include "intel_region_lmem.h" #include "intel_region_ttm.h"
drivers/gpu/drm/i915/gt/intel_workarounds_types.h +1 -1
@@ -8,7 +8,7 @@#include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" struct i915_wa {i915_reg_t reg;
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h +0 -1
@@ -7,7 +7,6 @@#define _GUC_ACTIONS_SLPC_ABI_H_#include <linux/types.h> -#include "i915_reg.h" /** * DOC: SLPC SHARED DATA STRUCTURE
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +1 -1
@@ -9,7 +9,7 @@#include <linux/compiler.h> #include <linux/types.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" /* Definitions of GuC H/W registers, bits, etc */
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_guc_slpc.h" #include "gt/intel_gt.h" #include "gt/intel_gt_regs.h"
drivers/gpu/drm/i915/gt/uc/intel_huc.h +1 -1
@@ -6,7 +6,7 @@#ifndef _INTEL_HUC_H_#define _INTEL_HUC_H_ -#include "i915_reg.h" +#include "i915_reg_defs.h" #include "intel_uc_fw.h" #include "intel_huc_fw.h"
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +1 -0
@@ -11,6 +11,7 @@#include "intel_uc_fw.h" #include "intel_uc_fw_abi.h" #include "i915_drv.h" +#include "i915_reg.h" static inline struct intel_gt *____uc_fw_to_gt (struct intel_uc_fw *uc_fw,enum intel_uc_fw_type type)
drivers/gpu/drm/i915/gvt/aperture_gm.c +1 -0
@@ -35,6 +35,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gt/intel_ggtt_fencing.h" #include "gvt.h"
drivers/gpu/drm/i915/gvt/display.c +1 -0
@@ -33,6 +33,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" static int get_edp_pipe (struct intel_vgpu *vgpu)
drivers/gpu/drm/i915/gvt/dmabuf.c +1 -0
@@ -32,6 +32,7 @@#include <linux/vfio.h> #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" #define GEN8_DECODE_PTE (pte) (pte & GENMASK_ULL(63, 12))
drivers/gpu/drm/i915/gvt/edid.c +1 -0
@@ -33,6 +33,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" #define GMBUS1_TOTAL_BYTES_SHIFT 16
drivers/gpu/drm/i915/gvt/fb_decoder.c +1 -0
@@ -37,6 +37,7 @@#include "i915_drv.h" #include "gvt.h" #include "i915_pvinfo.h" +#include "i915_reg.h" #define PRIMARY_FORMAT_NUM 16struct pixel_format {
drivers/gpu/drm/i915/gvt/handlers.c +1 -0
@@ -37,6 +37,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" #include "i915_pvinfo.h" #include "display/intel_display_types.h"
drivers/gpu/drm/i915/gvt/interrupt.c +1 -0
@@ -30,6 +30,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" #include "trace.h"
drivers/gpu/drm/i915/gvt/interrupt.h +1 -1
@@ -35,7 +35,7 @@#include <linux/hrtimer.h> #include <linux/kernel.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" enum intel_gvt_event_type {RCS_MI_USER_INTERRUPT =0 ,
drivers/gpu/drm/i915/gvt/mmio.c +1 -0
@@ -34,6 +34,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "gvt.h" #include "gt/intel_gt_regs.h"
drivers/gpu/drm/i915/gvt/mmio_context.h +0 -1
@@ -41,7 +41,6 @@#include "gt/intel_engine_regs.h" #include "gt/intel_engine_types.h" #include "gt/intel_lrc_reg.h" -#include "i915_reg.h" struct i915_request ;struct intel_context ;
drivers/gpu/drm/i915/i915_cmd_parser.c +1 -0
@@ -33,6 +33,7 @@#include "i915_cmd_parser.h" #include "i915_drv.h" #include "i915_memcpy.h" +#include "i915_reg.h" /** * DOC: batch buffer command parser
drivers/gpu/drm/i915/i915_drv.h +0 -1
@@ -61,7 +61,6 @@#include <drm/ttm/ttm_device.h> #include "i915_params.h" -#include "i915_reg.h" #include "i915_utils.h" #include "display/intel_bios.h"
drivers/gpu/drm/i915/i915_pci.c +1 -0
@@ -28,6 +28,7 @@#include "i915_driver.h" #include "i915_drv.h" #include "i915_pci.h" +#include "i915_reg.h" #define PLATFORM (x) .platform = (x)#define GEN (x) \
drivers/gpu/drm/i915/i915_perf_types.h +1 -1
@@ -18,7 +18,7 @@#include <uapi/drm/i915_drm.h> #include "gt/intel_sseu.h" -#include "i915_reg.h" +#include "i915_reg_defs.h" #include "intel_wakeref.h" struct drm_i915_private ;
drivers/gpu/drm/i915/i915_reg.h +0 -3
@@ -115,7 +115,6 @@* #define GEN8_BAR _MMIO(0xb888) */ -#define VLV_DISPLAY_BASE 0x180000#define VLV_MIPI_BASE VLV_DISPLAY_BASE#define BXT_MIPI_BASE 0x60000
@@ -189,8 +188,6 @@#define _MASKED_BIT_ENABLE (a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })#define _MASKED_BIT_DISABLE (a) (_MASKED_FIELD((a), 0)) -#define GEN12_SFC_DONE_MAX 4 -#define GU_CNTL _MMIO(0x101010)#define LMEM_INIT REG_BIT(7)
drivers/gpu/drm/i915/i915_reg_defs.h +4 -0
@@ -94,4 +94,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); } +#define VLV_DISPLAY_BASE 0x180000 + +#define GEN12_SFC_DONE_MAX 4 +#endif /* __I915_REG_DEFS__ */
drivers/gpu/drm/i915/intel_dram.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_dram.h" #include "intel_pcode.h"
drivers/gpu/drm/i915/intel_pcode.c +1 -0
@@ -4,6 +4,7 @@*/ #include "i915_drv.h" +#include "i915_reg.h" #include "intel_pcode.h" static int gen6_check_mailbox_status (u32 mbox)
drivers/gpu/drm/i915/intel_pm.h +0 -1
@@ -12,7 +12,6 @@#include "display/intel_global_state.h" #include "i915_drv.h" -#include "i915_reg.h" struct drm_device ;struct drm_i915_private ;
drivers/gpu/drm/i915/intel_sbi.c +1 -0
@@ -7,6 +7,7 @@#include "i915_drv.h" #include "intel_sbi.h" +#include "i915_reg.h" /* SBI access */ static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
drivers/gpu/drm/i915/intel_uncore.h +1 -1
@@ -30,7 +30,7 @@#include <linux/hrtimer.h> #include <linux/io-64-nonatomic-lo-hi.h> -#include "i915_reg.h" +#include "i915_reg_defs.h" struct drm_i915_private ;struct intel_runtime_pm ;
drivers/gpu/drm/i915/vlv_sideband.c +1 -0
@@ -5,6 +5,7 @@#include "i915_drv.h" #include "i915_iosf_mbi.h" +#include "i915_reg.h" #include "vlv_sideband.h" /*
Signature · 1 line
2.34.1
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Only include i915_reg.h from .c files
Quoted 5 lines · Matt Roper
Several of our i915 header files, have been including
i915_reg.h. This means that any change toi915_reg.hwill trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete thei915_reg.hinclude from all headers and include an explicit include from the .c files that truly
if you're going to respin this or while applying, it may be good to reword this sentence as we have too many "include".
Lucas De Marchi
Patchwork
CI[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Second round of i915_reg.h splitting (rev2)
In reply to Matt Roper== Series Details ==
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip 48db4167e8d0 drm/i915/perf: Move OA regs to their own header -:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 1023 lines checked0a70f3e5b4bc drm/i915/perf: Express OA register ranges with i915_range -:32: ERROR:OPEN_BRACE: open brace '{' following function definitions go on the next line #32: FILE: drivers/gpu/drm/i915/i915_perf.c:3867:
+static bool reg_in_range_table(u32 addr, const struct i915_range *table) {
-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line #89: FILE: drivers/gpu/drm/i915/i915_perf.c:3914:
+ { .start = 0x182300, .end = 0x1823a4 },$
-:90: WARNING:LEADING_SPACE: please, no spaces at the start of a line #90: FILE: drivers/gpu/drm/i915/i915_perf.c:3915:
+ {}$
total: 1 errors, 2 warnings, 0 checks, 524 lines checked35f45d644995 drm/i915: Parameterize R_PWR_CLK_STATE register definition 75196de08f35 drm/i915: Parameterize MI_PREDICATE registerse304eedf6882 drm/i915: Move GT registers to their own header file
-:181: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #181:
new file mode 100644
-:294: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #294: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:109:
+#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
-:296: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #296: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:111:
+#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
-:411: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #411: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:226:
+#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-:415: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #415: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:230:
+#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
-:421: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #421: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:236:
+#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
-:741: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns #741: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:556:
+#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
-:780: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines #780: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:595:
+#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
+when command complete */
-:780: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #780: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:595:
+when command complete */
-:893: WARNING:LONG_LINE_COMMENT: line length of 134 exceeds 100 columns #893: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:708:
+#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
-:980: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'cxt_reg' - possible side-effects? #980: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:795:
+#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
+ GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
+ GEN6_CXT_PIPELINE_SIZE(cxt_reg))
-:990: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ctx_reg' - possible side-effects? #990: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:805:
+#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
+ GEN7_CXT_VFSTATE_SIZE(ctx_reg))
-:1560: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #1560: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1375:
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+((slice) % 3) * 0x4)
-:1567: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #1567: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1382:
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
+((slice) % 3) * 0x8)
-:1570: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #1570: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1385:
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
+((slice) % 3) * 0x8)
total: 0 errors, 10 warnings, 5 checks, 3535 lines checked 033e2e31ec1c drm/i915: Only include i915_reg.h from .c files
Patchwork
CI[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Second round of i915_reg.h splitting (rev2)
In reply to Matt Roper== Series Details ==
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Patchwork
CI[Intel-gfx] ✓ Fi.CI.BAT: success for Second round of i915_reg.h splitting (rev2)
In reply to Matt Roper== Series Details ==
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11129 -> Patchwork_22094
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/index.html
Participating hosts (51 -> 45)
------------------------------
Additional (1): fi-pnv-d510
Missing (7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22094 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@[email protected]
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][2] ([i915#4547])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@[email protected]
* igt@i915_selftest@live@requests:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][3] ([i915#2927] / [i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@i915_selftest@[email protected]
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#2403] / [i915#4312])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-pnv-d510/igt@[email protected]
- fi-skl-6600u: NOTRUN -> [FAIL][5] ([i915#1436] / [i915#4312])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-skl-6600u/igt@[email protected]
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
- fi-bsw-kefka: [DMESG-FAIL][8] ([i915#541]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][10] ([i915#4494]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-5/igt@i915_selftest@[email protected]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-5/igt@i915_selftest@[email protected]
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][12] ([i915#4269]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-cml-u2/igt@[email protected]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-cml-u2/igt@[email protected]
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] -> [DMESG-FAIL][15] ([i915#4494])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/bat-dg1-6/igt@i915_selftest@[email protected]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/bat-dg1-6/igt@i915_selftest@[email protected]
- fi-hsw-4770: [INCOMPLETE][16] ([i915#3303]) -> [INCOMPLETE][17] ([i915#4785])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/fi-hsw-4770/igt@i915_selftest@[email protected]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/fi-hsw-4770/igt@i915_selftest@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-------------
* Linux: CI_DRM_11129 -> Patchwork_22094
CI-20190529: 20190529
CI_DRM_11129: 0b83d3cf9f9eab03ec804d56ac2686320a64f3ee @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6330: f73008bac9a8db0779264b170f630483e9165764 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22094: 033e2e31ec1c90c3956530673656fa81b4e478b1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
033e2e31ec1c drm/i915: Only include i915_reg.h from .c files e304eedf6882 drm/i915: Move GT registers to their own header file 75196de08f35 drm/i915: Parameterize MI_PREDICATE registers 35f45d644995 drm/i915: Parameterize R_PWR_CLK_STATE register definition 0a70f3e5b4bc drm/i915/perf: Express OA register ranges with i915_range 48db4167e8d0 drm/i915/perf: Move OA regs to their own header
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/index.html
Patchwork
CI[Intel-gfx] ✗ Fi.CI.IGT: failure for Second round of i915_reg.h splitting (rev2)
In reply to Matt Roper== Series Details ==
== Series Details ==
Series: Second round of i915_reg.h splitting (rev2)
URL : https://patchwork.freedesktop.org/series/99079/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11129_full -> Patchwork_22094_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22094_full absolutely need to be verified manually.
If you think the reported changes have nothing to do with the changes introduced in Patchwork_22094_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22094_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl6/igt@[email protected]
- shard-apl: NOTRUN -> [DMESG-WARN][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl8/igt@[email protected]
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@[email protected]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][4] -> [INCOMPLETE][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl6/igt@[email protected]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl2/igt@[email protected]
Known issues
------------
Here are the changes found in Patchwork_22094_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@[email protected]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl7/igt@[email protected]
- shard-iclb: [PASS][8] -> [TIMEOUT][9] ([i915#3070])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb8/igt@[email protected]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb6/igt@[email protected]
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#4525]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb4/igt@[email protected]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb7/igt@[email protected]
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#4547])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl7/igt@gem_exec_capture@[email protected]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl10/igt@gem_exec_capture@[email protected]
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][14] ([i915#2846])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@[email protected]
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2846])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk9/igt@[email protected]
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +95 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@[email protected]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl4/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb2/igt@gem_exec_fair@[email protected]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb2/igt@gem_exec_fair@[email protected]
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@[email protected]
* igt@gem_lmem_swapping@smem-oom:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#4613])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@gem_pread@exhaustion:
- shard-kbl: NOTRUN -> [WARN][25] ([i915#2658])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-skl: NOTRUN -> [WARN][26] ([i915#2658])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#4270])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3323])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3323])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@[email protected]
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3297])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#3297])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#2527] / [i915#2856])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
- shard-skl: NOTRUN -> [DMESG-WARN][33] ([i915#1436] / [i915#716])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111614]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][35] -> [DMESG-WARN][36] ([i915#118])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk5/igt@[email protected]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk2/igt@[email protected]
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][37] ([i915#3763])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3777]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111615])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +9 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3689] / [i915#3886])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3689])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271]) +93 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +8 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-audio-edid:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109284] / [fdo#111827]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +7 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl8/igt@[email protected]
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +12 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +7 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@[email protected]
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#2105])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@[email protected]
* igt@kms_cursor_crc@pipe-c-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][54] ([i915#3319]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109279] / [i915#3359])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109278] / [fdo#109279])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@kms_cursor_crc@pipe-d-cursor-128x128-random:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271]) +135 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@[email protected]
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-skl: [PASS][60] -> [DMESG-WARN][61] ([i915#1982])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl9/igt@[email protected]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl7/igt@[email protected]
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglb: NOTRUN -> [SKIP][62] ([fdo#109274] / [fdo#111825]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl1/igt@[email protected]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl2/igt@[email protected]
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#109280] / [fdo#111825]) +6 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109280]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][67] -> [FAIL][68] ([i915#1188])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl6/igt@[email protected]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl2/igt@[email protected]
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#1187])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#1187])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][72] -> [DMESG-WARN][73] ([i915#180]) +5 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@[email protected]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl6/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-skl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][76] ([i915#265]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@[email protected]
- shard-kbl: NOTRUN -> [FAIL][77] ([i915#265]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][78] -> [FAIL][79] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl10/igt@[email protected]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl4/igt@[email protected]
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#3536])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#2920])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@[email protected]
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl9/igt@[email protected]
* igt@kms_setmode@basic:
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#31])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk4/igt@[email protected]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk1/igt@[email protected]
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2437])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][89] ([i915#2437])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@[email protected]
* igt@perf@polling-parameterized:
- shard-glk: [PASS][91] -> [FAIL][92] ([i915#1542])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk3/igt@[email protected]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk3/igt@[email protected]
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#109291])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@sysfs_clients@sema-10:
- shard-tglb: NOTRUN -> [SKIP][94] ([i915#2994])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb6/igt@[email protected]
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl8/igt@[email protected]
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@[email protected]
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [PASS][97] -> [FAIL][98] ([i915#1731])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl1/igt@sysfs_heartbeat_interval@[email protected]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl10/igt@sysfs_heartbeat_interval@[email protected]
#### Possible fixes ####
* igt@gem_eio@in-flight-1us:
- shard-tglb: [TIMEOUT][99] ([i915#3063]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb1/igt@[email protected]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb1/igt@[email protected]
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][101] ([i915#4525]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb3/igt@[email protected]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb2/igt@[email protected]
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][103] ([i915#2842]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb6/igt@gem_exec_fair@[email protected]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb5/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [FAIL][105] ([i915#2842]) -> [PASS][106] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl3/igt@gem_exec_fair@[email protected]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl4/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk2/igt@gem_exec_fair@[email protected]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk7/igt@gem_exec_fair@[email protected]
* igt@gem_exec_suspend@basic-s3@smem:
- shard-skl: [INCOMPLETE][109] ([i915#4547]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl10/igt@gem_exec_suspend@[email protected]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl8/igt@gem_exec_suspend@[email protected]
* igt@gem_softpin@allocator-evict-all-engines:
- shard-glk: [FAIL][111] ([i915#4171]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk6/igt@[email protected]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk4/igt@[email protected]
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114] +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl3/igt@[email protected]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl2/igt@[email protected]
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][115] ([i915#118]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk2/igt@[email protected]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk3/igt@[email protected]
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][117] ([i915#2346]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb7/igt@[email protected]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][119] ([i915#180]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-apl2/igt@[email protected]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-apl7/igt@[email protected]
- shard-kbl: [INCOMPLETE][121] ([i915#180] / [i915#636]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl4/igt@[email protected]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl7/igt@[email protected]
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][123] ([i915#79]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk9/igt@kms_flip@[email protected]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk6/igt@kms_flip@[email protected]
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][125] ([i915#79]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl9/igt@kms_flip@[email protected]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl1/igt@kms_flip@[email protected]
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128] +6 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-kbl4/igt@kms_flip@[email protected]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-kbl1/igt@kms_flip@[email protected]
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][129] ([i915#4911]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][131] ([fdo#108145] / [i915#265]) -> [PASS][132] +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-skl8/igt@[email protected]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-skl4/igt@[email protected]
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][133] ([fdo#109441]) -> [PASS][134] +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][135] ([i915#3063] / [i915#3648]) -> [FAIL][136] ([i915#232])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-tglb7/igt@[email protected]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-tglb3/igt@[email protected]
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][137] ([i915#4525]) -> [FAIL][138] ([i915#4916])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb5/igt@[email protected]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-iclb4/igt@[email protected]
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][139] ([i915#2684]) -> [WARN][140] ([i915#1804] / [i915#2684])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11129/shard-iclb2/igt@[email protected]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/shard-
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22094/index.html