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Quartz64-A fixes and enablement from 5.17-rc1

PATCH Applied Peter Geis 2 participants 6 messages Jan 28, 2022 – Jan 29, 2022

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Peter Geis

author
#0 lore raw

v2 cover Quartz64-A fixes and enablement from 5.17-rc1

Good Evening,

This is the first of several patch series for further expanding Quartz64-A support.

This series has the following patches:
Fix the ddr regulator voltage.
Add pmu_io_domains to permit sdio and high speed emmc support. Add sdmmc1 node for wifi support.
Annotate con40 functions and enable i2c3.

Please review and apply.

Very Respectfully,
Peter Geis

Changelog:
v2:
- drop status = "okay" from sdio_pwrseq
- drop disable-wp from sdmmc1
- move reset-gpios to be alphabetical in sdio_pwrseq
- add con40 annotation patch

Peter Geis (4):
arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
arm64: dts: rockchip: add Quartz64-A pmu_io_domains
arm64: dts: rockchip: add Quartz64-A sdmmc1 node
arm64: dts: rockchip: add Quartz64-A con40 hardware

 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 81 ++++++++++++++++++-
 1 file changed, 79 insertions(+), 2 deletions(-)
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH v2 1/4 arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage

The Quartz64 Model A uses a voltage divider to ensure ddr voltage is within specification from the default regulator configuration. Adjusting this voltage is detrimental, and currently causes the ddr voltage to be about 0.8v.

Remove the min and max voltage setpoints for the ddr regulator.

Fixes b33a22a1e7c4 ("arm64: dts: rockchip: add basic dts for Pine64

Quartz64-A")

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 --
 1 file changed, 2 deletions(-)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +0 -2
index 166399b7f13f..d9eb92d59099 100644
@@ -285,8 +285,6 @@ regulator-state-mem {
 			vcc_ddr: DCDC_REG3 {
 				regulator-always-on;
 				regulator-boot-on;
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
 				regulator-initial-mode = <0x2>;
 				regulator-name = "vcc_ddr";
 				regulator-state-mem {
Signature · 1 line
2.25.1
author
#2 lore raw

PATCH v2 2/4 arm64: dts: rockchip: add Quartz64-A pmu_io_domains

In reply to Peter Geis

Several io power domains on the Quartz64-A operate at 1.8v. Add the pmu_io_domains definition to enable support for this. This permits the enablement of the following features:
sdio - wifi support
sdhci - mmc-hs200-1_8v

Signed-off-by Peter Geis <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +13 -0
index d9eb92d59099..33c2c18caaa9 100644
@@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h {
 	};
 };
 
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc1v8_dvp>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
 &sdhci {
 	bus-width = <8>;
 	mmc-hs200-1_8v;
Signature · 1 line
2.25.1
author
#3 lore raw

PATCH v2 3/4 arm64: dts: rockchip: add Quartz64-A sdmmc1 node

In reply to Peter Geis

The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64.
Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A.

Signed-off-by Peter Geis <[email protected]>

---

Changelog:
v2:
- drop status = "okay" from sdio_pwrseq
- drop disable-wp from sdmmc1
- move reset-gpios to be alphabetical in sdio_pwrseq

---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +43 -0
index 33c2c18caaa9..c5a79046a9d0 100644
@@ -91,6 +91,17 @@ simple-audio-card,codec {
 		};
 	};
 
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk817 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <5000000>;
+		reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	};
+
 	vcc12v_dcin: vcc12v_dcin {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";

@@ -147,6 +158,17 @@ vcc_sys: vcc_sys {
 		regulator-max-microvolt = <4400000>;
 		vin-supply = <&vbus>;
 	};
+
+	/* sourced from vcc_sys, sdio module operates internally at 3.3v */
+	vcc_wl: vcc_wl {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_wl";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
 };
 
 &cpu0 {

@@ -475,6 +497,12 @@ pmic_int_l: pmic-int-l {
 		};
 	};
 
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	vcc_sd {
 		vcc_sd_h: vcc-sd-h {
 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;

@@ -516,6 +544,21 @@ &sdmmc0 {
 	status = "okay";
 };
 
+&sdmmc1 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_wl>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
 &spdif {
 	status = "okay";
 };
Signature · 1 line
2.25.1
author
#4 lore raw

PATCH v2 4/4 arm64: dts: rockchip: add Quartz64-A con40 hardware

In reply to Peter Geis

The Quartz64-A has a 40 pin connector that exposes various functions. Annotate the functions exposed in the device tree.
Enable i2c3, which is pulled up to vcc_3v3 on board.

The following functions are currently exposed:
i2c3
spi1
uart2
uart0
spdif

Signed-off-by Peter Geis <[email protected]>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +23 -0
index c5a79046a9d0..d3dc60ff60dd 100644
@@ -449,6 +449,14 @@ regulator-state-mem {
 	};
 };
 
+/* i2c3 is exposed on con40
+ * pin 3 - i2c3_sda_m0, pullup to vcc_3v3
+ * pin 5 - i2c3_scl_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+	status = "okay";
+};
+
 &i2s1_8ch {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2s1m0_sclktx

@@ -559,10 +567,17 @@ &sdmmc1 {
 	status = "okay";
 };
 
+/* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";
 };
 
+/* spi1 is exposed on con40
+ * pin 11 - spi1_mosi_m1
+ * pin 13 - spi1_miso_m1
+ * pin 15 - spi1_clk_m1
+ * pin 17 - spi1_cs0_m1
+ */
 &spi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;

@@ -576,6 +591,10 @@ &tsadc {
 	status = "okay";
 };
 
+/* uart0 is exposed on con40
+ * pin 12 - uart0_tx
+ * pin 14 - uart0_rx
+ */
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_xfer>;

@@ -602,6 +621,10 @@ bluetooth {
 	};
 };
 
+/* uart2 is exposed on con40
+ * pin 8 - uart2_tx_m0_debug
+ * pin 10 - uart2_rx_m0_debug
+ */
 &uart2 {
 	status = "okay";
 };
Signature · 1 line
2.25.1
maintainer Applied
#5 lore raw
In reply to Peter Geis
Quoted 5 lines · Peter Geis

Good Evening,

This is the first of several patch series for further expanding Quartz64-A support.

Quoted 7 lines

This series has the following patches:
Fix the ddr regulator voltage.
Add pmu_io_domains to permit sdio and high speed emmc support. Add sdmmc1 node for wifi support.
Annotate con40 functions and enable i2c3.

[...]

Applied, thanks!

[1/4] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage

      commit: 8c318aaa20000bcfb9dc115c2a8e08c2e77ad439
[2/4] arm64: dts: rockchip: add Quartz64-A pmu_io_domains
      commit: 827dfba89ae150cd0fd88bc13117540cb4882943
[3/4] arm64: dts: rockchip: add Quartz64-A sdmmc1 node
      commit: 2ed1e35457a1917a9c567c186a5adc7ce6341b6e

With a minimal reordering (sdio-* comes before spdif alphabetically)

[4/4] arm64: dts: rockchip: add Quartz64-A con40 hardware

      commit: 2943660fe301aa650cdf60226a2a350d09145823

Best regards,

Signature · 1 line
Heiko Stuebner <[email protected]>