drm/i915: M/N cleanup
v2 cover drm/i915: M/N cleanup
From: Ville Syrjälä <[email protected]>
Rehashed version of the M/N cleanup after Jani (rightly) complained about the legibility of some of the patches in the v1 series. These are chunked to a finer pulp, some got revised a bit, and I left out a few of the FDI related things for now. I'll revisit the PCH port/FDI topic later, for now I just slapped in an extra patch to make sure we don't try to use DRRS on PCH ports.
Ville Syrjälä (17):
drm/i915: Nuke intel_dp_set_m_n()
drm/i915: Nuke intel_dp_get_m_n()
drm/i915: Nuke ilk_get_fdi_m_n_config()
drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2
variants
drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2
variants
drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() drm/i915: Move PCH transcoder M/N setup into the PCH code drm/i915: Move M/N setup to a more logical place on ddi platforms drm/i915: Extract {i9xx,ilk}_configure_cpu_transcoder() drm/i915: Disable DRRS on IVB/HSW port != A
drm/i915: Extract can_enable_drrs()
drm/i915: Fix intel_cpu_transcoder_has_m2_n2()
drm/i915: Clear DP M2/N2 when not doing DRRS
drm/i915: Program pch transcoder m2/n2
drm/i915: Dump dp_m2_n2 always
drm/i915: Always check dp_m2_n2 on pre-bdw
drm/i915: Document BDW+ DRRS M/N programming requirements
drivers/gpu/drm/i915/display/g4x_dp.c | 18 +- drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_display.c | 266 ++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 32 ++- .../drm/i915/display/intel_display_types.h | 19 -- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 - drivers/gpu/drm/i915/display/intel_drrs.c | 50 +++- .../gpu/drm/i915/display/intel_pch_display.c | 54 +++- .../gpu/drm/i915/display/intel_pch_display.h | 6 + 9 files changed, 259 insertions(+), 202 deletions(-)
Signature · 1 line
2.34.1
PATCH v2 1/17 drm/i915: Nuke intel_dp_set_m_n()
From: Ville Syrjälä <[email protected]>
I want to make a clean split betwen the CPU vs. PCH transcoder programming. To that end eliminate intel_dp_set_m_n() and just call the individual CPU/PCH transcoder functions directly.
--- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 56 +++++++------------ drivers/gpu/drm/i915/display/intel_display.h | 6 +- .../drm/i915/display/intel_display_types.h | 19 ------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/display/intel_drrs.c | 5 +- 6 files changed, 32 insertions(+), 62 deletions(-)
drivers/gpu/drm/i915/display/intel_ddi.c +3 -1
@@ -2510,7 +2510,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST )) {intel_ddi_set_dp_msa (crtc_state, conn_state); -intel_dp_set_m_n (crtc_state,M1_N1 ); +intel_cpu_transcoder_set_m_n (crtc_state, + &crtc_state->dp_m_n, + &crtc_state->dp_m2_n2); } }
drivers/gpu/drm/i915/display/intel_display.c +20 -36
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drivers/gpu/drm/i915/display/intel_display.h +3 -3
@@ -27,7 +27,6 @@#include <drm/drm_util.h> -enum link_m_n_set ;enum drm_scaling_filter ;struct dpll ;struct drm_connector ;
@@ -607,8 +606,9 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv);void intel_dp_get_m_n (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config); -void intel_dp_set_m_n (const struct intel_crtc_state *crtc_state, -enum link_m_n_set m_n); +void intel_cpu_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, +const struct intel_link_m_n *m_n, +const struct intel_link_m_n *m2_n2);void ilk_get_fdi_m_n_config (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config); void i9xx_crtc_clock_get(struct intel_crtc *crtc,
drivers/gpu/drm/i915/display/intel_display_types.h +0 -19
@@ -1445,25 +1445,6 @@ struct intel_hdmi { };struct intel_dp_mst_encoder ; -/* -* enum link_m_n_set: -* When platform provides two set of M_N registers for dp, we can -* program them and switch between them incase of DRRS. -* But When only one such register is provided, we have to program the -* required divider value on that registers itself based on the DRRS state. -* -* M1_N1 : Program dp_m_n on M1_N1 registers -* dp_m2_n2 on M2_N2 registers (If supported) -* -* M2_N2 : Program dp_m2_n2 on M1_N1 registers -* M2_N2 registers are not supported -*/ - -enum link_m_n_set { -/* Sets the m1_n1 and m2_n2 */ -M1_N1 =0 , -M2_N2 -};struct intel_dp_compliance_data {unsigned long edid;
drivers/gpu/drm/i915/display/intel_dp_mst.c +3 -1
@@ -523,7 +523,9 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,intel_ddi_set_dp_msa (pipe_config, conn_state); -intel_dp_set_m_n (pipe_config,M1_N1 ); +intel_cpu_transcoder_set_m_n (pipe_config, + &pipe_config->dp_m_n, + &pipe_config->dp_m2_n2); } static void intel_mst_enable_dp(struct intel_atomic_state *state,
drivers/gpu/drm/i915/display/intel_drrs.c +3 -2
@@ -115,8 +115,9 @@ static void intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, enum drrs_refresh_rate_type refresh_type) { -intel_dp_set_m_n (crtc_state, - refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1); + intel_cpu_transcoder_set_m_n(crtc_state, refresh_type == DRRS_LOW_RR ? + &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n, + NULL); } static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
Signature · 1 line
2.34.1
PATCH v2 2/17 drm/i915: Nuke intel_dp_get_m_n()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
As with intel_dp_set_m_n() let's get rid of the wrapper and just call the relevant PCH vs. CPU transcoder functions directly.
--- drivers/gpu/drm/i915/display/g4x_dp.c | 14 +++++++++++- drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++++-- drivers/gpu/drm/i915/display/intel_display.c | 23 +++++--------------- drivers/gpu/drm/i915/display/intel_display.h | 8 +++++-- 4 files changed, 32 insertions(+), 22 deletions(-)
drivers/gpu/drm/i915/display/g4x_dp.c +13 -1
@@ -333,6 +333,18 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,return ret; } +static void g4x_dp_get_m_n (struct intel_crtc_state *crtc_state) +{ +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); + +if (crtc_state->has_pch_encoder) +intel_pch_transcoder_get_m_n (crtc, &crtc_state->dp_m_n); +else +intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, + &crtc_state->dp_m_n, + &crtc_state->dp_m2_n2); +} +static void intel_dp_get_config (struct intel_encoder *encoder,struct intel_crtc_state *pipe_config) {
@@ -384,7 +396,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, pipe_config->lane_count = ((tmp &DP_PORT_WIDTH_MASK ) >>DP_PORT_WIDTH_SHIFT ) +1 ; -intel_dp_get_m_n (crtc, pipe_config); +g4x_dp_get_m_n (pipe_config);if (port ==PORT_A ) {if ((intel_de_read (dev_priv,DP_A ) &DP_PLL_FREQ_MASK ) ==DP_PLL_FREQ_162MHZ )
drivers/gpu/drm/i915/display/intel_ddi.c +7 -2
@@ -3360,7 +3360,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |=BIT (INTEL_OUTPUT_DP ); pipe_config->lane_count = ((temp &DDI_PORT_WIDTH_MASK ) >>DDI_PORT_WIDTH_SHIFT ) +1 ; -intel_dp_get_m_n (crtc, pipe_config); + +intel_cpu_transcoder_get_m_n (crtc, cpu_transcoder, + &pipe_config->dp_m_n, + &pipe_config->dp_m2_n2);if (DISPLAY_VER (dev_priv) >=11 ) {i915_reg_t dp_tp_ctl =dp_tp_ctl_reg (encoder, pipe_config);
@@ -3397,7 +3400,9 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->mst_master_transcoder =REG_FIELD_GET (TRANS_DDI_MST_TRANSPORT_SELECT_MASK , temp); -intel_dp_get_m_n (crtc, pipe_config); +intel_cpu_transcoder_get_m_n (crtc, cpu_transcoder, + &pipe_config->dp_m_n, + &pipe_config->dp_m2_n2); pipe_config->infoframes.enable |=intel_hdmi_infoframes_enabled (encoder, pipe_config);
drivers/gpu/drm/i915/display/intel_display.c +6 -17
@@ -3856,8 +3856,8 @@ static void intel_get_m_n(struct drm_i915_private *i915, m_n->tu =REG_FIELD_GET (TU_SIZE_MASK ,intel_de_read (i915, data_m_reg)) +1 ; } -static void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, -struct intel_link_m_n *m_n) +void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, +struct intel_link_m_n *m_n) {struct drm_device *dev = crtc->base.dev;struct drm_i915_private *dev_priv =to_i915 (dev);
@@ -3868,10 +3868,10 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } -static void intel_cpu_transcoder_get_m_n (struct intel_crtc *crtc, -enum transcoder transcoder, -struct intel_link_m_n *m_n, -struct intel_link_m_n *m2_n2) +void intel_cpu_transcoder_get_m_n (struct intel_crtc *crtc, +enum transcoder transcoder, +struct intel_link_m_n *m_n, +struct intel_link_m_n *m2_n2) {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe;
@@ -3893,17 +3893,6 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, } } -void intel_dp_get_m_n (struct intel_crtc *crtc, -struct intel_crtc_state *pipe_config) -{ -if (pipe_config->has_pch_encoder) -intel_pch_transcoder_get_m_n (crtc, &pipe_config->dp_m_n); -else -intel_cpu_transcoder_get_m_n (crtc, pipe_config->cpu_transcoder, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); -} -void ilk_get_fdi_m_n_config (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config) {
drivers/gpu/drm/i915/display/intel_display.h +6 -2
@@ -604,11 +604,15 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); -void intel_dp_get_m_n (struct intel_crtc *crtc, -struct intel_crtc_state *pipe_config);void intel_cpu_transcoder_set_m_n (const struct intel_crtc_state *crtc_state,const struct intel_link_m_n *m_n,const struct intel_link_m_n *m2_n2); +void intel_cpu_transcoder_get_m_n (struct intel_crtc *crtc, +enum transcoder cpu_transcoder, +struct intel_link_m_n *m_n, +struct intel_link_m_n *m2_n2); +void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, +struct intel_link_m_n *m_n);void ilk_get_fdi_m_n_config (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config); void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Signature · 1 line
2.34.1
PATCH v2 3/17 drm/i915: Nuke ilk_get_fdi_m_n_config()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Get rid of the entirely pointless ilk_get_fdi_m_n_config() wrapper and just call the CPU transcoder function directly.
--- drivers/gpu/drm/i915/display/intel_display.c | 7 ------- drivers/gpu/drm/i915/display/intel_display.h | 2 -- drivers/gpu/drm/i915/display/intel_pch_display.c | 6 ++++-- 3 files changed, 4 insertions(+), 11 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +0 -7
@@ -3893,13 +3893,6 @@ void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, } } -void ilk_get_fdi_m_n_config (struct intel_crtc *crtc, -struct intel_crtc_state *pipe_config) -{ -intel_cpu_transcoder_get_m_n (crtc, pipe_config->cpu_transcoder, - &pipe_config->fdi_m_n,NULL ); -} -static void ilk_get_pfit_pos_size (struct intel_crtc_state *crtc_state,u32 pos,u32 size) {
drivers/gpu/drm/i915/display/intel_display.h +0 -2
@@ -613,8 +613,6 @@ void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct intel_link_m_n *m2_n2);void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc,struct intel_link_m_n *m_n); -void ilk_get_fdi_m_n_config (struct intel_crtc *crtc, -struct intel_crtc_state *pipe_config);void i9xx_crtc_clock_get (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config);int intel_dotclock_calculate (int link_freq,const struct intel_link_m_n *m_n);
drivers/gpu/drm/i915/display/intel_pch_display.c +4 -2
@@ -386,7 +386,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>FDI_DP_PORT_WIDTH_SHIFT ) +1 ; -ilk_get_fdi_m_n_config (crtc, crtc_state); +intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n,NULL );if (HAS_PCH_IBX (dev_priv)) {/*
@@ -509,7 +510,8 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>FDI_DP_PORT_WIDTH_SHIFT ) +1 ; -ilk_get_fdi_m_n_config (crtc, crtc_state); +intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n,NULL ); crtc_state->hw.adjusted_mode.crtc_clock =lpt_get_iclkip (dev_priv); }
Signature · 1 line
2.34.1
PATCH v2 4/17 drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Make things a bit more explicit by splitting intel_cpu_transcoder_set_m_n() into separate variants for M1/N1 vs. M2/N2. Makes the DRRS M/N programming at least more obvious.
Note that for the MST and DRRS cases we don't need to call the M2/N2 variant at all since the transcoders that support those do not have the M2/N2 registers.
Same could be said for i9xx_crtc_enable() but I want to do a higher level code sharing between that valleyview_crtc_enable() later in which case we do need the M2/N2 variant. This is also why I keep the transcoder_has_m2_n2() in intel_cpu_transcoder_set_m2_n2() so the caller doesn't have necessarily care what the chosen transcoder supports.
--- drivers/gpu/drm/i915/display/intel_ddi.c | 7 +- drivers/gpu/drm/i915/display/intel_display.c | 75 +++++++++++--------- drivers/gpu/drm/i915/display/intel_display.h | 7 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +- drivers/gpu/drm/i915/display/intel_drrs.c | 5 +- 5 files changed, 54 insertions(+), 45 deletions(-)
drivers/gpu/drm/i915/display/intel_ddi.c +4 -3
@@ -2510,9 +2510,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST )) {intel_ddi_set_dp_msa (crtc_state, conn_state); -intel_cpu_transcoder_set_m_n (crtc_state, - &crtc_state->dp_m_n, - &crtc_state->dp_m2_n2); +intel_cpu_transcoder_set_m1_n1 (crtc_state, + &crtc_state->dp_m_n); +intel_cpu_transcoder_set_m2_n2 (crtc_state, + &crtc_state->dp_m2_n2); } }
drivers/gpu/drm/i915/display/intel_display.c +42 -33
125 lines not on this page · raw message
drivers/gpu/drm/i915/display/intel_display.h +4 -3
@@ -604,9 +604,10 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); -void intel_cpu_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, -const struct intel_link_m_n *m_n, -const struct intel_link_m_n *m2_n2); +void intel_cpu_transcoder_set_m1_n1 (const struct intel_crtc_state *crtc_state, +const struct intel_link_m_n *m_n); +void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state, +const struct intel_link_m_n *m_n); void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, enum transcoder cpu_transcoder, struct intel_link_m_n *m_n,
drivers/gpu/drm/i915/display/intel_dp_mst.c +2 -3
@@ -523,9 +523,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,intel_ddi_set_dp_msa (pipe_config, conn_state); -intel_cpu_transcoder_set_m_n (pipe_config, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); +intel_cpu_transcoder_set_m1_n1 (pipe_config, + &pipe_config->dp_m_n); } static void intel_mst_enable_dp(struct intel_atomic_state *state,
drivers/gpu/drm/i915/display/intel_drrs.c +2 -3
@@ -115,9 +115,8 @@ static void intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, enum drrs_refresh_rate_type refresh_type) { - intel_cpu_transcoder_set_m_n(crtc_state, refresh_type == DRRS_LOW_RR ? - &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n, - NULL); + intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ? + &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); } static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
Signature · 1 line
2.34.1
PATCH v2 5/17 drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
As with intel_cpu_transcoder_set_m_n() let's split the readout counterpart into explicit M1/N1 vs. M2/N2 variants as well.
--- drivers/gpu/drm/i915/display/g4x_dp.c | 12 ++++--- drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++---- drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++-------- drivers/gpu/drm/i915/display/intel_display.h | 10 +++--- .../gpu/drm/i915/display/intel_pch_display.c | 8 ++--- 5 files changed, 42 insertions(+), 32 deletions(-)
drivers/gpu/drm/i915/display/g4x_dp.c +7 -5
@@ -337,12 +337,14 @@ static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) {struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); -if (crtc_state->has_pch_encoder) +if (crtc_state->has_pch_encoder) {intel_pch_transcoder_get_m_n (crtc, &crtc_state->dp_m_n); -else -intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, - &crtc_state->dp_m_n, - &crtc_state->dp_m2_n2); + }else { +intel_cpu_transcoder_get_m1_n1 (crtc, crtc_state->cpu_transcoder, + &crtc_state->dp_m_n); +intel_cpu_transcoder_get_m2_n2 (crtc, crtc_state->cpu_transcoder, + &crtc_state->dp_m2_n2); + } } static void intel_dp_get_config(struct intel_encoder *encoder,
drivers/gpu/drm/i915/display/intel_ddi.c +6 -6
@@ -3362,9 +3362,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->lane_count = ((temp &DDI_PORT_WIDTH_MASK ) >>DDI_PORT_WIDTH_SHIFT ) +1 ; -intel_cpu_transcoder_get_m_n (crtc, cpu_transcoder, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); +intel_cpu_transcoder_get_m1_n1 (crtc, cpu_transcoder, + &pipe_config->dp_m_n); +intel_cpu_transcoder_get_m2_n2 (crtc, cpu_transcoder, + &pipe_config->dp_m2_n2);if (DISPLAY_VER (dev_priv) >=11 ) {i915_reg_t dp_tp_ctl =dp_tp_ctl_reg (encoder, pipe_config);
@@ -3401,9 +3402,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->mst_master_transcoder =REG_FIELD_GET (TRANS_DDI_MST_TRANSPORT_SELECT_MASK , temp); -intel_cpu_transcoder_get_m_n (crtc, cpu_transcoder, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); +intel_cpu_transcoder_get_m1_n1 (crtc, cpu_transcoder, + &pipe_config->dp_m_n); pipe_config->infoframes.enable |=intel_hdmi_infoframes_enabled (encoder, pipe_config);
drivers/gpu/drm/i915/display/intel_display.c +19 -13
@@ -3877,29 +3877,35 @@ void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } -void intel_cpu_transcoder_get_m_n (struct intel_crtc *crtc, -enum transcoder transcoder, -struct intel_link_m_n *m_n, -struct intel_link_m_n *m2_n2) +void intel_cpu_transcoder_get_m1_n1 (struct intel_crtc *crtc, +enum transcoder transcoder, +struct intel_link_m_n *m_n) {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe; -if (DISPLAY_VER (dev_priv) >=5 ) { +if (DISPLAY_VER (dev_priv) >=5 )intel_get_m_n (dev_priv, m_n,PIPE_DATA_M1 (transcoder),PIPE_DATA_N1 (transcoder),PIPE_LINK_M1 (transcoder),PIPE_LINK_N1 (transcoder)); - -if (m2_n2 &&transcoder_has_m2_n2 (dev_priv, transcoder)) { -intel_get_m_n (dev_priv, m2_n2, -PIPE_DATA_M2 (transcoder),PIPE_DATA_N2 (transcoder), -PIPE_LINK_M2 (transcoder),PIPE_LINK_N2 (transcoder)); - } - }else { +else intel_get_m_n (dev_priv, m_n,PIPE_DATA_M_G4X (pipe),PIPE_DATA_N_G4X (pipe),PIPE_LINK_M_G4X (pipe),PIPE_LINK_N_G4X (pipe)); - } +} + +void intel_cpu_transcoder_get_m2_n2 (struct intel_crtc *crtc, +enum transcoder transcoder, +struct intel_link_m_n *m_n) +{ +struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); + +if (!transcoder_has_m2_n2 (dev_priv, transcoder)) +return ; + +intel_get_m_n (dev_priv, m_n, +PIPE_DATA_M2 (transcoder),PIPE_DATA_N2 (transcoder), +PIPE_LINK_M2 (transcoder),PIPE_LINK_N2 (transcoder)); } static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
drivers/gpu/drm/i915/display/intel_display.h +6 -4
@@ -608,10 +608,12 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state, const struct intel_link_m_n *m_n);void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state,const struct intel_link_m_n *m_n); -void intel_cpu_transcoder_get_m_n (struct intel_crtc *crtc, -enum transcoder cpu_transcoder, -struct intel_link_m_n *m_n, -struct intel_link_m_n *m2_n2); +void intel_cpu_transcoder_get_m1_n1 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder, +struct intel_link_m_n *m_n); +void intel_cpu_transcoder_get_m2_n2 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder, +struct intel_link_m_n *m_n);void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc,struct intel_link_m_n *m_n); void i9xx_crtc_clock_get(struct intel_crtc *crtc,
drivers/gpu/drm/i915/display/intel_pch_display.c +4 -4
@@ -386,8 +386,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>FDI_DP_PORT_WIDTH_SHIFT ) +1 ; -intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, - &crtc_state->fdi_m_n,NULL ); +intel_cpu_transcoder_get_m1_n1 (crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n);if (HAS_PCH_IBX (dev_priv)) {/*
@@ -510,8 +510,8 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>FDI_DP_PORT_WIDTH_SHIFT ) +1 ; -intel_cpu_transcoder_get_m_n (crtc, crtc_state->cpu_transcoder, - &crtc_state->fdi_m_n,NULL ); +intel_cpu_transcoder_get_m1_n1 (crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n); crtc_state->hw.adjusted_mode.crtc_clock =lpt_get_iclkip (dev_priv); }
Signature · 1 line
2.34.1
PATCH v2 6/17 drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Instead of passing in the whole crtc state let's pass in just the bits of state we need. This will help with the DRRS code which shouldn't really be accessing the atomic state stuff directly as it gets called outside the normal atomic flows.
--- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++-- drivers/gpu/drm/i915/display/intel_display.c | 37 ++++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 6 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- drivers/gpu/drm/i915/display/intel_drrs.c | 5 ++- 5 files changed, 32 insertions(+), 25 deletions(-)
drivers/gpu/drm/i915/display/intel_ddi.c +4 -2
@@ -2498,6 +2498,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) {struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); +enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;if (DISPLAY_VER (dev_priv) >=12 )tgl_ddi_pre_enable_dp (state, encoder, crtc_state, conn_state);
@@ -2510,9 +2512,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST )) {intel_ddi_set_dp_msa (crtc_state, conn_state); -intel_cpu_transcoder_set_m1_n1 (crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &crtc_state->dp_m2_n2); } }
drivers/gpu/drm/i915/display/intel_display.c +18 -19
@@ -118,7 +118,7 @@static void intel_set_transcoder_timings (const struct intel_crtc_state *crtc_state);static void intel_set_pipe_src_size (const struct intel_crtc_state *crtc_state); -static void intel_pch_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, +static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc,const struct intel_link_m_n *m_n);static void i9xx_set_pipeconf (const struct intel_crtc_state *crtc_state);static void ilk_set_pipeconf (const struct intel_crtc_state *crtc_state);
@@ -1816,6 +1816,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))
@@ -1836,12 +1837,11 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,if (intel_crtc_has_dp_encoder (new_crtc_state)) {if (new_crtc_state->has_pch_encoder) { -intel_pch_transcoder_set_m_n (new_crtc_state, - &new_crtc_state->dp_m_n); +intel_pch_transcoder_set_m_n (crtc, &new_crtc_state->dp_m_n); }else { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (new_crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &new_crtc_state->dp_m2_n2); } }
@@ -1850,7 +1850,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,intel_set_pipe_src_size (new_crtc_state);if (new_crtc_state->has_pch_encoder) -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->fdi_m_n);ilk_set_pipeconf (new_crtc_state);
@@ -2017,7 +2017,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta crtc_state->pixel_multiplier - 1);if (crtc_state->has_pch_encoder) -intel_cpu_transcoder_set_m1_n1 (crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->fdi_m_n);hsw_set_frame_start_delay (crtc_state);
@@ -2452,15 +2452,16 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (new_crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &new_crtc_state->dp_m2_n2); }
@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m2_n2); }
@@ -3140,10 +3142,9 @@ static void intel_set_m_n(struct drm_i915_private *i915,intel_de_write (i915, link_n_reg, m_n->link_n); } -static void intel_pch_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, +static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe;
@@ -3165,13 +3166,12 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,return DISPLAY_VER (dev_priv) ==7 ||IS_CHERRYVIEW (dev_priv); } -void intel_cpu_transcoder_set_m1_n1 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc, +enum transcoder transcoder,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe; -enum transcoder transcoder = crtc_state->cpu_transcoder;if (DISPLAY_VER (dev_priv) >=5 ) intel_set_m_n(dev_priv, m_n,
@@ -3183,12 +3183,11 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state, PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); } -void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m2_n2 (struct intel_crtc *crtc, +enum transcoder transcoder,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -enum transcoder transcoder = crtc_state->cpu_transcoder;if (!transcoder_has_m2_n2 (dev_priv, transcoder))return ;
drivers/gpu/drm/i915/display/intel_display.h +4 -2
@@ -604,9 +604,11 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); -void intel_cpu_transcoder_set_m1_n1 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n); -void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m2_n2 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n); void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, enum transcoder cpu_transcoder,
drivers/gpu/drm/i915/display/intel_dp_mst.c +2 -1
@@ -473,6 +473,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,struct intel_digital_port *dig_port = intel_mst->primary;struct intel_dp *intel_dp = &dig_port->dp;struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); +struct intel_crtc *crtc =to_intel_crtc (pipe_config->uapi.crtc);struct intel_connector *connector =to_intel_connector (conn_state->connector);int ret;
@@ -523,7 +524,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,intel_ddi_set_dp_msa (pipe_config, conn_state); -intel_cpu_transcoder_set_m1_n1 (pipe_config, +intel_cpu_transcoder_set_m1_n1 (crtc, pipe_config->cpu_transcoder, &pipe_config->dp_m_n); }
drivers/gpu/drm/i915/display/intel_drrs.c +4 -1
@@ -115,7 +115,10 @@ static void intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, enum drrs_refresh_rate_type refresh_type) { - intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ? + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + +intel_cpu_transcoder_set_m1_n1 (crtc, crtc_state->cpu_transcoder, + refresh_type ==DRRS_LOW_RR ? &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); }
Signature · 1 line
2.34.1
Jani Nikula
maintainerRe: [Intel-gfx] [PATCH v2 06/17] drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()
Quoted 6 lines · Ville Syrjala
From: Ville Syrjälä <[email protected]>
Instead of passing in the whole crtc state let's pass in just the bits of state we need. This will help with the DRRS code which shouldn't really be accessing the atomic state stuff directly as it gets called outside the normal atomic flows.
Overall looks good, one bug crept in.
Quoted 115 lines
Signed-off-by Ville Syrjälä <[email protected]>--- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++-- drivers/gpu/drm/i915/display/intel_display.c | 37 ++++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 6 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- drivers/gpu/drm/i915/display/intel_drrs.c | 5 ++- 5 files changed, 32 insertions(+), 25 deletions(-)drivers/gpu/drm/i915/display/intel_ddi.c +4
-2@@ -2498,6 +2498,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) {struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); +enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;if (DISPLAY_VER (dev_priv) >=12 )tgl_ddi_pre_enable_dp (state, encoder, crtc_state, conn_state);@@ -2510,9 +2512,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST )) {intel_ddi_set_dp_msa (crtc_state, conn_state); -intel_cpu_transcoder_set_m1_n1 (crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &crtc_state->dp_m2_n2); } }drivers/gpu/drm/i915/display/intel_display.c +11
-9@@ -118,7 +118,7 @@static void intel_set_transcoder_timings (const struct intel_crtc_state *crtc_state);static void intel_set_pipe_src_size (const struct intel_crtc_state *crtc_state); -static void intel_pch_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, +static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc,const struct intel_link_m_n *m_n);static void i9xx_set_pipeconf (const struct intel_crtc_state *crtc_state);static void ilk_set_pipeconf (const struct intel_crtc_state *crtc_state);@@ -1816,6 +1816,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))@@ -1836,12 +1837,11 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,if (intel_crtc_has_dp_encoder (new_crtc_state)) {if (new_crtc_state->has_pch_encoder) { -intel_pch_transcoder_set_m_n (new_crtc_state, - &new_crtc_state->dp_m_n); +intel_pch_transcoder_set_m_n (crtc, &new_crtc_state->dp_m_n); }else { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (new_crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &new_crtc_state->dp_m2_n2); } }@@ -1850,7 +1850,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,intel_set_pipe_src_size (new_crtc_state);if (new_crtc_state->has_pch_encoder) -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->fdi_m_n);ilk_set_pipeconf (new_crtc_state);@@ -2017,7 +2017,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta crtc_state->pixel_multiplier - 1);if (crtc_state->has_pch_encoder) -intel_cpu_transcoder_set_m1_n1 (crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->fdi_m_n);hsw_set_frame_start_delay (crtc_state);@@ -2452,15 +2452,16 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (new_crtc_state, +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &new_crtc_state->dp_m2_n2); }@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;
drivers/gpu/drm/i915/display/intel_display.c static void i9xx_crtc_enable(struct intel_atomic_state *state, · line 2521
Quoted 10 lines
drivers/gpu/drm/i915/display/intel_display.c +2
-2if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); - intel_cpu_transcoder_set_m2_n2(new_crtc_state, + intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
m1_n1 copy paste fail?
Quoted 100 lines
drivers/gpu/drm/i915/display/intel_display.c +5
-8&new_crtc_state->dp_m2_n2); }@@ -3140,10 +3142,9 @@ static void intel_set_m_n(struct drm_i915_private *i915,intel_de_write (i915, link_n_reg, m_n->link_n); } -static void intel_pch_transcoder_set_m_n (const struct intel_crtc_state *crtc_state, +static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe;@@ -3165,13 +3166,12 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,return DISPLAY_VER (dev_priv) ==7 ||IS_CHERRYVIEW (dev_priv); } -void intel_cpu_transcoder_set_m1_n1 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc, +enum transcoder transcoder,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe; -enum transcoder transcoder = crtc_state->cpu_transcoder;if (DISPLAY_VER (dev_priv) >=5 ) intel_set_m_n(dev_priv, m_n,@@ -3183,12 +3183,11 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state, PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); } -void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m2_n2 (struct intel_crtc *crtc, +enum transcoder transcoder,const struct intel_link_m_n *m_n) { -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -enum transcoder transcoder = crtc_state->cpu_transcoder;if (!transcoder_has_m2_n2 (dev_priv, transcoder))return ;drivers/gpu/drm/i915/display/intel_display.h +4
-2@@ -604,9 +604,11 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); -void intel_cpu_transcoder_set_m1_n1 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n); -void intel_cpu_transcoder_set_m2_n2 (const struct intel_crtc_state *crtc_state, +void intel_cpu_transcoder_set_m2_n2 (struct intel_crtc *crtc, +enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n); void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, enum transcoder cpu_transcoder,drivers/gpu/drm/i915/display/intel_dp_mst.c +2
-1@@ -473,6 +473,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,struct intel_digital_port *dig_port = intel_mst->primary;struct intel_dp *intel_dp = &dig_port->dp;struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); +struct intel_crtc *crtc =to_intel_crtc (pipe_config->uapi.crtc);struct intel_connector *connector =to_intel_connector (conn_state->connector);int ret;@@ -523,7 +524,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,intel_ddi_set_dp_msa (pipe_config, conn_state); -intel_cpu_transcoder_set_m1_n1 (pipe_config, +intel_cpu_transcoder_set_m1_n1 (crtc, pipe_config->cpu_transcoder, &pipe_config->dp_m_n); }drivers/gpu/drm/i915/display/intel_drrs.c +4
-1@@ -115,7 +115,10 @@ static void intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, enum drrs_refresh_rate_type refresh_type) { - intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ? + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + +intel_cpu_transcoder_set_m1_n1 (crtc, crtc_state->cpu_transcoder, + refresh_type ==DRRS_LOW_RR ? &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); }
Signature · 1 line
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 06/17] drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()
Quoted 10 lines · Jani Nikula
Quoted 10 lines
drivers/gpu/drm/i915/display/intel_display.c +1
-0@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;
Quoted 8 lines
drivers/gpu/drm/i915/display/intel_display.c static void i9xx_crtc_enable(struct intel_atomic_state *state, · line 2521
Quoted 6 lines
drivers/gpu/drm/i915/display/intel_display.c +2
-2if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); - intel_cpu_transcoder_set_m2_n2(new_crtc_state, + intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
m1_n1copy paste fail?
Yep. I guess we don't have g4x+DP in CI so this went unnoticed. I'll give it a quick smoke test on my ctg+DP to make sure nothing else slipped through.
Signature · 2 lines
Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 06/17] drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()
Quoted 20 lines · Ville Syrjälä
Quoted 10 lines · Jani Nikula
Quoted 10 lines
drivers/gpu/drm/i915/display/intel_display.c +1
-0@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ;Quoted 8 lines
drivers/gpu/drm/i915/display/intel_display.c static void i9xx_crtc_enable(struct intel_atomic_state *state, · line 2521
Quoted 6 lines
drivers/gpu/drm/i915/display/intel_display.c +2
-2if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (new_crtc_state, +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &new_crtc_state->dp_m_n); - intel_cpu_transcoder_set_m2_n2(new_crtc_state, + intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
m1_n1copy paste fail?
Quoted 1 line
Yep. I guess we don't have g4x+DP in CI so this went unnoticed.
And it wouldn't have helped to have one since the introduction of i9xx_configure_cpu_transcoder() in pathc 9 already fixed this. So the only way to hit it would have been to bisect through the series.
Signature · 2 lines
Ville Syrjälä Intel
PATCH v2 7/17 drm/i915: Move PCH transcoder M/N setup into the PCH code
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Do the PCH transcoder M/N setup next to where all the other PCH transcoder stuff is programmed. Matches the spec modeset sequence better.
--- drivers/gpu/drm/i915/display/g4x_dp.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 66 +++++-------------- drivers/gpu/drm/i915/display/intel_display.h | 12 +++- .../gpu/drm/i915/display/intel_pch_display.c | 24 +++++++ .../gpu/drm/i915/display/intel_pch_display.h | 4 ++ 5 files changed, 57 insertions(+), 50 deletions(-)
drivers/gpu/drm/i915/display/g4x_dp.c +1 -0
@@ -18,6 +18,7 @@#include "intel_fifo_underrun.h" #include "intel_hdmi.h" #include "intel_hotplug.h" +#include "intel_pch_display.h" #include "intel_pps.h" #include "vlv_sideband.h"
drivers/gpu/drm/i915/display/intel_display.c +18 -48
104 lines not on this page · raw message
drivers/gpu/drm/i915/display/intel_display.h +10 -2
@@ -27,6 +27,8 @@#include <drm/drm_util.h> +#include "i915_reg_defs.h" +enum drm_scaling_filter ;struct dpll ;struct drm_connector ;
@@ -604,6 +606,14 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); +void intel_set_m_n (struct drm_i915_private *i915, +const struct intel_link_m_n *m_n, +i915_reg_t data_m_reg,i915_reg_t data_n_reg, +i915_reg_t link_m_reg,i915_reg_t link_n_reg); +void intel_get_m_n (struct drm_i915_private *i915, +struct intel_link_m_n *m_n, +i915_reg_t data_m_reg,i915_reg_t data_n_reg, +i915_reg_t link_m_reg,i915_reg_t link_n_reg);void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc,enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n);
@@ -616,8 +626,6 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,void intel_cpu_transcoder_get_m2_n2 (struct intel_crtc *crtc,enum transcoder cpu_transcoder,struct intel_link_m_n *m_n); -void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, -struct intel_link_m_n *m_n);void i9xx_crtc_clock_get (struct intel_crtc *crtc,struct intel_crtc_state *pipe_config);int intel_dotclock_calculate (int link_freq,const struct intel_link_m_n *m_n);
drivers/gpu/drm/i915/display/intel_pch_display.c +24 -0
@@ -88,6 +88,28 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, pipe_name(pipe)); } +static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc, +const struct intel_link_m_n *m_n) +{ +struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum pipe pipe = crtc->pipe; + +intel_set_m_n (dev_priv, m_n, +PCH_TRANS_DATA_M1 (pipe),PCH_TRANS_DATA_N1 (pipe), +PCH_TRANS_LINK_M1 (pipe),PCH_TRANS_LINK_N1 (pipe)); +} + +void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, +struct intel_link_m_n *m_n) +{ +struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum pipe pipe = crtc->pipe; + +intel_get_m_n (dev_priv, m_n, +PCH_TRANS_DATA_M1 (pipe),PCH_TRANS_DATA_N1 (pipe), +PCH_TRANS_LINK_M1 (pipe),PCH_TRANS_LINK_N1 (pipe)); +} +static void ilk_pch_transcoder_set_timings (const struct intel_crtc_state *crtc_state,enum pipe pch_transcoder) {
@@ -278,6 +300,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,/* set transcoder timing, panel must allow it */ assert_pps_unlocked (dev_priv, pipe); +if (intel_crtc_has_dp_encoder (crtc_state)) +intel_pch_transcoder_set_m_n (crtc, &crtc_state->dp_m_n);ilk_pch_transcoder_set_timings (crtc_state, pipe);intel_fdi_normal_train (crtc);
drivers/gpu/drm/i915/display/intel_pch_display.h +4 -0
@@ -9,6 +9,7 @@struct intel_atomic_state ;struct intel_crtc ;struct intel_crtc_state ; +struct intel_link_m_n ;void ilk_pch_pre_enable (struct intel_atomic_state *state,struct intel_crtc *crtc);
@@ -26,4 +27,7 @@ void lpt_pch_disable(struct intel_atomic_state *state, struct intel_crtc *crtc);void lpt_pch_get_config (struct intel_crtc_state *crtc_state); +void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, +struct intel_link_m_n *m_n); +#endif
Signature · 1 line
2.34.1
PATCH v2 8/17 drm/i915: Move M/N setup to a more logical place on ddi platforms
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Let's do the cpu transcoder M/N setup next to where we program most other cpu transcoder timings/etc.
--- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--------- drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ---- 3 files changed, 11 insertions(+), 17 deletions(-)
drivers/gpu/drm/i915/display/intel_ddi.c +1 -9
@@ -2498,8 +2498,6 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) {struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); -struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); -enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;if (DISPLAY_VER (dev_priv) >=12 )tgl_ddi_pre_enable_dp (state, encoder, crtc_state, conn_state);
@@ -2509,14 +2507,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,/* MST will call a setting of MSA after an allocating of Virtual Channel * from MST encoder pre_enable callback. */ -if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST )) { +if (!intel_crtc_has_type (crtc_state,INTEL_OUTPUT_DP_MST ))intel_ddi_set_dp_msa (crtc_state, conn_state); - -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, - &crtc_state->dp_m2_n2); - } } static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
drivers/gpu/drm/i915/display/intel_display.c +10 -4
@@ -2003,16 +2003,22 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_stastruct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; +if (crtc_state->has_pch_encoder) { +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, + &crtc_state->fdi_m_n); + }else if (intel_crtc_has_dp_encoder (crtc_state)) { +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, + &crtc_state->dp_m_n); +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, + &crtc_state->dp_m2_n2); + } +intel_set_transcoder_timings (crtc_state);if (cpu_transcoder !=TRANSCODER_EDP )intel_de_write (dev_priv,PIPE_MULT (cpu_transcoder), crtc_state->pixel_multiplier -1 ); -if (crtc_state->has_pch_encoder) -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &crtc_state->fdi_m_n); -hsw_set_frame_start_delay (crtc_state);hsw_set_transconf (crtc_state);
drivers/gpu/drm/i915/display/intel_dp_mst.c +0 -4
@@ -473,7 +473,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,struct intel_digital_port *dig_port = intel_mst->primary;struct intel_dp *intel_dp = &dig_port->dp;struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev); -struct intel_crtc *crtc =to_intel_crtc (pipe_config->uapi.crtc);struct intel_connector *connector =to_intel_connector (conn_state->connector);int ret;
@@ -523,9 +522,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,intel_ddi_enable_pipe_clock (encoder, pipe_config);intel_ddi_set_dp_msa (pipe_config, conn_state); - -intel_cpu_transcoder_set_m1_n1 (crtc, pipe_config->cpu_transcoder, - &pipe_config->dp_m_n); } static void intel_mst_enable_dp(struct intel_atomic_state *state,
Signature · 1 line
2.34.1
PATCH v2 9/17 drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Follow the path laid out by hsw+ and extract helpers to configure the cpu transcoder for earlier platforms as well.
--- drivers/gpu/drm/i915/display/intel_display.c | 68 ++++++++++---------- 1 file changed, 35 insertions(+), 33 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +35 -33
@@ -1808,13 +1808,29 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat plane->disable_arm (plane, crtc_state); } +static void ilk_configure_cpu_transcoder (const struct intel_crtc_state *crtc_state) +{ +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); +enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + +if (crtc_state->has_pch_encoder) { +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->fdi_m_n); + }else if (intel_crtc_has_dp_encoder (crtc_state)) { +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->dp_m_n); +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &crtc_state->dp_m2_n2); + } + +intel_set_transcoder_timings (crtc_state); + +ilk_set_pipeconf (crtc_state); +} +static void ilk_crtc_enable (struct intel_atomic_state *state,struct intel_crtc *crtc) {const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))
@@ -1833,21 +1849,10 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,intel_set_cpu_fifo_underrun_reporting (dev_priv, pipe, false);intel_set_pch_fifo_underrun_reporting (dev_priv, pipe, false); -if (new_crtc_state->has_pch_encoder) { -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &new_crtc_state->fdi_m_n); - }else if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, - &new_crtc_state->dp_m2_n2); - } +ilk_configure_cpu_transcoder (new_crtc_state); -intel_set_transcoder_timings (new_crtc_state);intel_set_pipe_src_size (new_crtc_state); -ilk_set_pipeconf (new_crtc_state); - crtc->active = true;intel_encoders_pre_enable (state, crtc);
@@ -2445,26 +2450,34 @@ static void modeset_put_crtc_power_domains(struct intel_crtc *crtc, domains); } +static void i9xx_configure_cpu_transcoder (const struct intel_crtc_state *crtc_state) +{ +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); +enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + +if (intel_crtc_has_dp_encoder (crtc_state)) { +intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, &crtc_state->dp_m_n); +intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, &crtc_state->dp_m2_n2); + } + +intel_set_transcoder_timings (crtc_state); + +i9xx_set_pipeconf (crtc_state); +} +static void valleyview_crtc_enable (struct intel_atomic_state *state,struct intel_crtc *crtc) {const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ; -if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m2_n2 (crtc, cpu_transcoder, - &new_crtc_state->dp_m2_n2); - } +i9xx_configure_cpu_transcoder (new_crtc_state); -intel_set_transcoder_timings (new_crtc_state);intel_set_pipe_src_size (new_crtc_state);if (IS_CHERRYVIEW (dev_priv) && pipe ==PIPE_B ) {
@@ -2472,8 +2485,6 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,intel_de_write (dev_priv,CHV_CANVAS (pipe),0 ); } -i9xx_set_pipeconf (new_crtc_state); - crtc->active = true;intel_set_cpu_fifo_underrun_reporting (dev_priv, pipe, true);
@@ -2508,24 +2519,15 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,const struct intel_crtc_state *new_crtc_state =intel_atomic_get_new_crtc_state (state, crtc);struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;enum pipe pipe = crtc->pipe;if (drm_WARN_ON (&dev_priv->drm, crtc->active))return ; -if (intel_crtc_has_dp_encoder (new_crtc_state)) { -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &new_crtc_state->dp_m_n); -intel_cpu_transcoder_set_m1_n1 (crtc, cpu_transcoder, - &new_crtc_state->dp_m2_n2); - } +i9xx_configure_cpu_transcoder (new_crtc_state); -intel_set_transcoder_timings (new_crtc_state);intel_set_pipe_src_size (new_crtc_state); -i9xx_set_pipeconf (new_crtc_state); - crtc->active = true;if (DISPLAY_VER (dev_priv) !=2 )
Signature · 1 line
2.34.1
PATCH v2 10/17 drm/i915: Disable DRRS on IVB/HSW port != A
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Currently we allow DRRS on IVB PCH ports, but we're missing a few programming steps meaning it is guaranteed to not work. And on HSW DRRS is not supported on anything but port A ever as only transcoder EDP has the M2/N2 registers (though I'm not sure if HSW ever has eDP on any other port).
Starting from BDW all transcoders have the dynamically reprogrammable M/N registers so DRRS could work on any port.
Stop initializing DRRS on ports where it cannot possibly work.
--- drivers/gpu/drm/i915/display/intel_drrs.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/gpu/drm/i915/display/intel_drrs.c +8 -0
@@ -413,6 +413,7 @@ intel_drrs_init(struct intel_connector *connector, struct drm_display_mode *fixed_mode) {struct drm_i915_private *dev_priv =to_i915 (connector->base.dev); +struct intel_encoder *encoder = connector->encoder;struct drm_display_mode *downclock_mode =NULL ;INIT_DELAYED_WORK (&dev_priv->drrs.work, intel_drrs_downclock_work);
@@ -424,6 +425,13 @@ intel_drrs_init(struct intel_connector *connector,return NULL ; } +if ((DISPLAY_VER (dev_priv) <8 && !HAS_GMCH (dev_priv)) && + encoder->port !=PORT_A ) { +drm_dbg_kms (&dev_priv->drm, +"DRRS only supported on eDP port A\n" ); +return NULL ; + } +if (dev_priv->vbt.drrs_type !=SEAMLESS_DRRS_SUPPORT ) {drm_dbg_kms (&dev_priv->drm,"VBT doesn't support DRRS\n" );return NULL ;
Signature · 1 line
2.34.1
PATCH v2 11/17 drm/i915: Extract can_enable_drrs()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Pull the "can we do DRRS?" check into helper in order to reduce the clutter in intel_drrs_compute_config().
--- drivers/gpu/drm/i915/display/intel_drrs.c | 31 ++++++++++++++--------- 1 file changed, 19 insertions(+), 12 deletions(-)
drivers/gpu/drm/i915/display/intel_drrs.c +19 -12
@@ -47,17 +47,13 @@* requested by userspace. */ -void -intel_drrs_compute_config (struct intel_dp *intel_dp, -struct intel_crtc_state *pipe_config, -int output_bpp,bool constant_n) +static bool can_enable_drrs (struct intel_connector *connector, +const struct intel_crtc_state *pipe_config) { -struct intel_connector *intel_connector = intel_dp->attached_connector; -struct drm_i915_private *dev_priv =dp_to_i915 (intel_dp); -int pixel_clock; +const struct drm_i915_private *i915 =to_i915 (connector->base.dev);if (pipe_config->vrr.enable) -return ; +return false;/* * DRRS and PSR can't be enable together, so giving preference to PSR
@@ -66,15 +62,26 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,* after intel_psr_compute_config(). */ if (pipe_config->has_psr) -return ; +return false; -if (!intel_connector->panel.downclock_mode || - dev_priv->drrs.type !=SEAMLESS_DRRS_SUPPORT ) +return connector->panel.downclock_mode && + i915->drrs.type ==SEAMLESS_DRRS_SUPPORT ; +} + +void +intel_drrs_compute_config (struct intel_dp *intel_dp, +struct intel_crtc_state *pipe_config, +int output_bpp,bool constant_n) +{ +struct intel_connector *connector = intel_dp->attached_connector; +int pixel_clock; + +if (!can_enable_drrs (connector, pipe_config))return ; pipe_config->has_drrs = true; - pixel_clock = intel_connector->panel.downclock_mode->clock; + pixel_clock = connector->panel.downclock_mode->clock;if (pipe_config->splitter.enable) pixel_clock /= pipe_config->splitter.link_count;
Signature · 1 line
2.34.1
PATCH v2 12/17 drm/i915: Fix intel_cpu_transcoder_has_m2_n2()
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp). Make the code reflect that.
--- drivers/gpu/drm/i915/display/intel_display.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +1 -5
@@ -3149,11 +3149,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,if (IS_HASWELL (dev_priv))return transcoder ==TRANSCODER_EDP ; -/* -* Strictly speaking some registers are available before -* gen7, but we only support DRRS on gen7+ -*/ -return DISPLAY_VER (dev_priv) ==7 ||IS_CHERRYVIEW (dev_priv); +return IS_DISPLAY_VER (dev_priv,5 ,7 ) ||IS_CHERRYVIEW (dev_priv); } void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
Signature · 1 line
2.34.1
Jani Nikula
maintainerRe: [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix intel_cpu_transcoder_has_m2_n2()
Quoted 4 lines · Ville Syrjala
From: Ville Syrjälä <[email protected]>
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp). Make the code reflect that.
Nitpick, it's not called intel_cpu_transcoder_has_m2_n2() until in the next patch.
Side note, I've also been looking at this bit in intel_drrs_set_state():
if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type); else if (DISPLAY_VER(dev_priv) > 6) intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
and wondering if that should be deduplicated with the transcoder_has_m2_n2() somehow. This is all a bit confusing with the slightly different conditions.
BR,
Jani.
Quoted 23 lines
Signed-off-by Ville Syrjälä <[email protected]>--- drivers/gpu/drm/i915/display/intel_display.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)drivers/gpu/drm/i915/display/intel_display.c +1
-5@@ -3149,11 +3149,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,if (IS_HASWELL (dev_priv))return transcoder ==TRANSCODER_EDP ; -/* -* Strictly speaking some registers are available before -* gen7, but we only support DRRS on gen7+ -*/ -return DISPLAY_VER (dev_priv) ==7 ||IS_CHERRYVIEW (dev_priv); +return IS_DISPLAY_VER (dev_priv,5 ,7 ) ||IS_CHERRYVIEW (dev_priv); } void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
Signature · 1 line
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 12/17] drm/i915: Fix intel_cpu_transcoder_has_m2_n2()
Quoted 11 lines · Jani Nikula
Quoted 4 lines · Ville Syrjala
From: Ville Syrjälä <[email protected]>
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp). Make the code reflect that.
Nitpick, it's not called
intel_cpu_transcoder_has_m2_n2()until in the next patch.Side note, I've also been looking at this bit in
intel_drrs_set_state():
Quoted 8 lines
if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type); else if (DISPLAY_VER(dev_priv) > 6) intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);and wondering if that should be deduplicated with the
transcoder_has_m2_n2()somehow. This is all a bit confusing with the slightly different conditions.
Yeah, I have a patch to use intel_cpu_transcoder_has_m2_n2() for this already on my drrs branch. It just didn't make the cut for this series for some arbitrary reason.
The other place we could perhaps use intel_cpu_transcoder_has_m2_n2() is the PIPE_CONF_CHECK_ALT vs. checking both m_n and m2_n2. But I don't really want the logic there to depend on the states it's trying to compare, so I think a naked platform check there is better.
Signature · 2 lines
Ville Syrjälä Intel
PATCH v2 13/17 drm/i915: Clear DP M2/N2 when not doing DRRS
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Make life simpler by always programming DP M2/N2 with a consistent value. This will lets use do state readout+chec unconditionally.
I was first going to just set M2/N2=M1/N1 but then it occurred to me that it might interfere with fastboot on account of BIOS likely leaving the registers zeroed. So let's zero out the values instead (except TU where a zero register value actually means '1'). Still not sure that's the best approach but lets go with it for now.
--- drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++---- drivers/gpu/drm/i915/display/intel_display.h | 3 +++ drivers/gpu/drm/i915/display/intel_drrs.c | 6 +++++- 3 files changed, 19 insertions(+), 5 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +11 -4
@@ -3132,6 +3132,13 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) } } +void intel_zero_m_n (struct intel_link_m_n *m_n) +{ +/* corresponds to 0 register value */ +memset (m_n,0 ,sizeof (*m_n)); + m_n->tu =1 ; +} + void intel_set_m_n(struct drm_i915_private *i915, const struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg,
@@ -3143,8 +3150,8 @@ void intel_set_m_n(struct drm_i915_private *i915,intel_de_write (i915, link_n_reg, m_n->link_n); } -static bool transcoder_has_m2_n2 (struct drm_i915_private *dev_priv, -enum transcoder transcoder) +bool intel_cpu_transcoder_has_m2_n2 (struct drm_i915_private *dev_priv, +enum transcoder transcoder) {if (IS_HASWELL (dev_priv))return transcoder ==TRANSCODER_EDP ;
@@ -3175,7 +3182,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -if (!transcoder_has_m2_n2 (dev_priv, transcoder)) +if (!intel_cpu_transcoder_has_m2_n2 (dev_priv, transcoder))return ; intel_set_m_n(dev_priv, m_n,
@@ -3873,7 +3880,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); -if (!transcoder_has_m2_n2 (dev_priv, transcoder)) +if (!intel_cpu_transcoder_has_m2_n2 (dev_priv, transcoder))return ; intel_get_m_n(dev_priv, m_n,
drivers/gpu/drm/i915/display/intel_display.h +3 -0
@@ -606,6 +606,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);void intel_display_prepare_reset (struct drm_i915_private *dev_priv);void intel_display_finish_reset (struct drm_i915_private *dev_priv); +void intel_zero_m_n (struct intel_link_m_n *m_n); void intel_set_m_n(struct drm_i915_private *i915, const struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg,
@@ -614,6 +615,8 @@ void intel_get_m_n(struct drm_i915_private *i915,struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg); +bool intel_cpu_transcoder_has_m2_n2 (struct drm_i915_private *dev_priv, +enum transcoder transcoder);void intel_cpu_transcoder_set_m1_n1 (struct intel_crtc *crtc,enum transcoder cpu_transcoder,const struct intel_link_m_n *m_n);
drivers/gpu/drm/i915/display/intel_drrs.c +5 -1
@@ -74,10 +74,14 @@ intel_drrs_compute_config(struct intel_dp *intel_dp, int output_bpp, bool constant_n) {struct intel_connector *connector = intel_dp->attached_connector; +struct drm_i915_private *i915 =to_i915 (connector->base.dev);int pixel_clock; -if (!can_enable_drrs (connector, pipe_config)) +if (!can_enable_drrs (connector, pipe_config)) { +if (intel_cpu_transcoder_has_m2_n2 (i915, pipe_config->cpu_transcoder)) +intel_zero_m_n (&pipe_config->dp_m2_n2);return ; + } pipe_config->has_drrs = true;
Signature · 1 line
2.34.1
PATCH v2 14/17 drm/i915: Program pch transcoder m2/n2
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
Program the PCH transcoder M2/N2 values appropriately. We're still missing a few things for PCH port DRRS but at least this means we can do readout/state check for dp_m2_n2 unconditionally.
--- drivers/gpu/drm/i915/display/g4x_dp.c | 3 +- .../gpu/drm/i915/display/intel_pch_display.c | 36 +++++++++++++++---- .../gpu/drm/i915/display/intel_pch_display.h | 6 ++-- 3 files changed, 36 insertions(+), 9 deletions(-)
drivers/gpu/drm/i915/display/g4x_dp.c +2 -1
@@ -339,7 +339,8 @@ static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc);if (crtc_state->has_pch_encoder) { -intel_pch_transcoder_get_m_n (crtc, &crtc_state->dp_m_n); +intel_pch_transcoder_get_m1_n1 (crtc, &crtc_state->dp_m_n); +intel_pch_transcoder_get_m2_n2 (crtc, &crtc_state->dp_m2_n2); }else {intel_cpu_transcoder_get_m1_n1 (crtc, crtc_state->cpu_transcoder, &crtc_state->dp_m_n);
drivers/gpu/drm/i915/display/intel_pch_display.c +30 -6
@@ -88,8 +88,8 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, pipe_name(pipe)); } -static void intel_pch_transcoder_set_m_n (struct intel_crtc *crtc, -const struct intel_link_m_n *m_n) +static void intel_pch_transcoder_set_m1_n1 (struct intel_crtc *crtc, +const struct intel_link_m_n *m_n) {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe;
@@ -99,8 +99,19 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } -void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, -struct intel_link_m_n *m_n) +static void intel_pch_transcoder_set_m2_n2 (struct intel_crtc *crtc, +const struct intel_link_m_n *m_n) +{ +struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum pipe pipe = crtc->pipe; + +intel_set_m_n (dev_priv, m_n, +PCH_TRANS_DATA_M2 (pipe),PCH_TRANS_DATA_N2 (pipe), +PCH_TRANS_LINK_M2 (pipe),PCH_TRANS_LINK_N2 (pipe)); +} + +void intel_pch_transcoder_get_m1_n1 (struct intel_crtc *crtc, +struct intel_link_m_n *m_n) {struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev);enum pipe pipe = crtc->pipe;
@@ -110,6 +121,17 @@ void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } +void intel_pch_transcoder_get_m2_n2 (struct intel_crtc *crtc, +struct intel_link_m_n *m_n) +{ +struct drm_i915_private *dev_priv =to_i915 (crtc->base.dev); +enum pipe pipe = crtc->pipe; + +intel_get_m_n (dev_priv, m_n, +PCH_TRANS_DATA_M2 (pipe),PCH_TRANS_DATA_N2 (pipe), +PCH_TRANS_LINK_M2 (pipe),PCH_TRANS_LINK_N2 (pipe)); +} +static void ilk_pch_transcoder_set_timings (const struct intel_crtc_state *crtc_state,enum pipe pch_transcoder) {
@@ -300,8 +322,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,/* set transcoder timing, panel must allow it */ assert_pps_unlocked (dev_priv, pipe); -if (intel_crtc_has_dp_encoder (crtc_state)) -intel_pch_transcoder_set_m_n (crtc, &crtc_state->dp_m_n); +if (intel_crtc_has_dp_encoder (crtc_state)) { +intel_pch_transcoder_set_m1_n1 (crtc, &crtc_state->dp_m_n); +intel_pch_transcoder_set_m2_n2 (crtc, &crtc_state->dp_m2_n2); + }ilk_pch_transcoder_set_timings (crtc_state, pipe);intel_fdi_normal_train (crtc);
drivers/gpu/drm/i915/display/intel_pch_display.h +4 -2
@@ -27,7 +27,9 @@ void lpt_pch_disable(struct intel_atomic_state *state, struct intel_crtc *crtc);void lpt_pch_get_config (struct intel_crtc_state *crtc_state); -void intel_pch_transcoder_get_m_n (struct intel_crtc *crtc, -struct intel_link_m_n *m_n); +void intel_pch_transcoder_get_m1_n1 (struct intel_crtc *crtc, +struct intel_link_m_n *m_n); +void intel_pch_transcoder_get_m2_n2 (struct intel_crtc *crtc, +struct intel_link_m_n *m_n);#endif
Signature · 1 line
2.34.1
PATCH v2 15/17 drm/i915: Dump dp_m2_n2 always
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
No point in special casing the dp_m2_n2 dumping. Just do it always.
--- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +5 -5
@@ -5626,11 +5626,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,if (intel_crtc_has_dp_encoder (pipe_config)) {intel_dump_m_n_config (pipe_config,"dp m_n" , - pipe_config->lane_count, &pipe_config->dp_m_n); -if (pipe_config->has_drrs) -intel_dump_m_n_config (pipe_config,"dp m2_n2" , - pipe_config->lane_count, - &pipe_config->dp_m2_n2); + pipe_config->lane_count, + &pipe_config->dp_m_n); +intel_dump_m_n_config (pipe_config,"dp m2_n2" , + pipe_config->lane_count, + &pipe_config->dp_m2_n2); } drm_dbg_kms(&dev_priv->drm,
Signature · 1 line
2.34.1
PATCH v2 16/17 drm/i915: Always check dp_m2_n2 on pre-bdw
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
No point in special casing the check of dp_m2_n2 on pre-bdw platforms. Either the transcoder has M2/N2 in which case the values should be set to something sensible, or it doesn't in which case dp_m2_n2 is always zeroed.
--- drivers/gpu/drm/i915/display/intel_display.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/display/intel_display.c +5 -6
@@ -6478,13 +6478,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,PIPE_CONF_CHECK_I (lane_count);PIPE_CONF_CHECK_X (lane_lat_optim_mask); -if (DISPLAY_VER (dev_priv) <8 ) { -PIPE_CONF_CHECK_M_N (dp_m_n); - -if (current_config->has_drrs) -PIPE_CONF_CHECK_M_N (dp_m2_n2); - }else +if (DISPLAY_VER (dev_priv) >=9 ||IS_BROADWELL (dev_priv)) {PIPE_CONF_CHECK_M_N_ALT (dp_m_n, dp_m2_n2); + }else { +PIPE_CONF_CHECK_M_N (dp_m_n); +PIPE_CONF_CHECK_M_N (dp_m2_n2); + }PIPE_CONF_CHECK_X (output_types);
Signature · 1 line
2.34.1
PATCH v2 17/17 drm/i915: Document BDW+ DRRS M/N programming requirements
In reply to Ville SyrjalaFrom: Ville Syrjälä <[email protected]>
When reprogramming M/N live on BDW+ we must write the LINK_N register last as it's the one that arms the double buffered register update for all the M/N registers. Document this so that we don't accidentally break things.
--- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/gpu/drm/i915/display/intel_display.c +4 -0
@@ -3147,6 +3147,10 @@ void intel_set_m_n(struct drm_i915_private *i915,intel_de_write (i915, data_m_reg,TU_SIZE (m_n->tu) | m_n->data_m);intel_de_write (i915, data_n_reg, m_n->data_n);intel_de_write (i915, link_m_reg, m_n->link_m); +/* +* On BDW+ writing LINK_N arms the double buffered update +* of all the M/N registers, so it must be written last. +*/ intel_de_write (i915, link_n_reg, m_n->link_n); }
Signature · 1 line
2.34.1
Patchwork
CI[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev3)
In reply to Ville Syrjala== Series Details ==
== Series Details ==
Series: drm/i915: M/N cleanup (rev3)
URL : https://patchwork.freedesktop.org/series/99409/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Patchwork
CI[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: M/N cleanup (rev3)
In reply to Ville Syrjala== Series Details ==
== Series Details ==
Series: drm/i915: M/N cleanup (rev3)
URL : https://patchwork.freedesktop.org/series/99409/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11157 -> Patchwork_22136
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22136 absolutely need to be verified manually.
If you think the reported changes have nothing to do with the changes introduced in Patchwork_22136, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/index.html
Participating hosts (43 -> 41)
------------------------------
Missing (2): fi-bsw-cyan fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22136:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11157/fi-kbl-soraka/igt@i915_selftest@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-kbl-soraka/igt@i915_selftest@[email protected]
Known issues
------------
Here are the changes found in Patchwork_22136 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][3] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-skl-6600u/igt@[email protected]
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][4] -> [INCOMPLETE][5] ([i915#3303])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11157/fi-hsw-4770/igt@i915_selftest@[email protected]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-hsw-4770/igt@i915_selftest@[email protected]
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][6] ([i915#1436] / [i915#4312])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-kbl-soraka/igt@[email protected]
- fi-hsw-4770: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / [i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-hsw-4770/igt@[email protected]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][8] ([i915#295]) -> [PASS][9] +12 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11157/fi-cfl-8109u/igt@[email protected]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/fi-cfl-8109u/igt@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
Build changes
-------------
* Linux: CI_DRM_11157 -> Patchwork_22136
CI-20190529: 20190529
CI_DRM_11157: df832f248a682d4eb6a0b649da9e30b340bd718e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6336: ae2eb9e18bc58a4c45f28cfd80962938198dec3c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22136: 400357c683c76a7449f592145dced47de8b76710 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
400357c683c7 drm/i915: Document BDW+ DRRS M/N programming requirements 30075c15511c drm/i915: Always check dp_m2_n2 on pre-bdw25dbb558a992 drm/i915: Dump dp_m2_n2 always358b45363939 drm/i915: Program pch transcoder m2/n2b1b54f14bfc7 drm/i915: Clear DP M2/N2 when not doing DRRSc762f233edbd drm/i915: Fix intel_cpu_transcoder_has_m2_n2()e24e2a4f1cbd drm/i915: Extract can_enable_drrs()0dbe450c1034 drm/i915: Disable DRRS on IVB/HSW port != A526f4a744b5e drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() 03603a62432e drm/i915: Move M/N setup to a more logical place on ddi platforms dadfec6b4a8d drm/i915: Move PCH transcoder M/N setup into the PCH code b24bc557b481 drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() ac12a25cbe51 drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants 869c03688556 drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants cd6fb83cc545 drm/i915: Nuke ilk_get_fdi_m_n_config()486215cbea5c drm/i915: Nuke intel_dp_get_m_n()59bfa1b269e1 drm/i915: Nuke intel_dp_set_m_n()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22136/index.html
Patchwork
CI[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev4)
In reply to Ville Syrjala== Series Details ==
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Patchwork
CI[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: M/N cleanup (rev4)
In reply to Ville Syrjala== Series Details ==
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11158 -> Patchwork_22138
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/index.html
Participating hosts (41 -> 42)
------------------------------
Additional (4): fi-kbl-soraka fi-kbl-8809g bat-adlp-4 fi-pnv-d510
Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22138 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-snb-2600/igt@amdgpu/[email protected]
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@gem_exec_fence@[email protected]
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][3] ([i915#4962]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@gem_exec_suspend@[email protected]
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@[email protected]
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@[email protected]
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@[email protected]
* igt@gem_lmem_swapping@basic:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@[email protected]
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@[email protected]
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@[email protected]
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([i915#3282])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][13] -> [INCOMPLETE][14] ([i915#4785])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-hsw-4770/igt@i915_selftest@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-hsw-4770/igt@i915_selftest@[email protected]
- bat-dg1-6: [PASS][15] -> [DMESG-FAIL][16] ([i915#4494] / [i915#4957])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/bat-dg1-6/igt@i915_selftest@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-dg1-6/igt@i915_selftest@[email protected]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@[email protected]
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@[email protected]
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@[email protected]
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][21] ([fdo#109271]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@[email protected]
- bat-adlp-4: NOTRUN -> [SKIP][22] ([i915#4103]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-4: NOTRUN -> [SKIP][23] ([fdo#109285])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@[email protected]
- fi-kbl-soraka: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#533])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-soraka/igt@[email protected]
- fi-kbl-8809g: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#533])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@[email protected]
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][27] ([fdo#109271]) +54 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: NOTRUN -> [FAIL][28] ([i915#4547])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-4: NOTRUN -> [SKIP][29] ([i915#3291] / [i915#3708]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][30] ([fdo#109271]) +57 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-pnv-d510/igt@[email protected]
- bat-adlp-4: NOTRUN -> [SKIP][31] ([i915#3301] / [i915#3708])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/bat-adlp-4/igt@[email protected]
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][32] ([fdo#109271] / [i915#1436] / [i915#4312])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-hsw-4770/igt@[email protected]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][33] ([i915#4547]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-skl-6600u/igt@gem_exec_suspend@[email protected]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-skl-6600u/igt@gem_exec_suspend@[email protected]
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][35] ([i915#3921]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/fi-snb-2600/igt@i915_selftest@[email protected]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/fi-snb-2600/igt@i915_selftest@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4962]: https://gitlab.freedesktop.org/drm/intel/issues/4962
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11158 -> Patchwork_22138
CI-20190529: 20190529
CI_DRM_11158: e130c3068948a12aacfd1771c59a5294fcab3c56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6336: ae2eb9e18bc58a4c45f28cfd80962938198dec3c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22138: d5af77ca26c97bf3633e51aa97ace3c17e47afe3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d5af77ca26c9 drm/i915: Document BDW+ DRRS M/N programming requirements 62bf4afa563a drm/i915: Always check dp_m2_n2 on pre-bdwadc52ae0eebc drm/i915: Dump dp_m2_n2 always4bba1318f44d drm/i915: Program pch transcoder m2/n237ad5bdcb7d4 drm/i915: Clear DP M2/N2 when not doing DRRSf685a5da6075 drm/i915: Fix intel_cpu_transcoder_has_m2_n2()0bbfe5441dc8 drm/i915: Extract can_enable_drrs()83b28f1b34cd drm/i915: Disable DRRS on IVB/HSW port != A914ac6ae7c94 drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() 44f84510432b drm/i915: Move M/N setup to a more logical place on ddi platforms bc664c33fa94 drm/i915: Move PCH transcoder M/N setup into the PCH code 3f579d008760 drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() 18de5e153b3f drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants 6542a86c9bac drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants 6bf3df4ef5b4 drm/i915: Nuke ilk_get_fdi_m_n_config()2db0c2196593 drm/i915: Nuke intel_dp_get_m_n()e772bf5cf482 drm/i915: Nuke intel_dp_set_m_n()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/index.html
Patchwork
CI[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: M/N cleanup (rev4)
In reply to Ville Syrjala== Series Details ==
== Series Details ==
Series: drm/i915: M/N cleanup (rev4)
URL : https://patchwork.freedesktop.org/series/99409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11158_full -> Patchwork_22138_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_22138_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][1], [FAIL][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk5/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk9/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk4/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk4/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk4/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk2/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk2/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk1/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk1/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk8/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk9/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk8/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk5/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk8/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk8/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#1099])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb2/igt@[email protected]
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][52] -> [FAIL][53] ([i915#2410])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-tglb5/igt@[email protected]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-tglb8/igt@[email protected]
* igt@gem_eio@kms:
- shard-tglb: [PASS][54] -> [FAIL][55] ([i915#232])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-tglb6/igt@[email protected]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-tglb3/igt@[email protected]
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][56] ([i915#4547])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl6/igt@gem_exec_capture@[email protected]
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][57] -> [FAIL][58] ([i915#2842]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl7/igt@gem_exec_fair@[email protected]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-tglb2/igt@gem_exec_fair@[email protected]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-tglb8/igt@gem_exec_fair@[email protected]
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#2842])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk5/igt@gem_exec_fair@[email protected]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk3/igt@gem_exec_fair@[email protected]
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2190])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#2190])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb8/igt@[email protected]
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#4613]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
* igt@gem_lmem_swapping@smem-oom:
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/igt@[email protected]
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271]) +27 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
* igt@gem_userptr_blits@access-control:
- shard-iclb: NOTRUN -> [SKIP][68] ([i915#3297])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@[email protected]
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][69] ([i915#4990])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@[email protected]
- shard-kbl: NOTRUN -> [DMESG-WARN][70] ([i915#4990])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl3/igt@[email protected]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][73] -> [SKIP][74] ([i915#4281])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb1/igt@[email protected]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@[email protected]
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3777]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/igt@[email protected]
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#110723]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@[email protected]
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-snb: NOTRUN -> [SKIP][77] ([fdo#109271]) +75 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb2/igt@[email protected]
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#2705])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb8/igt@[email protected]
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109278] / [i915#3886])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3886])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3886]) +6 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109284] / [fdo#111827]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@[email protected]
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/igt@[email protected]
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +7 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb7/igt@[email protected]
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][88] ([i915#1319])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
- shard-apl: NOTRUN -> [TIMEOUT][89] ([i915#1319])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@[email protected]
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb8/igt@[email protected]
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- shard-skl: [PASS][91] -> [DMESG-WARN][92] ([i915#1982]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl8/igt@[email protected]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl8/igt@[email protected]
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][93] -> [FAIL][94] ([i915#2346])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl6/igt@[email protected]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl9/igt@[email protected]
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][95] -> [FAIL][96] ([i915#79])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl7/igt@kms_flip@[email protected]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl4/igt@kms_flip@[email protected]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271]) +121 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109280]) +5 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][100] -> [DMESG-WARN][101] ([i915#180]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl7/igt@kms_plane@[email protected]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl7/igt@kms_plane@[email protected]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][102] ([fdo#108145] / [i915#265])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl6/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][103] -> [FAIL][104] ([fdo#108145] / [i915#265]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl1/igt@[email protected]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl7/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
* igt@kms_plane_cursor@pipe-d-viewport-size-256:
- shard-glk: NOTRUN -> [SKIP][106] ([fdo#109271]) +39 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk9/igt@[email protected]
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#658])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@[email protected]
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][108] -> [SKIP][109] ([fdo#109441])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][110] -> [FAIL][111] ([i915#31])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk5/igt@[email protected]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk4/igt@[email protected]
* igt@prime_vgem@coherency-gtt:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109292])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb3/igt@[email protected]
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#2994]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@[email protected]
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [TIMEOUT][114] ([i915#3070]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb8/igt@[email protected]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb6/igt@[email protected]
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][116] ([i915#4525]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb3/igt@[email protected]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb2/igt@[email protected]
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [INCOMPLETE][118] ([i915#4547]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl4/igt@gem_exec_capture@[email protected]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl6/igt@gem_exec_capture@[email protected]
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][120] ([i915#2842]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb4/igt@gem_exec_fair@[email protected]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb8/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][122] ([i915#2842]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl7/igt@gem_exec_fair@[email protected]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl7/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][124] ([i915#2849]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb3/igt@gem_exec_fair@[email protected]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb2/igt@gem_exec_fair@[email protected]
* igt@gem_exec_suspend@basic-s3@smem:
- shard-apl: [DMESG-WARN][126] ([i915#180]) -> [PASS][127] +3 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl8/igt@gem_exec_suspend@[email protected]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@gem_exec_suspend@[email protected]
* igt@gem_exec_whisper@basic-normal:
- shard-glk: [DMESG-WARN][128] ([i915#118]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk1/igt@[email protected]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk8/igt@[email protected]
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][130] ([i915#644]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-glk9/igt@[email protected]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-glk5/igt@[email protected]
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][132] ([i915#3921]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-snb4/igt@i915_selftest@[email protected]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb7/igt@i915_selftest@[email protected]
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][134] ([i915#2521]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl6/igt@[email protected]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl9/igt@[email protected]
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][136] ([i915#180]) -> [PASS][137] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl7/igt@[email protected]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl6/igt@[email protected]
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][138] ([i915#2346] / [i915#533]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-kbl: [FAIL][140] ([i915#79]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl7/igt@kms_flip@[email protected]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl4/igt@kms_flip@[email protected]
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1:
- shard-kbl: [FAIL][142] ([i915#2122]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-kbl1/igt@kms_flip@[email protected]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-kbl4/igt@kms_flip@[email protected]
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][144] ([i915#1188]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl1/igt@[email protected]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl7/igt@[email protected]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-snb: [FAIL][146] ([fdo#103375]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-snb5/igt@[email protected]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb2/igt@[email protected]
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][148] ([fdo#109441]) -> [PASS][149] +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][150] ([i915#180] / [i915#295]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl3/igt@[email protected]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
* igt@perf@polling:
- shard-skl: [FAIL][152] ([i915#1542]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl10/igt@[email protected]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl4/igt@[email protected]
* igt@perf_pmu@rc6-suspend:
- shard-snb: [INCOMPLETE][154] -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-snb2/igt@[email protected]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-snb2/igt@[email protected]
* igt@testdisplay:
- shard-skl: [DMESG-WARN][156] ([i915#1982]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-skl10/[email protected]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-skl8/[email protected]
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][158] ([i915#3063] / [i915#3648]) -> [FAIL][159] ([i915#232])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-tglb7/igt@[email protected]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-tglb3/igt@[email protected]
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][160] ([i915#2684]) -> [WARN][161] ([i915#1804] / [i915#2684])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb2/igt@[email protected]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb4/igt@[email protected]
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][162] ([i915#4148]) -> [SKIP][163] ([fdo#109642] / [fdo#111068] / [i915#658])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl3/igt@[email protected]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl2/igt@[email protected]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl3/igt@[email protected]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl8/igt@[email protected]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl3/igt@[email protected]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11158/shard-apl1/igt@[email protected]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl1/igt@[email protected]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl3/igt@[email protected]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl2/igt@[email protected]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl7/igt@[email protected]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl8/igt@[email protected]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/shard-apl7/igt@[email protected]
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fd
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22138/index.html
Quoted 9 lines · Ville Syrjala
From: Ville Syrjälä <[email protected]>
Rehashed version of the M/N cleanup after Jani (rightly) complained about the legibility of some of the patches in the v1 series. These are chunked to a finer pulp, some got revised a bit, and I left out a few of the FDI related things for now. I'll revisit the PCH port/FDI topic later, for now I just slapped in an extra patch to make sure we don't try to use DRRS on PCH ports.
I've commented on one bug that needs fixing, and some nitpicks and future suggestions, but overall the series is
Quoted 32 lines
Ville Syrjälä (17):
drm/i915: Nukeintel_dp_set_m_n()
drm/i915: Nukeintel_dp_get_m_n()
drm/i915: Nukeilk_get_fdi_m_n_config()
drm/i915: Splitintel_cpu_transcoder_set_m_n()into M1/N1 vs. M2/N2
variants
drm/i915: Splitintel_cpu_transcoder_get_m_n()into M1/N1 vs. M2/N2
variants
drm/i915: Pass crtc+cpu_transcoder tointel_cpu_transcoder_set_m_n()drm/i915: Move PCH transcoder M/N setup into the PCH code drm/i915: Move M/N setup to a more logical place on ddi platforms drm/i915: Extract {i9xx,ilk}_configure_cpu_transcoder() drm/i915: Disable DRRS on IVB/HSW port != A
drm/i915: Extractcan_enable_drrs()
drm/i915: Fixintel_cpu_transcoder_has_m2_n2()
drm/i915: Clear DP M2/N2 when not doing DRRS
drm/i915: Program pch transcoder m2/n2
drm/i915: Dumpdp_m2_n2always
drm/i915: Always checkdp_m2_n2on pre-bdw
drm/i915: Document BDW+ DRRS M/N programming requirementsdrivers/gpu/drm/i915/display/g4x_dp.c | 18 +- drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_display.c | 266 ++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 32 ++- .../drm/i915/display/intel_display_types.h | 19 -- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 - drivers/gpu/drm/i915/display/intel_drrs.c | 50 +++- .../gpu/drm/i915/display/intel_pch_display.c | 54 +++- .../gpu/drm/i915/display/intel_pch_display.h | 6 + 9 files changed, 259 insertions(+), 202 deletions(-)
Signature · 1 line
Jani Nikula, Intel Open Source Graphics Center