Add thead,c900-plic support
Subsystems (4)
v7 cover Add thead,c900-plic support
From: Guo Ren <[email protected]>
Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core.
Changes since V7:
- Remove /proc/interrupts display part modification
Changes since V6:
- Modify sifive,plic-1.0.0.yaml comment
- Remove vendor-prefixes patch which has been merged
- Only put dt naming distinguish in sifive-plic.c
Changes since V5:
- Move back to mask/unmask
- Fixup the problem in eoi callback
- Remove allwinner,sun20i-d1 IRQCHIP_DECLARE
- Rewrite comment log
- Add DT list
- Fixup compatible string
- Remove allwinner-d1 compatible
- make dt_binding_check
- Add T-head vendor-prefixes
Changes since V4:
- Update description in errata style
- Update enum suggested by Anup, Heiko, Samuel
- Update comment by Anup
- Add cover-letter
Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
- Add sifive_plic_chip and thead_plic_chip for difference
Changes since V2:
- Add a separate compatible string "thead,c9xx-plic"
- set irq_mask/unmask of "plic_chip" to NULL and point irq_enable/disable of "plic_chip" to plic_irq_mask/unmask
- Add a detailed comment block in plic_init() about the differences in Claim/Completion process of RISC-V PLIC and C9xx PLIC.
Guo Ren (2):
dt-bindings: update riscv plic compatible string irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing
.../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ drivers/irqchip/irq-sifive-plic.c | 1 + 2 files changed, 16 insertions(+), 6 deletions(-)
Signature · 1 line
2.25.1
PATCH v7 1/2 dt-bindings: update riscv plic compatible string
From: Guo Ren <[email protected]>
Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core.
--- .../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +15 -6
@@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow access + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam <[email protected]> - Paul Walmsley <[email protected]>
@@ -42,12 +46,17 @@ maintainers: properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic reg: maxItems: 1
Signature · 1 line
2.25.1
Re: [PATCH V7 1/2] dt-bindings: update riscv plic compatible string
Quoted 12 lines · On Sun, 30 Jan 2022 21:56:33 +0800, [email protected] wrote:
From: Guo Ren <[email protected]>
Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core.
Signed-off-by Guo Ren <[email protected]>Cc Anup Patel <[email protected]>Cc Heiko Stuebner <[email protected]>Cc Rob Herring <[email protected]>Cc Rob Herring <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Samuel Holland <[email protected]>
Quoted 4 lines
--- .../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)
[irqchip: irq/irqchip-fixes] dt-bindings: update riscv plic compatible string
In reply to [email protected]The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
Commit-ID: 321a8be37e1a93cefeae990107533142c8515933 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/321a8be37e1a93cefeae990107533142c8515933 Author: Guo Ren <[email protected]> AuthorDate: Sun, 30 Jan 2022 21:56:33 +08:00 Committer: Marc Zyngier <[email protected]> CommitterDate: Wed, 02 Feb 2022 10:48:50
dt-bindings: update riscv plic compatible string
Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core.
--- Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +15 -6
@@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow access + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam <[email protected]> - Paul Walmsley <[email protected]>
@@ -42,12 +46,17 @@ maintainers: properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic reg: maxItems: 1
PATCH v7 2/2 irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing
In reply to [email protected]From: Guo Ren <[email protected]>
The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi).
Qute opensbi patch commit-msg by Samuel:
The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver.
[1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
--- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+)
drivers/irqchip/irq-sifive-plic.c +1 -0
@@ -398,3 +398,4 @@ static int __init plic_init(struct device_node *node,IRQCHIP_DECLARE (sifive_plic,"sifive,plic-1.0.0" , plic_init);IRQCHIP_DECLARE (riscv_plic0,"riscv,plic0" , plic_init);/* for legacy systems */ +IRQCHIP_DECLARE (thead_c900_plic,"thead,c900-plic" , plic_init);/* for firmware driver */
Signature · 1 line
2.25.1
Re: [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing
Quoted 22 lines · On 1/30/22 7:56 AM, [email protected] wrote:
From: Guo Ren <[email protected]>
The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi).
Qute opensbi patch commit-msg by Samuel:
The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver.
[1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
Signed-off-by Guo Ren <[email protected]>Cc Anup Patel <[email protected]>Cc Marc Zyngier <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Samuel Holland <[email protected]>Cc Thomas Gleixner <[email protected]>
Quoted 3 lines
--- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+)
Re: [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing
Hi Marc,
Quoted 28 lines · Samuel Holland
Quoted 22 lines · On 1/30/22 7:56 AM, [email protected] wrote:
From: Guo Ren <[email protected]>
The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi).
Qute opensbi patch commit-msg by Samuel:
The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver.
[1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
Signed-off-by Guo Ren <[email protected]>Cc Anup Patel <[email protected]>Cc Marc Zyngier <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Samuel Holland <[email protected]>Cc Thomas Gleixner <[email protected]>Quoted 3 lines
--- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+)
Quoted 1 line
Tested-by Samuel Holland <[email protected]>
ping... gently. Any problem with the above patch?
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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[irqchip: irq/irqchip-fixes] irqchip/sifive-plic: Add missing thead,c900-plic match string
In reply to [email protected]The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
Commit-ID: 1d4df649cbb4b26d19bea38ecff4b65b10a1bbca Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/1d4df649cbb4b26d19bea38ecff4b65b10a1bbca Author: Guo Ren <[email protected]> AuthorDate: Sun, 30 Jan 2022 21:56:34 +08:00 Committer: Marc Zyngier <[email protected]> CommitterDate: Wed, 02 Feb 2022 10:49:29
irqchip/sifive-plic: Add missing thead,c900-plic match string
The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi).
Qute opensbi patch commit-msg by Samuel:
The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver.
[1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
--- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+)
drivers/irqchip/irq-sifive-plic.c +1 -0
@@ -398,3 +398,4 @@ out_free_priv:IRQCHIP_DECLARE (sifive_plic,"sifive,plic-1.0.0" , plic_init);IRQCHIP_DECLARE (riscv_plic0,"riscv,plic0" , plic_init);/* for legacy systems */ +IRQCHIP_DECLARE (thead_c900_plic,"thead,c900-plic" , plic_init);/* for firmware driver */