Renesas 8T49N241 device driver

drivers/clk/8t49n24x-core.c new file +66 -0

new file mode 100644
index 000000000000..df6b4f6392b5
@@ -0,0 +1,752 @@
+// SPDX-License-Identifier: GPL-2.0
+/* 8t49n24x-core.c - Program 8T49N24x settings via I2C (common code)
+ *
+ * Copyright (C) 2018, Renesas Electronics America <[email protected]>
+ */
+
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+
+#include "8t49n24x-core.h"
+
+/*
+ * In Timing Commander, Q0 is changed from 25MHz to Q0 75MHz, the following
+ * changes occur:
+ *
+ * 2 bytes change in EEPROM data string.
+ *
+ * DSM_INT R0025[0],R0026[7:0] : 35 => 30
+ * NS2_Q0 R0040[7:0],R0041[7:0] : 14 => 4
+ *
+ * In EEPROM
+ * 1. R0026
+ * 2. R0041
+ *
+ * Note that VCO_Frequency (metadata) also changed (3500 =>3000).
+ * This reflects a change to DSM_INT.
+ *
+ * Note that the Timing Commander code has workarounds in the workflow scripts
+ * to handle dividers for the 8T49N241 (because the development of that GUI
+ * predates chip override functionality). That affects NS1_Qx (x in 1-3)
+ * and NS2_Qx. NS1_Qx contains the upper bits of NS_Qx, and NS2_Qx contains
+ * the lower bits. That is NOT the case for Q0, though. In that case NS1_Q0
+ * is the 1st stage output divider (/5, /6, /4) and NS2_Q0 is the 16-bit
+ * second stage (with actual divide being twice the value stored in the
+ * register).
+ *
+ * NS1_Q0 R003F[1:0]
+ */
+
+#define R8T49N24X_VCO_MIN                      2999997000u
+#define R8T49N24X_VCO_MAX                      4000004000u
+#define R8T49N24X_VCO_OPT                      3500000000u
+#define R8T49N24X_MIN_INT_DIVIDER      6
+#define R8T49N24X_MIN_NS1                      4
+#define R8T49N24X_MAX_NS1                      6
+
+static const u8 q0_ns1_options[3] = { 5, 6, 4 };
+
+/**
+ * __renesas_bits_to_shift - num bits to shift given specified mask
+ * @mask:      32-bit word input to count zero bits on right
+ *
+ * Given a bit mask indicating where a value will be stored in
+ * a register, return the number of bits you need to shift the value
+ * before ORing it into the register value.
+ *
+ * Return: number of bits to shift
+ */
+int __renesas_bits_to_shift(unsigned int mask)
+{
+       if (mask)
+               return __ffs(mask);
+       else
+               return 0;
+}
+

drivers/clk/8t49n24x-core.c new file +17 -0

+               reg, reg >> 8, reg & 0xFF);
+
+       print_hex_dump_debug("i2c_write_bulk: ", DUMP_PREFIX_NONE,
+                            16, 1, val, val_count, false);
+
+       for (i = 0; i < val_count; i++) {
+               block[currentOffset++] = val[i];
+
+               if (i > 0 && (i + 1) % WRITE_BLOCK_SIZE == 0) {
+                       err = regmap_bulk_write(map, block_offset, block, WRITE_BLOCK_SIZE);
+                       if (err)
+                               break;
+                       block_offset += WRITE_BLOCK_SIZE;
+                       currentOffset = 0;
+               }
+       }
+

drivers/clk/8t49n24x-core.c new file +130 -0

+
+       switch (output_num) {
+       case 0:
+               offsets->oe_offset = R8T49N24X_REG_OUTEN;
+               offsets->oe_mask = R8T49N24X_REG_OUTEN0_MASK;
+               offsets->dis_mask = R8T49N24X_REG_Q0_DIS_MASK;
+               break;
+       case 1:
+               offsets->oe_offset = R8T49N24X_REG_OUTEN;
+               offsets->oe_mask = R8T49N24X_REG_OUTEN1_MASK;
+               offsets->dis_mask = R8T49N24X_REG_Q1_DIS_MASK;
+               offsets->n_17_16_offset = R8T49N24X_REG_N_Q1_17_16;
+               offsets->n_17_16_mask = R8T49N24X_REG_N_Q1_17_16_MASK;
+               offsets->n_15_8_offset = R8T49N24X_REG_N_Q1_15_8;
+               offsets->n_7_0_offset = R8T49N24X_REG_N_Q1_7_0;
+               offsets->nfrac_27_24_offset = R8T49N24X_REG_NFRAC_Q1_27_24;
+               offsets->nfrac_27_24_mask = R8T49N24X_REG_NFRAC_Q1_27_24_MASK;
+               offsets->nfrac_23_16_offset = R8T49N24X_REG_NFRAC_Q1_23_16;
+               offsets->nfrac_15_8_offset = R8T49N24X_REG_NFRAC_Q1_15_8;
+               offsets->nfrac_7_0_offset = R8T49N24X_REG_NFRAC_Q1_7_0;
+               break;
+       case 2:
+               offsets->oe_offset = R8T49N24X_REG_OUTEN;
+               offsets->oe_mask = R8T49N24X_REG_OUTEN2_MASK;
+               offsets->dis_mask = R8T49N24X_REG_Q2_DIS_MASK;
+               offsets->n_17_16_offset = R8T49N24X_REG_N_Q2_17_16;
+               offsets->n_17_16_mask = R8T49N24X_REG_N_Q2_17_16_MASK;
+               offsets->n_15_8_offset = R8T49N24X_REG_N_Q2_15_8;
+               offsets->n_7_0_offset = R8T49N24X_REG_N_Q2_7_0;
+               offsets->nfrac_27_24_offset = R8T49N24X_REG_NFRAC_Q2_27_24;
+               offsets->nfrac_27_24_mask = R8T49N24X_REG_NFRAC_Q2_27_24_MASK;
+               offsets->nfrac_23_16_offset = R8T49N24X_REG_NFRAC_Q2_23_16;
+               offsets->nfrac_15_8_offset = R8T49N24X_REG_NFRAC_Q2_15_8;
+               offsets->nfrac_7_0_offset = R8T49N24X_REG_NFRAC_Q2_7_0;
+               break;
+       case 3:
+               offsets->oe_offset = R8T49N24X_REG_OUTEN;
+               offsets->oe_mask = R8T49N24X_REG_OUTEN3_MASK;
+               offsets->dis_mask = R8T49N24X_REG_Q3_DIS_MASK;
+               offsets->n_17_16_offset = R8T49N24X_REG_N_Q3_17_16;
+               offsets->n_17_16_mask = R8T49N24X_REG_N_Q3_17_16_MASK;
+               offsets->n_15_8_offset = R8T49N24X_REG_N_Q3_15_8;
+               offsets->n_7_0_offset = R8T49N24X_REG_N_Q3_7_0;
+               offsets->nfrac_27_24_offset = R8T49N24X_REG_NFRAC_Q3_27_24;
+               offsets->nfrac_27_24_mask = R8T49N24X_REG_NFRAC_Q3_27_24_MASK;
+               offsets->nfrac_23_16_offset = R8T49N24X_REG_NFRAC_Q3_23_16;
+               offsets->nfrac_15_8_offset = R8T49N24X_REG_NFRAC_Q3_15_8;
+               offsets->nfrac_7_0_offset = R8T49N24X_REG_NFRAC_Q3_7_0;
+               break;
+       }
+}
+
+/**
+ * r8t49n24x_calc_div_q0 - Calculate dividers and VCO freq to generate
+ *             the specified Q0 frequency.
+ * @chip:      Device data structure. contains all requested frequencies
+ *             for all outputs.
+ *
+ * The actual output divider is ns1 * ns2 * 2. fOutput = fVCO / (ns1 * ns2 * 2)
+ *
+ * The options for ns1 (when the source is the VCO) are 4,5,6. ns2 is a
+ * 16-bit value.
+ *
+ * chip->divs: structure for specifying ns1/ns2 values. If 0 after this
+ * function, Q0 is not requested
+ */
+static void r8t49n24x_calc_div_q0(struct clk_r8t49n24x_chip *chip)
+{
+       unsigned int i;
+       unsigned int min_div = 0, max_div = 0, best_vco = 0;
+       unsigned int min_ns2 = 0, max_ns2 = 0;
+       bool is_lower_vco = false;
+
+       chip->divs.ns1_q0 = 0;
+       chip->divs.ns2_q0 = 0;
+
+       if (chip->clk[0].requested == 0)
+               return;
+
+       min_div = (R8T49N24X_VCO_MIN / 2 / chip->clk[0].requested * 2) * 2;
+       max_div = (R8T49N24X_VCO_MAX / 2 / chip->clk[0].requested * 2) * 2;
+
+       dev_dbg(&chip->i2c_client->dev,
+               "requested: %lu, min_div: %u, max_div: %u",
+               chip->clk[0].requested, min_div, max_div);
+
+       min_ns2 = min_div / (R8T49N24X_MAX_NS1 * 2);
+       max_ns2 = max_div / (R8T49N24X_MIN_NS1 * 2);
+
+       dev_dbg(&chip->i2c_client->dev, "min_ns2: %u, max_ns2: %u", min_ns2, max_ns2);
+
+       for (i = 0; i < ARRAY_SIZE(q0_ns1_options); i++) {
+               unsigned int j = min_ns2;
+
+               while (j <= max_ns2) {
+                       unsigned int actual_div = q0_ns1_options[i] * j * 2;
+                       unsigned int current_vco = actual_div * chip->clk[0].requested;
+
+                       if (current_vco < R8T49N24X_VCO_MIN)
+                               dev_dbg(&chip->i2c_client->dev,
+                                       "ignore div: (ns1=%u * ns2=%u * 2 * %lu) == %u < %u",
+                                       q0_ns1_options[i], j,
+                                       chip->clk[0].requested, current_vco,
+                                       R8T49N24X_VCO_MIN);
+                       else if (current_vco > R8T49N24X_VCO_MAX) {
+                               dev_dbg(&chip->i2c_client->dev,
+                                       "ignore div: (ns1=%u * ns2=%u * 2 * %lu) == %u > %u. EXIT LOOP.",
+                                       q0_ns1_options[i], j,
+                                       chip->clk[0].requested, current_vco,
+                                       R8T49N24X_VCO_MAX);
+                               j = max_ns2;
+                       } else {
+                               bool use = false;
+
+                               dev_dbg(&chip->i2c_client->dev,
+                                       "contender: (ns1=%u * ns2=%u * 2 * %lu) == %u [in range]",
+                                       q0_ns1_options[i], j,
+                                       chip->clk[0].requested, current_vco);
+                               if (current_vco <= R8T49N24X_VCO_OPT) {
+                                       if (current_vco > best_vco || !is_lower_vco) {
+                                               is_lower_vco = true;
+                                               use = true;
+                                       }
+                               } else if (!is_lower_vco && current_vco > best_vco) {
+                                       use = true;
+                               }
+                               if (use) {
+                                       chip->divs.ns1_q0 = i;
+                                       chip->divs.ns2_q0 = j;
+                                       best_vco = current_vco;

drivers/clk/8t49n24x-core.c new file +134 -0

+ * @chip:      Device data structure. contains all requested frequencies
+ *             for all outputs.
+ *
+ * Calculate the clock dividers (dsmint, dsmfrac for vco; ns1/ns2 for q0,
+ * n/nfrac for q1-3) for a given target frequency.
+ *
+ * Return: 0 on success, negative errno otherwise.
+ */
+static int r8t49n24x_calc_divs(struct clk_r8t49n24x_chip *chip)
+{
+       unsigned int i;
+       unsigned int vco = 0;
+       unsigned int pfd = 0;
+       unsigned long rem = 0;
+
+       r8t49n24x_calc_div_q0(chip);
+
+       dev_dbg(&chip->i2c_client->dev,
+               "after r8t49n24x_calc_div_q0. ns1: %u [/%u], ns2: %u",
+               chip->divs.ns1_q0, q0_ns1_options[chip->divs.ns1_q0],
+               chip->divs.ns2_q0);
+
+       chip->divs.dsmint = 0;
+       chip->divs.dsmfrac = 0;
+
+       if (chip->clk[0].requested > 0) {
+               /* Q0 is in use and is governing the actual VCO freq */
+               vco = q0_ns1_options[chip->divs.ns1_q0] * chip->divs.ns2_q0
+                       * 2 * chip->clk[0].requested;
+       } else {
+               unsigned int freq = 0;
+               unsigned int min_div = 0, max_div = 0;
+               unsigned int i = 0;
+               bool is_lower_vco = false;
+
+               /*
+                * Q0 is not in use. Use the first requested (fractional)
+                * output frequency as the one controlling the VCO.
+                */
+               for (i = 1; i < NUM_OUTPUTS; i++) {
+                       if (chip->clk[i].requested != 0) {
+                               freq = chip->clk[i].requested;
+                               break;
+                       }
+               }
+
+               if (!freq) {
+                       dev_err(&chip->i2c_client->dev, "NO FREQUENCIES SPECIFIED");
+                       return -EINVAL;
+               }
+
+               /*
+                * First, determine the min/max div for the output frequency.
+                */
+               min_div = R8T49N24X_MIN_INT_DIVIDER;
+               max_div = (R8T49N24X_VCO_MAX / 2 / freq) * 2;
+
+               dev_dbg(&chip->i2c_client->dev,
+                       "calc_divs for fractional output. freq: %u, min_div: %u, max_div: %u",
+                       freq, min_div, max_div);
+
+               i = min_div;
+
+               while (i <= max_div) {
+                       unsigned int current_vco = freq * i;
+
+                       dev_dbg(&chip->i2c_client->dev,
+                               "calc_divs for fractional output. walk: %u, freq: %u, vco: %u",
+                               i, freq, vco);
+
+                       if (current_vco >= R8T49N24X_VCO_MIN &&
+                           vco <= R8T49N24X_VCO_MAX) {
+                               if (current_vco <= R8T49N24X_VCO_OPT) {
+                                       if (current_vco > vco || !is_lower_vco) {
+                                               is_lower_vco = true;
+                                               vco = current_vco;
+                                       }
+                               } else if (!is_lower_vco && current_vco > vco) {
+                                       vco = current_vco;
+                               }
+                       }
+                       /* Divider must be even. */
+                       i += 2;
+               }
+       }
+
+       if (!vco) {
+               dev_err(&chip->i2c_client->dev, "no integer divider in range found. NOT SUPPORTED.");
+               return -EINVAL;
+       }
+
+       /* Setup dividers for outputs with fractional dividers. */
+       for (i = 1; i < NUM_OUTPUTS; i++) {
+               if (chip->clk[i].requested) {
+                       /*
+                        * The value written to the chip is half
+                        * the calculated divider.
+                        */
+                       rem = vco % (chip->clk[i].requested * 2);
+                       chip->divs.nint[i - 1] = vco / chip->clk[i].requested * 2;
+                       chip->divs.nfrac[i - 1] = div64_ul(rem << 28,
+                                                          chip->clk[i].requested * 2);
+
+                       dev_dbg(&chip->i2c_client->dev,
+                               "div to get Q%i freq %lu from vco %u: int part: %u, rem: %lu, frac part: %u",
+                               i, chip->clk[i].requested,
+                               vco, chip->divs.nint[i - 1], rem,
+                               chip->divs.nfrac[i - 1]);
+               }
+       }
+
+       /* Calculate freq for pfd */
+       pfd = chip->input_clk_freq * (chip->doubler_disabled ? 1 : 2);
+
+       /*
+        * Calculate dsmint & dsmfrac:
+        * -----------------------------
+        * dsm = float(vco)/float(pfd)
+        * dsmfrac = dsm-floor(dsm) * 2^21
+        * rem = vco % pfd
+        * therefore:
+        * dsmfrac = (rem * 2^21)/pfd
+        */
+       rem = vco % pfd;
+       chip->divs.dsmint = vco / pfd;
+       chip->divs.dsmfrac = div64_ul(rem << 21, pfd);
+
+       dev_dbg(&chip->i2c_client->dev,
+               "vco: %u, pfd: %u, dsmint: %u, dsmfrac: %u, rem: %lu",
+               vco, pfd, chip->divs.dsmint,
+               chip->divs.dsmfrac, rem);
+
+       return 0;
+}

drivers/clk/8t49n24x-core.c new file +54 -0

+{
+       int err;
+       struct clk_register_offsets offsets;
+       struct i2c_client *client = chip->i2c_client;
+
+       /*
+        * When an output is enabled, enable it in the original
+        * data read from the chip and cached. Otherwise it may be
+        * accidentally turned off when another output is enabled.
+        *
+        * E.g., the driver starts with all outputs off in reg_out_en_x.
+        * Q1 is enabled with the appropriate mask. Q2 is then enabled,
+        * which results in Q1 being turned back off (because Q1 was off
+        * in reg_out_en_x).
+        */
+
+       r8t49n24x_get_offsets(output, &offsets);
+
+       dev_dbg(&client->dev,
+               "q%u enable? %d. reg_out_en_x before: 0x%x, reg_out_mode_0_1 before: 0x%x",
+               output, enable, chip->reg_out_en_x, chip->reg_out_mode_0_1);
+
+       dev_dbg(&client->dev, "reg_out_mode_2_3 before: 0x%x, reg_qx_dis before: 0x%x",
+               chip->reg_out_mode_2_3, chip->reg_qx_dis);
+
+       chip->reg_out_en_x = chip->reg_out_en_x & ~offsets.oe_mask;
+       if (enable)
+               chip->reg_out_en_x |= BIT(__renesas_bits_to_shift(offsets.oe_mask));
+
+       chip->reg_qx_dis = chip->reg_qx_dis & ~offsets.dis_mask;
+       dev_dbg(&client->dev,
+               "q%u enable? %d. reg_qx_dis mask: 0x%x, before checking enable: 0x%x",
+               output, enable, offsets.dis_mask, chip->reg_qx_dis);
+
+       if (!enable)
+               chip->reg_qx_dis |= BIT(__renesas_bits_to_shift(offsets.dis_mask));
+
+       dev_dbg(&client->dev,
+               "q%u enable? %d. reg_out_en_x after: 0x%x, reg_qx_dis after: 0x%x",
+               output, enable, chip->reg_out_en_x, chip->reg_qx_dis);
+
+       err = __i2c_write(client, chip->regmap, R8T49N24X_REG_OUTEN, chip->reg_out_en_x);
+       if (err) {
+               dev_err(&client->dev, "error setting %s: %i", "R8T49N24X_REG_OUTEN", err);
+               return err;
+       }
+
+       err = __i2c_write(client, chip->regmap, R8T49N24X_REG_OUTMODE0_1, chip->reg_out_mode_0_1);
+       if (err) {
+               dev_err(&client->dev, "error setting %s: %i", "R8T49N24X_REG_OUTMODE0_1", err);
+               return err;
+       }
+
+       err = __i2c_write(client, chip->regmap, R8T49N24X_REG_OUTMODE2_3, chip->reg_out_mode_2_3);

drivers/clk/8t49n24x-core.c new file +27 -0

+
+       return 0;
+}
+
+/**
+ * r8t49n24x_update_device - write registers to the chip
+ * @chip:      Device data structure
+ *
+ * Write all values to hardware that we        have calculated.
+ *
+ * Return: passes on regmap_bulk_write return value.
+ */
+static int r8t49n24x_update_device(struct clk_r8t49n24x_chip *chip)
+{
+       int err;
+       unsigned int i;
+       struct i2c_client *client = chip->i2c_client;
+
+       dev_dbg(&client->dev, "setting DSM_INT_8 (val %u @ %u)",
+               chip->divs.dsmint >> 8, R8T49N24X_REG_DSM_INT_8);
+
+       err = __i2c_write_with_mask(client, chip->regmap, R8T49N24X_REG_DSM_INT_8,
+                                   (chip->divs.dsmint >> 8) & R8T49N24X_REG_DSM_INT_8_MASK,
+                                   chip->reg_dsm_int_8, R8T49N24X_REG_DSM_INT_8_MASK);
+       if (err) {
+               dev_err(&client->dev, "error setting R8T49N24X_REG_DSM_INT_8: %i", err);
+               return err;

drivers/clk/8t49n24x-core.h new file +13 -0

new file mode 100644
index 000000000000..93621fbdbe6b
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * 8t49n24x-core.h - Program 8T49N24x settings via I2C (common code)
+ *
+ * Copyright (C) 2018, Renesas Electronics America <[email protected]>
+ */
+
+#ifndef __8T49N24X_CORE_H_
+#define __8T49N24X_CORE_H_
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+

drivers/clk/8t49n24x-core.h new file +16 -0

+
+/**
+ * r8t49n24x_clk_notifier_cb - Clock rate change callback
+ * @nb:                Pointer to notifier block
+ * @event:     Notification reason
+ * @data:      Pointer to notification data object
+ *
+ * This function is called when the input clock frequency changes.
+ * The callback checks whether a valid bus frequency can be generated after the
+ * change. If so, the change is acknowledged, otherwise the change is aborted.
+ * New dividers are written to the HW in the pre- or post change notification
+ * depending on the scaling direction.
+ *
+ * Return:     NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
+ *             to acknowledge the change, NOTIFY_DONE if the notification is
+ *             considered irrelevant.

+ case POST_RATE_CHANGE:

drivers/clk/8t49n24x-core.h new file +28 -0

+               if (err)
+                       dev_dbg(&chip->i2c_client->dev, "error setting frequency (%i)\n", err);
+               return NOTIFY_OK;
+       case ABORT_RATE_CHANGE:
+               return NOTIFY_OK;
+       default:
+               return NOTIFY_DONE;
+       }
+}
+
+static struct clk_hw *of_clk_r8t49n24x_get(struct of_phandle_args *clkspec,
+                                          void *_data)
+{
+       struct clk_r8t49n24x_chip *chip = _data;
+       unsigned int idx = clkspec->args[0];
+
+       if (idx >= ARRAY_SIZE(chip->clk)) {
+               pr_err("invalid clock index %u for provider %pOF\n", idx, clkspec->np);
+               return ERR_PTR(-EINVAL);
+       }
+
+       return &chip->clk[idx].hw;
+}
+
+/**
+ * r8t49n24x_probe - main entry point for ccf driver
+ * @client:    pointer to i2c_client structure
+ * @id:                pointer to i2c_device_id structure

drivers/clk/8t49n24x-core.h new file +61 -0

+       chip->i2c_client = client;
+
+       chip->min_freq = R8T49N24X_MIN_FREQ;
+       chip->max_freq = R8T49N24X_MAX_FREQ;
+
+       for (i = 0; i <= NUM_INPUTS; i++) {
+               char name[12];
+
+               sprintf(name, i == NUM_INPUTS ? "xtal" : "clk%i", i);
+               dev_dbg(&client->dev, "attempting to get %s", name);
+               chip->input_clk = devm_clk_get_optional(&client->dev, name);
+               if (chip->input_clk) {
+                       err = 0;
+                       chip->input_clk_num = i;
+                       break;
+               }
+       }
+
+       if (IS_ERR(chip->input_clk)) {
+               return dev_err_probe(&client->dev, PTR_ERR(chip->input_clk),
+                                    "can't get input clock/xtal\n");
+       }
+
+       chip->input_clk_freq = clk_get_rate(chip->input_clk);
+       dev_dbg(&client->dev, "Frequency from clk in device tree: %uHz", chip->input_clk_freq);
+
+       chip->input_clk_nb.notifier_call = r8t49n24x_clk_notifier_cb;
+       if (clk_notifier_register(chip->input_clk, &chip->input_clk_nb))
+               dev_warn(&client->dev, "Unable to register clock notifier for input_clk.");
+
+       dev_dbg(&client->dev, "about to read settings: %zu", ARRAY_SIZE(chip->settings));
+
+       err = of_property_read_u8_array(client->dev.of_node, "renesas,settings", chip->settings,
+                                       ARRAY_SIZE(chip->settings));
+       if (!err) {
+               dev_dbg(&client->dev, "settings property specified in DT");
+               chip->has_settings = true;
+       } else if (err == -EOVERFLOW) {
+               dev_dbg(&client->dev, "EOVERFLOW reading settings. ARRAY_SIZE: %zu",
+                       ARRAY_SIZE(chip->settings));
+                       return err;
+       } else {
+               dev_dbg(&client->dev,
+                       "settings property missing in DT (or an error that can be ignored: %i).",
+                       err);
+       }
+
+       /*
+        * Requested output frequencies cannot be specified in the DT.
+        * Either a consumer needs to use the clock API to request the rate.
+        * Use clock-names in DT to specify the output clock.
+        */
+
+       chip->regmap = devm_regmap_init_i2c(client, &r8t49n24x_regmap_config);
+       if (IS_ERR(chip->regmap)) {
+               dev_err(&client->dev, "failed to allocate register map\n");
+               return PTR_ERR(chip->regmap);
+       }
+
+       dev_dbg(&client->dev, "call i2c_set_clientdata");
+       i2c_set_clientdata(client, chip);

drivers/clk/8t49n24x-core.h new file +7 -0

+       err = r8t49n24x_read_from_hw(chip);
+       if (err)
+               return err;
+
+       /* Create all 4 clocks */
+       for (i = 0; i < NUM_OUTPUTS; i++) {
+               init.name = kasprintf(GFP_KERNEL, "%s.Q%i", client->dev.of_node->name, i);