memory: tegra: Add MC channels and error logging
v6 cover memory: tegra: Add MC channels and error logging
From tegra186 onward, memory controllers support multiple channels. Add memory controller channels in device tree and add support to map address spaces of these channels in tegra MC driver.
When memory controller interrupt occurs, registers from these channels are required to be read in order to get error information. Add error logging support from tegra186 onward for memory controller interrupts.
Ashish Mhetre (4):
memory: tegra: Add memory controller channels support
memory: tegra: Add MC error logging on tegra186 onward
dt-bindings: memory: Update reg maxitems for tegra186
arm64: tegra: Add memory controller channels
---
Changes in v6:
- Added reg-names for each reg item of memory controller node
- Added logging for interrupts on multiple memory controller channels
- Added clearing interrupt support for global intstatus
- Updated DT binding documentation to work with existing DTS as well
- Updated function to get MC channels
- Updated variable names
Changes in v5:
- Updated patch sequence such that driver patches are before DT patches
- Fixed DT ABI break from v4
- Fixed smatch bug
- Updated description in DT binding documentation
- Updated variable names
Changes in v4:
- Added memory controller channels support
- Added newlines after every break statement of all switch cases
- Fixed compile error with W=1 build
- Fixed the interrupt mask bit logic
Changes in v3:
- Removed unnecessary ifdefs
- Grouped newly added MC registers with existing MC registers
- Removed unnecessary initialization of variables
- Updated code to use newly added field 'has_addr_hi_reg' instead of ifdefs
Changes in v2:
- Updated patch subject and commit message
- Removed separate irq handlers
- Updated tegra30_mc_handle_irq to be used for tegra186 onwards as well
.../nvidia,tegra186-mc.yaml | 14 +- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 21 ++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 21 ++- drivers/memory/tegra/mc.c | 120 +++++++++++++++--- drivers/memory/tegra/mc.h | 37 +++++- drivers/memory/tegra/tegra186.c | 98 ++++++++++++++ drivers/memory/tegra/tegra194.c | 45 +++++++ drivers/memory/tegra/tegra234.c | 64 ++++++++++ include/soc/tegra/mc.h | 12 ++ 10 files changed, 412 insertions(+), 27 deletions(-)
Signature · 1 line
2.17.1
PATCH v6 1/4 memory: tegra: Add memory controller channels support
From tegra186 onwards, memory controller support multiple channels. Add support for mapping address spaces of these channels. Make sure that number of channels are as expected on each SOC. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info.
--- drivers/memory/tegra/mc.c | 6 ++++ drivers/memory/tegra/tegra186.c | 54 +++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 7 +++++ 5 files changed, 69 insertions(+)
drivers/memory/tegra/mc.c +6 -0
@@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev)if (IS_ERR (mc->regs))return PTR_ERR (mc->regs); +if (mc->soc->ops && mc->soc->ops->map_regs) { + err = mc->soc->ops->map_regs (mc, pdev); +if (err <0 ) +return err; + } + mc->debugfs.root =debugfs_create_dir ("mc" ,NULL );if (mc->soc->ops && mc->soc->ops->probe) {
drivers/memory/tegra/tegra186.c +54 -0
71 lines not on this page · raw message
drivers/memory/tegra/tegra194.c +1 -0
@@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, };
drivers/memory/tegra/tegra234.c +1 -0
@@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, };
include/soc/tegra/mc.h +7 -0
@@ -13,6 +13,9 @@#include <linux/irq.h> #include <linux/reset-controller.h> #include <linux/types.h> +#include <linux/platform_device.h> + +#define MC_MAX_CHANNELS 16struct clk ;struct device ;
@@ -181,6 +184,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc,struct platform_device *pdev); };struct tegra_mc_soc {
@@ -194,6 +198,7 @@ struct tegra_mc_soc {unsigned int atom_size;u8 client_id_mask; +u8 num_channels;const struct tegra_smmu_soc *smmu;
@@ -212,6 +217,8 @@ struct tegra_mc {struct tegra_smmu *smmu;struct gart_device *gart;void __iomem *regs; +void __iomem *bcast_ch_regs; +void __iomem *ch_regs[MC_MAX_CHANNELS ];struct clk *clk;int irq;
Signature · 1 line
2.17.1
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 5 lines
drivers/memory/tegra/tegra186.c +5
-0+ num_dt_channels =of_property_count_elems_of_size (pdev->dev.of_node,"reg" , + reg_cells *sizeof (u32)); +/* +* On tegra186 onwards, memory controller support multiple channels. +* Apart from regular memory controller channels, there is one broadcast
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 180
Quoted 10 lines
drivers/memory/tegra/tegra186.c +10
-0+* channel and one for stream-id registers. +*/ +if (num_dt_channels < mc->soc->num_channels +2 ) { +dev_warn (&pdev->dev,"MC channels are missing, please update memory controller DT node with MC channels\n" ); +return 0 ; + } + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"mc-broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) +return PTR_ERR (mc->bcast_ch_regs);
Looks to me that you don't need to use of_property_count_elems_of_size() and could only check the "mc-broadcast" presence to decide whether this is an older DT.
mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
if (IS_ERR(mc->bcast_ch_regs)) {
dev_warn(&pdev->dev, "Broadcast channel is missing, please update your
device-tree\n");
return PTR_ERR(mc->bcast_ch_regs);
}Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 20 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 5 lines
drivers/memory/tegra/tegra186.c +5
-0+ num_dt_channels =of_property_count_elems_of_size (pdev->dev.of_node,"reg" , + reg_cells *sizeof (u32)); +/* +* On tegra186 onwards, memory controller support multiple channels. +* Apart from regular memory controller channels, there is one broadcast drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 180
Quoted 10 lines
drivers/memory/tegra/tegra186.c +10
-0+* channel and one for stream-id registers. +*/ +if (num_dt_channels < mc->soc->num_channels +2 ) { +dev_warn (&pdev->dev,"MC channels are missing, please update memory controller DT node with MC channels\n" ); +return 0 ; + } + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"mc-broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) +return PTR_ERR (mc->bcast_ch_regs);
Quoted 4 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()and could only check the "mc-broadcast" presence to decide whether this is an older DT.
Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 7 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");if (IS_ERR(mc->bcast_ch_regs)) { dev_warn(&pdev->dev, "Broadcast channel is missing, please update your device-tree\n"); return PTR_ERR(mc->bcast_ch_regs); }
return 0;
to avoid DT ABI break, right?
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 45 lines · Ashish Mhetre
Quoted 26 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 13 lines
+
num_dt_channels= of_property_count_elems_of_size(pdev->dev.of_node, "reg", +reg_cells* sizeof(u32));
+ /*
+ * On tegra186 onwards, memory controller support multiple channels.
+ * Apart from regular memory controller channels, there is one broadcast
+ * channel and one for stream-id registers.
+ */
+ if (num_dt_channels<mc->soc->num_channels+ 2) { + dev_warn(&pdev->dev, "MC channels are missing, pleaseQuoted 8 lines
update memory controller DT node with MC channels\n");
+ return 0;
+ }
+
+mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "mc-broadcast");
+ if (IS_ERR(mc->bcast_ch_regs))
+ returnPTR_ERR(mc->bcast_ch_regs);Quoted 4 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()and could only check the "mc-broadcast" presence to decide whether this is an older DT.Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 8 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");
if (IS_ERR(mc->bcast_ch_regs)) {
dev_warn(&pdev->dev, "Broadcast channel is missing, please update your
device-tree\n");
returnPTR_ERR(mc->bcast_ch_regs);
}
Quoted 3 lines
return 0;
to avoid DT ABI break, right?
Yes, it should be "return 0".
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 49 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 45 lines · Ashish Mhetre
Quoted 26 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 19 lines
+
num_dt_channels=
of_property_count_elems_of_size(pdev->dev.of_node, "reg",
+reg_cells*
sizeof(u32));(quoted diff) +2
-0+ /* + * On tegra186 onwards, memory controller support multiplechannels.
+ * Apart from regular memory controller channels, there is one
broadcastdrivers/memory/tegra/tegra186.c +4
-0+* channel and one for stream-id registers. +*/ +if (num_dt_channels < mc->soc->num_channels +2 ) { + dev_warn(&pdev->dev, "MC channels are missing, pleaseupdate memory controller DT node with MC channels\n");
drivers/memory/tegra/tegra186.c +4
-0+return 0 ; + } + + mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev,"mc-broadcast");
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 180
Quoted 2 lines
drivers/memory/tegra/tegra186.c +2
-0+if (IS_ERR (mc->bcast_ch_regs)) +return PTR_ERR (mc->bcast_ch_regs);Quoted 4 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()and could only check the "mc-broadcast" presence to decide whether this is an older DT.Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 8 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");if (IS_ERR(mc->bcast_ch_regs)) { dev_warn(&pdev->dev, "Broadcast channel is missing, please update your device-tree\n"); return PTR_ERR(mc->bcast_ch_regs); }
Quoted 5 lines
Quoted 3 lines
return 0;
to avoid DT ABI break, right?
Yes, it should be "return 0".
But if we "return 0" from here, then what about the case when ioremap() actually fails with new DT i.e. when broadcast reg is present in DT? In that case error should be returned and probe should be failed, right?
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 55 lines · Ashish Mhetre
Quoted 52 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 48 lines · Ashish Mhetre
Quoted 26 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 13 lines
+
num_dt_channels= of_property_count_elems_of_size(pdev->dev.of_node, "reg", +reg_cells* sizeof(u32));
+ /*
+ * On tegra186 onwards, memory controller support multiple channels.
+ * Apart from regular memory controller channels, there is one broadcast
+ * channel and one for stream-id registers.
+ */
+ if (num_dt_channels<mc->soc->num_channels+ 2) { + dev_warn(&pdev->dev, "MC channels are missing, pleaseQuoted 8 lines
update memory controller DT node with MC channels\n");
+ return 0;
+ }
+
+mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "mc-broadcast");
+ if (IS_ERR(mc->bcast_ch_regs))
+ returnPTR_ERR(mc->bcast_ch_regs);Quoted 5 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()
and could only check the "mc-broadcast" presence to decide whether this is an older DT.Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 8 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");
if (IS_ERR(mc->bcast_ch_regs)) {
dev_warn(&pdev->dev, "Broadcast channel is missing, please update your
device-tree\n");
returnPTR_ERR(mc->bcast_ch_regs);
}return 0;
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
to avoid DT ABI break, right?
Yes, it should be "return 0".
But if we "return 0" from here, then what about the case when
ioremap()actually fails with new DT i.e. when broadcast reg is present in DT? In that case error should be returned and probe should be failed, right?
You should check for the -ENOENT.
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 61 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 57 lines · Ashish Mhetre
Quoted 54 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 49 lines · Ashish Mhetre
Quoted 26 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 19 lines
+
num_dt_channels=
of_property_count_elems_of_size(pdev->dev.of_node, "reg",
+reg_cells*
sizeof(u32));(quoted diff) +2
-0+ /* + * On tegra186 onwards, memory controller support multiplechannels.
+ * Apart from regular memory controller channels, there is one
broadcastdrivers/memory/tegra/tegra186.c +4
-0+* channel and one for stream-id registers. +*/ +if (num_dt_channels < mc->soc->num_channels +2 ) { + dev_warn(&pdev->dev, "MC channels are missing, pleaseupdate memory controller DT node with MC channels\n");
drivers/memory/tegra/tegra186.c +4
-0+return 0 ; + } + + mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev,"mc-broadcast");
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 180
Quoted 2 lines
drivers/memory/tegra/tegra186.c +2
-0+if (IS_ERR (mc->bcast_ch_regs)) +return PTR_ERR (mc->bcast_ch_regs);Quoted 5 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()
and could only check the "mc-broadcast" presence to decide whether this is an older DT.Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 8 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");if (IS_ERR(mc->bcast_ch_regs)) { dev_warn(&pdev->dev, "Broadcast channel is missing, please update your device-tree\n"); return PTR_ERR(mc->bcast_ch_regs); }return 0;
to avoid DT ABI break, right?
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
Yes, it should be "return 0".
But if we "return 0" from here, then what about the case when
ioremap()actually fails with new DT i.e. when broadcast reg is present in DT? In that case error should be returned and probe should be failed, right?You should check for the
-ENOENT.
I checked __devm_ioremap_resource(), it returns -EINVAL if given resource is not present. So should we check for -EINVAL instead?
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 68 lines · Ashish Mhetre
Quoted 65 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 61 lines · Ashish Mhetre
Quoted 57 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 48 lines · Ashish Mhetre
Quoted 27 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 14 lines
+
num_dt_channels= of_property_count_elems_of_size(pdev->dev.of_node, "reg", +reg_cells* sizeof(u32));
+ /*
+ * On tegra186 onwards, memory controller support multiple channels.
+ * Apart from regular memory controller channels, there is one broadcast
+ * channel and one for stream-id registers.
+ */
+ if (num_dt_channels<mc->soc->num_channels+ 2) { +dev_warn(&pdev->dev, "MC channels are missing, please update memory controller DT node with MC channels\n");Quoted 8 lines
+ return 0;
+ }
+
+mc->bcast_ch_regs=
devm_platform_ioremap_resource_byname(pdev,
"mc-broadcast");
+ if (IS_ERR(mc->bcast_ch_regs))
+ returnPTR_ERR(mc->bcast_ch_regs);Quoted 6 lines
Looks to me that you don't need to use
of_property_count_elems_of_size()
and could only check the "mc-broadcast" presence to decide whether this
is an older DT.Now that we are using reg-names in new DT, yes it'd be fine to just check mc-broadcast to decide it's a new or old DT.
Quoted 8 lines
mc->bcast_ch_regs=devm_platform_ioremap_resource_byname(pdev, "broadcast");
if (IS_ERR(mc->bcast_ch_regs)) {
dev_warn(&pdev->dev, "Broadcast channel is missing, please update your
device-tree\n");
returnPTR_ERR(mc->bcast_ch_regs);
}Quoted 3 lines
return 0;
to avoid DT ABI break, right?
Yes, it should be "return 0".
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
But if we "return 0" from here, then what about the case when
ioremap()actually fails with new DT i.e. when broadcast reg is present in DT? In that case error should be returned and probe should be failed, right?You should check for the
-ENOENT.I checked
__devm_ioremap_resource(), it returns-EINVALif given resource is not present. So should we check for-EINVALinstead?
Yes
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
In reply to Ashish Mhetre06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 15 lines
include/soc/tegra/mc.h +3
-0@@ -13,6 +13,9 @@#include <linux/irq.h> #include <linux/reset-controller.h> #include <linux/types.h> +#include <linux/platform_device.h> + +#define MC_MAX_CHANNELS 16struct clk ;struct device ;
include/soc/tegra/mc.h struct tegra_mc_ops { · line 187
Quoted 4 lines
include/soc/tegra/mc.h +1
-0@@ -181,6 +184,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc,struct platform_device *pdev);
Use to_platform_device(mc->dev) instead of passing the pdev argument.
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 16 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 12 lines
include/soc/tegra/mc.h +3
-0@@ -13,6 +13,9 @@#include <linux/irq.h> #include <linux/reset-controller.h> #include <linux/types.h> +#include <linux/platform_device.h> + +#define MC_MAX_CHANNELS 16
Quoted 9 lines
include/soc/tegra/mc.h struct tegra_mc_ops { · line 187
Quoted 7 lines
include/soc/tegra/mc.h +1
-0struct clk ;struct device ;@@ -181,6 +184,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc,struct platform_device *pdev);Use
to_platform_device(mc->dev)instead of passing the pdev argument.
Okay, I'll update in v7.
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
In reply to Ashish Mhetre06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 31 lines
include/soc/tegra/mc.h +5
-0@@ -13,6 +13,9 @@#include <linux/irq.h> #include <linux/reset-controller.h> #include <linux/types.h> +#include <linux/platform_device.h> + +#define MC_MAX_CHANNELS 16struct clk ;struct device ;@@ -181,6 +184,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc,struct platform_device *pdev); };struct tegra_mc_soc {@@ -194,6 +198,7 @@ struct tegra_mc_soc {unsigned int atom_size;u8 client_id_mask; +u8 num_channels;const struct tegra_smmu_soc *smmu;
include/soc/tegra/mc.h struct tegra_mc { · line 221
Quoted 5 lines
include/soc/tegra/mc.h +2
-0@@ -212,6 +217,8 @@ struct tegra_mc {struct tegra_smmu *smmu;struct gart_device *gart;void __iomem *regs; +void __iomem *bcast_ch_regs; +void __iomem *ch_regs[MC_MAX_CHANNELS ];
Why not to allocate ch_regs at runtime?
Re: [Patch v6 1/4] memory: tegra: Add memory controller channels support
Quoted 34 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 30 lines
include/soc/tegra/mc.h +5
-0@@ -13,6 +13,9 @@#include <linux/irq.h> #include <linux/reset-controller.h> #include <linux/types.h> +#include <linux/platform_device.h> + +#define MC_MAX_CHANNELS 16struct clk ;struct device ;@@ -181,6 +184,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc,struct platform_device *pdev); };struct tegra_mc_soc {@@ -194,6 +198,7 @@ struct tegra_mc_soc {unsigned int atom_size;u8 client_id_mask; +u8 num_channels;const struct tegra_smmu_soc *smmu;
Quoted 8 lines
include/soc/tegra/mc.h struct tegra_mc { · line 221
Quoted 6 lines
include/soc/tegra/mc.h +2
-0@@ -212,6 +217,8 @@ struct tegra_mc {struct tegra_smmu *smmu;struct gart_device *gart;void __iomem *regs; +void __iomem *bcast_ch_regs; +void __iomem *ch_regs[MC_MAX_CHANNELS ];Why not to allocate
ch_regsat runtime?
Yes, we can do that. I'll make necessary changes in v7.
PATCH v6 2/4 memory: tegra: Add MC error logging on tegra186 onward
In reply to Ashish MhetreAdd support for reading MC_GLOBAL_INTSTATUS register which points to the memory controller channels on which interrupts have occurred. Add new function 'global_intstatus_to_channel' which returns the channel which should be used to get the information of interrupts. Remove static from tegra30_mc_handle_irq and use it as interrupt handler for MC interrupts on tegra186, tegra194 and tegra234 to log the errors. Add error specific MC status and address register bits and use them on tegra186, tegra194 and tegra234.
Add error logging for generalized carveout interrupt on tegra186, tegra194 and tegra234.
Add error logging for route sanity interrupt on tegra194 an tegra234. Add register for higher bits of error address which is available on tegra194 and tegra234.
Add a boolean variable 'has_addr_hi_reg' in tegra_mc_soc struture which will be true if soc has register for higher bits of memory controller error address. Set it true for tegra194 and tegra234.
Clear the global_intstatus bit corresponding to channel of which interrupts are logged.
--- drivers/memory/tegra/mc.c | 128 ++++++++++++++++++++++++++++---- drivers/memory/tegra/mc.h | 37 ++++++++- drivers/memory/tegra/tegra186.c | 9 +++ drivers/memory/tegra/tegra194.c | 8 ++ drivers/memory/tegra/tegra234.c | 7 ++ include/soc/tegra/mc.h | 3 + 6 files changed, 175 insertions(+), 17 deletions(-)
drivers/memory/tegra/mc.c +112 -16
@@ -508,14 +508,48 @@ int tegra30_mc_probe(struct tegra_mc *mc)return 0 ; } -static irqreturn_t tegra30_mc_handle_irq (int irq,void *data) +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, + .handle_irq = tegra30_mc_handle_irq, +}; +#endif + +static int global_intstatus_to_channel (const struct tegra_mc *mc,u32 status, +unsigned int *mc_channel) +{ +if ((status & mc->soc->ch_intmask) ==0 ) +return -EINVAL ; + + *mc_channel =__ffs ((status & mc->soc->ch_intmask) >> + mc->soc->status_reg_chan_shift); + +return 0 ; +} + +irqreturn_t tegra30_mc_handle_irq (int irq,void *data) {struct tegra_mc *mc = data; +unsigned int bit, channel;unsigned long status; -unsigned int bit; -/* mask all interrupts to avoid flooding */ - status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; +if (mc->soc->num_channels) { +u32 global_status; +int err; + + global_status =mc_ch_readl (mc,MC_BROADCAST_CHANNEL ,MC_GLOBAL_INTSTATUS ); + err =global_intstatus_to_channel (mc, global_status, &channel); +if (err <0 ) { +dev_err_ratelimited (mc->dev,"unknown interrupt channel 0x%08x\n" , + global_status); +return IRQ_NONE ; + } + +/* mask all interrupts to avoid flooding */ + status =mc_ch_readl (mc, channel,MC_INTSTATUS ) & mc->soc->intmask; + }else { + status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; + } +if (!status)return IRQ_NONE ;
@@ -523,18 +557,70 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data)const char *error = tegra_mc_status_names[bit] ?:"unknown" ;const char *client ="unknown" , *desc;const char *direction, *secure; +u32 status_reg, addr_reg; +u32 intmask =BIT (bit);phys_addr_t addr =0 ; +#ifdef CONFIG_PHYS_ADDR_T_64BIT +u32 addr_hi_reg =0 ; +#endif unsigned int i;char perm[7 ];u8 id, type;u32 value; - value =mc_readl (mc,MC_ERR_STATUS ); +switch (intmask) { +case MC_INT_DECERR_VPR : + status_reg =MC_ERR_VPR_STATUS ; + addr_reg =MC_ERR_VPR_ADR ; +break ; + +case MC_INT_SECERR_SEC : + status_reg =MC_ERR_SEC_STATUS ; + addr_reg =MC_ERR_SEC_ADR ; +break ; + +case MC_INT_DECERR_MTS : + status_reg =MC_ERR_MTS_STATUS ; + addr_reg =MC_ERR_MTS_ADR ; +break ; + +case MC_INT_DECERR_GENERALIZED_CARVEOUT : + status_reg =MC_ERR_GENERALIZED_CARVEOUT_STATUS ; + addr_reg =MC_ERR_GENERALIZED_CARVEOUT_ADR ; +break ; + +case MC_INT_DECERR_ROUTE_SANITY : + status_reg =MC_ERR_ROUTE_SANITY_STATUS ; + addr_reg =MC_ERR_ROUTE_SANITY_ADR ; +break ; + +default : + status_reg =MC_ERR_STATUS ; + addr_reg =MC_ERR_ADR ; + +#ifdef CONFIG_PHYS_ADDR_T_64BIT +if (mc->soc->has_addr_hi_reg) + addr_hi_reg =MC_ERR_ADR_HI ; +#endif +break ; + } + +if (mc->soc->num_channels) + value =mc_ch_readl (mc, channel, status_reg); +else + value =mc_readl (mc, status_reg);#ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits >32 ) { - addr = ((value >>MC_ERR_STATUS_ADR_HI_SHIFT ) & -MC_ERR_STATUS_ADR_HI_MASK ); +if (addr_hi_reg) { +if (mc->soc->num_channels) + addr =mc_ch_readl (mc, channel, addr_hi_reg); +else + addr =mc_readl (mc, addr_hi_reg); + }else { + addr = ((value >>MC_ERR_STATUS_ADR_HI_SHIFT ) & +MC_ERR_STATUS_ADR_HI_MASK ); + } addr <<=32 ; }#endif
@@ -591,7 +677,10 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data)break ; } - value =mc_readl (mc,MC_ERR_ADR ); +if (mc->soc->num_channels) + value =mc_ch_readl (mc, channel, addr_reg); +else + value =mc_readl (mc, addr_reg); addr |= value; dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
@@ -600,17 +689,18 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) }/* clear interrupts */ -mc_writel (mc, status,MC_INTSTATUS ); +if (mc->soc->num_channels) { +u32 status_chan_bit; + +mc_ch_writel (mc, channel, status,MC_INTSTATUS ); + status_chan_bit =BIT (channel) << mc->soc->status_reg_chan_shift; +mc_ch_writel (mc,MC_BROADCAST_CHANNEL , status_chan_bit,MC_GLOBAL_INTSTATUS ); + }else +mc_writel (mc, status,MC_INTSTATUS );return IRQ_HANDLED ; } -const struct tegra_mc_ops tegra30_mc_ops = { - .probe = tegra30_mc_probe, - .handle_irq = tegra30_mc_handle_irq, -}; -#endif -const char *const tegra_mc_status_names[32 ] = { [1 ] ="External interrupt" , [6 ] ="EMEM address decode error" ,
@@ -622,6 +712,8 @@ const char *const tegra_mc_status_names[32] = { [12] = "VPR violation", [13] = "Secure carveout violation", [16] = "MTS carveout violation", + [17] = "Generalized carveout violation", + [20] = "Route Sanity error", };const char *const tegra_mc_error_names[8 ] = {
@@ -770,7 +862,11 @@ static int tegra_mc_probe(struct platform_device *pdev)WARN (!mc->soc->client_id_mask,"missing client ID mask for this SoC\n" ); -mc_writel (mc, mc->soc->intmask,MC_INTMASK ); +if (mc->soc->num_channels && mc->bcast_ch_regs) +mc_ch_writel (mc,MC_BROADCAST_CHANNEL , mc->soc->intmask, +MC_INTMASK ); +else +mc_writel (mc, mc->soc->intmask,MC_INTMASK ); err =devm_request_irq (&pdev->dev, mc->irq, mc->soc->ops->handle_irq,0 ,dev_name (&pdev->dev), mc);
drivers/memory/tegra/mc.h +36 -1
@@ -43,7 +43,21 @@#define MC_EMEM_ARB_OVERRIDE 0xe8#define MC_TIMING_CONTROL_DBG 0xf8#define MC_TIMING_CONTROL 0xfc - +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_ERR_ADR_HI 0x11fc + +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)#define MC_INT_DECERR_MTS BIT(16)#define MC_INT_SECERR_SEC BIT(13)#define MC_INT_DECERR_VPR BIT(12)
@@ -78,6 +92,8 @@#define MC_TIMING_UPDATE BIT(0) +#define MC_BROADCAST_CHANNEL ~0 +static inline u32 tegra_mc_scale_percents (u64 val,unsigned int percents) { val = val * percents;
@@ -92,6 +108,24 @@ icc_provider_to_tegra_mc(struct icc_provider *provider) return container_of(provider, struct tegra_mc, provider); } +static inline u32 mc_ch_readl (const struct tegra_mc *mc,int ch, +unsigned long offset) +{ +if (ch ==MC_BROADCAST_CHANNEL ) +return readl_relaxed (mc->bcast_ch_regs + offset); + +return readl_relaxed (mc->ch_regs[ch] + offset); +} + +static inline void mc_ch_writel (const struct tegra_mc *mc,int ch, +u32 value,unsigned long offset) +{ +if (ch ==MC_BROADCAST_CHANNEL ) +writel_relaxed (value, mc->bcast_ch_regs + offset); +else +writel_relaxed (value, mc->ch_regs[ch] + offset); +} +static inline u32 mc_readl (const struct tegra_mc *mc,unsigned long offset) {return readl_relaxed (mc->regs + offset);
@@ -156,6 +190,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops;extern const struct tegra_mc_ops tegra186_mc_ops;#endif +irqreturn_t tegra30_mc_handle_irq (int irq,void *data);extern const char *const tegra_mc_status_names[32 ];extern const char *const tegra_mc_error_names[8 ];
drivers/memory/tegra/tegra186.c +9 -0
@@ -16,6 +16,8 @@#include <dt-bindings/memory/tegra186-mc.h> #endif +#include "mc.h" +#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
@@ -197,6 +199,7 @@ const struct tegra_mc_ops tegra186_mc_ops = { .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, .map_regs = tegra186_mc_map_regs, + .handle_irq = tegra30_mc_handle_irq, };#if defined(CONFIG_ARCH_TEGRA_186_SOC )
@@ -929,6 +932,12 @@ const struct tegra_mc_soc tegra186_mc_soc = { .clients = tegra186_mc_clients, .num_address_bits = 40, .num_channels = 4, + .client_id_mask = 0xff, + .intmask =MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000000f, + .status_reg_chan_shift = 0, };#endif
drivers/memory/tegra/tegra194.c +8 -0
@@ -1348,5 +1348,13 @@ const struct tegra_mc_soc tegra194_mc_soc = { .clients = tegra194_mc_clients, .num_address_bits = 40, .num_channels = 16, + .client_id_mask = 0xff, + .intmask =MC_INT_DECERR_ROUTE_SANITY | +MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x00000f00, + .status_reg_chan_shift = 8, };
drivers/memory/tegra/tegra234.c +7 -0
@@ -98,5 +98,12 @@ const struct tegra_mc_soc tegra234_mc_soc = { .clients = tegra234_mc_clients, .num_address_bits = 40, .num_channels = 16, + .intmask =MC_INT_DECERR_ROUTE_SANITY | +MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000ff00, + .status_reg_chan_shift = 8, };
include/soc/tegra/mc.h +3 -0
@@ -203,6 +203,9 @@ struct tegra_mc_soc {const struct tegra_smmu_soc *smmu;u32 intmask; +u32 ch_intmask; +u32 status_reg_chan_shift; +bool has_addr_hi_reg;const struct tegra_mc_reset_ops *reset_ops;const struct tegra_mc_reset *resets;
Signature · 1 line
2.17.1
Re: [Patch v6 2/4] memory: tegra: Add MC error logging on tegra186 onward
06.04.2022 08:24, Ashish Mhetre пишет:
drivers/memory/tegra/mc.c static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) · line 696
Quoted 7 lines
drivers/memory/tegra/mc.c +5
-1/* clear interrupts */ -mc_writel (mc, status,MC_INTSTATUS ); +if (mc->soc->num_channels) { +u32 status_chan_bit; + +mc_ch_writel (mc, channel, status,MC_INTSTATUS ); + status_chan_bit =BIT (channel) << mc->soc->status_reg_chan_shift;
s/status_reg_chan_shift/global_intstatus_channel_shift/
drivers/memory/tegra/mc.c static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) · line 697
Quoted 1 line
drivers/memory/tegra/mc.c +1
-0+mc_ch_writel (mc,MC_BROADCAST_CHANNEL , status_chan_bit,MC_GLOBAL_INTSTATUS );
and maybe add a one-line mc_channel_to_global_intstatus(mc, channel) helper
mc_ch_writel(mc, MC_BROADCAST_CHANNEL,
mc_channel_to_global_intstatus(mc, chan), MC_GLOBAL_INTSTATUS);
drivers/memory/tegra/mc.c static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) · line 699
Quoted 2 lines
drivers/memory/tegra/mc.c +2
-0+ }else +mc_writel (mc, status,MC_INTSTATUS );
Missing braces after "else", "./scripts/checkpatch.pl --strict" should warn about this.
Otherwise this patch looks okay at a quick glance.
Re: [Patch v6 2/4] memory: tegra: Add MC error logging on tegra186 onward
Quoted 12 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
drivers/memory/tegra/mc.c static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) · line 696
Quoted 7 lines
/* clear interrupts */drivers/memory/tegra/mc.c +5
-1-mc_writel (mc, status,MC_INTSTATUS ); +if (mc->soc->num_channels) { +u32 status_chan_bit; + +mc_ch_writel (mc, channel, status,MC_INTSTATUS ); + status_chan_bit =BIT (channel) << mc->soc->status_reg_chan_shift;
Quoted 2 lines
s/status_reg_chan_shift/global_intstatus_channel_shift/
Okay, I'll update in v7.
Quoted 7 lines
Quoted 1 line
+
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, status_chan_bit, MC_GLOBAL_INTSTATUS);and maybe add a one-line
mc_channel_to_global_intstatus(mc, channel)helpermc_ch_writel(mc,
MC_BROADCAST_CHANNEL,mc_channel_to_global_intstatus(mc, chan), MC_GLOBAL_INTSTATUS);
Okay, I'll add helper for getting status bit from channel and use it.
Quoted 5 lines
drivers/memory/tegra/mc.c static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) · line 699
Quoted 2 lines
drivers/memory/tegra/mc.c +2
-0+ }else +mc_writel (mc, status,MC_INTSTATUS );Missing braces after "else", "
./scripts/checkpatch.pl--strict" should warn about this.
I didn't run checkpatch.pl with "--strict". I will run from next time and address this.
Quoted 1 line
Otherwise this patch looks okay at a quick glance.
Thanks Dmitry. I'll address these comments.
PATCH v6 3/4 dt-bindings: memory: Update reg maxitems for tegra186
In reply to Ashish MhetreFrom tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation.
--- .../memory-controllers/nvidia,tegra186-mc.yaml | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +12 -3
@@ -35,7 +35,7 @@ properties: reg: minItems: 1 - maxItems: 3 + maxItems: 18 interrupts: items:
@@ -142,7 +142,8 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers - if: properties:
@@ -152,6 +153,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers - if: properties:
@@ -161,6 +163,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers additionalProperties: false
@@ -182,7 +185,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>;
Signature · 1 line
2.17.1
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
06.04.2022 08:24, Ashish Mhetre пишет:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml examples: · line 194
Quoted 10 lines
memory-controller@2c00000 { compatible = "nvidia,tegra186-mc";Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3";
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"
You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Quoted 15 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml examples: · line 194
Quoted 10 lines
memory-controller@2c00000 { compatible = "nvidia,tegra186-mc";Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3";
Quoted 4 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"
Okay, I'll update the reg-names by omitting "mc-".
Quoted 3 lines
You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I'll add validation of reg-names as well.
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
In reply to Dmitry OsipenkoQuoted 15 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml examples: · line 194
Quoted 10 lines
memory-controller@2c00000 { compatible = "nvidia,tegra186-mc";Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3";
Quoted 7 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I will add validation of reg-names as following:
reg-names:
minItems: 0
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
We will have to keep minItems to 0 in order to make it compatible with old DT, right?
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Quoted 42 lines · Ashish Mhetre
Quoted 17 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 4 lines
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
- reg = <0x00x02c000000x00xb0000>;
+ reg = <0x00x02c000000x00x10000>, /* MC-SID */Quoted 8 lines
+ <
0x00x02c100000x00x10000>, /* Broadcast channel */
+ <0x00x02c200000x00x10000>, /* MC0 */ + <0x00x02c300000x00x10000>, /* MC1 */ + <0x00x02c400000x00x10000>, /* MC2 */ + <0x00x02c500000x00x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3";Quoted 7 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"
You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I will add validation of reg-names as following:
reg-names:
minItems: 0
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
Quoted 2 lines
We will have to keep minItems to 0 in order to make it compatible with old DT, right?
Bindings are about the latest DTs. In general older dtbs must be updated and you must get error from the schema checker for older DTs. It's only drivers that should care about older dtbs.
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Quoted 46 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 42 lines · Ashish Mhetre
Quoted 17 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 11 lines
memory-controller@2c00000 { compatible = "nvidia,tegra186-mc";Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1- reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1",Quoted 1 line
"mc2", "mc3";
Quoted 7 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I will add validation of reg-names as following:
reg-names:
minItems: 0
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
Quoted 6 lines
Quoted 2 lines
We will have to keep minItems to 0 in order to make it compatible with old DT, right?
Bindings are about the latest DTs. In general older dtbs must be updated and you must get error from the schema checker for older DTs. It's only drivers that should care about older dtbs.
On v5 Krzysztof mentioned that old DTS will start failing with new bindings https://lkml.org/lkml/2022/3/22/907.
So I just wanted to confirm whether it's fine if updated bindings start to fail with old DTS?
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Quoted 52 lines · Ashish Mhetre
Quoted 49 lines · Dmitry Osipenko
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Quoted 44 lines · Ashish Mhetre
Quoted 17 lines · Dmitry Osipenko
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06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 4 lines
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
- reg = <0x00x02c000000x00xb0000>;
+ reg = <0x00x02c000000x00x10000>, /* MC-SID */Quoted 8 lines
+ <
0x00x02c100000x00x10000>, /* Broadcast channel */
+ <0x00x02c200000x00x10000>, /* MC0 */ + <0x00x02c300000x00x10000>, /* MC1 */ + <0x00x02c400000x00x10000>, /* MC2 */ + <0x00x02c500000x00x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3";Quoted 7 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"
You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I will add validation of reg-names as following:
reg-names:
minItems: 0
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3We will have to keep minItems to 0 in order to make it compatible with old DT, right?
Quoted 8 lines
Quoted 3 lines
Bindings are about the latest DTs. In general older dtbs must be updated and you must get error from the schema checker for older DTs. It's only drivers that should care about older dtbs.
On v5 Krzysztof mentioned that old DTS will start failing with new bindings https://lkml.org/lkml/2022/3/22/907.
So I just wanted to confirm whether it's fine if updated bindings start to fail with old DTS?
Since the older DT was incorrect, it's fine that the DT check will fail for it.
Re: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186
Quoted 60 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 56 lines · Ashish Mhetre
Quoted 52 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 42 lines · Ashish Mhetre
Quoted 17 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
06.04.2022 08:24, Ashish Mhetre пишет:
Quoted 11 lines
memory-controller@2c00000 { compatible = "nvidia,tegra186-mc";Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1- reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1",Quoted 1 line
"mc2", "mc3";
Quoted 7 lines
The "mc-" prefix feels redundant to me, I'd name the regs like this:
"sid", "broadcast", "ch0", "ch1", "ch2", "ch3"You should also add validation of the regs/reg-names to the yaml based on SoC version. I.e. it's not enough to only bump the maxItems.
Okay, I will add validation of reg-names as following:
reg-names:
minItems: 0
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3Quoted 2 lines
We will have to keep minItems to 0 in order to make it compatible with old DT, right?
Bindings are about the latest DTs. In general older dtbs must be updated and you must get error from the schema checker for older DTs. It's only drivers that should care about older dtbs.
Quoted 7 lines
Quoted 4 lines
On v5 Krzysztof mentioned that old DTS will start failing with new bindings https://lkml.org/lkml/2022/3/22/907.
So I just wanted to confirm whether it's fine if updated bindings start to fail with old DTS?Since the older DT was incorrect, it's fine that the DT check will fail for it.
Thanks for confirming Dmitry. I will incorporate all comments and send v7.
PATCH v6 4/4 arm64: tegra: Add memory controller channels
In reply to Ashish MhetreFrom tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt.
So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping.
--- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/nvidia/tegra186.dtsi +7 -1
@@ -521,7 +521,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
arch/arm64/boot/dts/nvidia/tegra194.dtsi +21 -3
@@ -604,9 +604,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3", + "mc4", "mc5", "mc6", "mc7", "mc8", "mc9", "mc10", + "mc11", "mc12", "mc13", "mc14", "mc15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "disabled";
arch/arm64/boot/dts/nvidia/tegra234.dtsi +21 -3
@@ -507,9 +507,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3", + "mc4", "mc5", "mc6", "mc7", "mc8", "mc9", "mc10", + "mc11", "mc12", "mc13", "mc14", "mc15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "okay";
Signature · 1 line
2.17.1