csky: cmpxchg: Optimize with acquire & release
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[email protected]
maintainerPATCH 1/1 csky: cmpxchg: Optimize with acquire & release
From: Guo Ren <[email protected]>
Optimize arch_xchg|cmpxchg|cmpxchg_local with ASM acquire|release instructions instead of previous C based.
Signed-off-by Guo Ren <[email protected]>
Signed-off-by Guo Ren <[email protected]>
--- arch/csky/include/asm/barrier.h | 8 +- arch/csky/include/asm/cmpxchg.h | 173 ++++++++++++++++++++++++++++++-- 2 files changed, 172 insertions(+), 9 deletions(-)
arch/csky/include/asm/barrier.h +5 -3
@@ -37,6 +37,9 @@* bar.brar * bar.bwaw */ +#define ACQUIRE_FENCE ".long 0x8427c000\n" +#define RELEASE_FENCE ".long 0x842ec000\n" +#define __bar_brw () asm volatile (".long 0x842cc000\n":::"memory")#define __bar_br () asm volatile (".long 0x8424c000\n":::"memory")#define __bar_bw () asm volatile (".long 0x8428c000\n":::"memory")
@@ -44,10 +47,10 @@#define __bar_ar () asm volatile (".long 0x8421c000\n":::"memory")#define __bar_aw () asm volatile (".long 0x8422c000\n":::"memory")#define __bar_brwarw () asm volatile (".long 0x842fc000\n":::"memory") -#define __bar_brarw () asm volatile (".long 0x8427c000\n":::"memory") +#define __bar_brarw () asm volatile (ACQUIRE_FENCE:::"memory")#define __bar_bwarw () asm volatile (".long 0x842bc000\n":::"memory")#define __bar_brwar () asm volatile (".long 0x842dc000\n":::"memory") -#define __bar_brwaw () asm volatile (".long 0x842ec000\n":::"memory") +#define __bar_brwaw () asm volatile (RELEASE_FENCE:::"memory")#define __bar_brar () asm volatile (".long 0x8425c000\n":::"memory")#define __bar_brar () asm volatile (".long 0x8425c000\n":::"memory")#define __bar_bwaw () asm volatile (".long 0x842ac000\n":::"memory")
@@ -56,7 +59,6 @@#define __smp_rmb () __bar_brar()#define __smp_wmb () __bar_bwaw() -#define ACQUIRE_FENCE ".long 0x8427c000\n"#define __smp_acquire_fence () __bar_brarw()#define __smp_release_fence () __bar_brwaw()
arch/csky/include/asm/cmpxchg.h +167 -6
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2.25.1
Hi Guo,
Quoted 22 lines · On Wed, Apr 06, 2022 at 08:40:56PM +0800, [email protected] wrote:
From: Guo Ren <[email protected]>
Optimize arch_xchg|cmpxchg|cmpxchg_local with ASM acquire|release instructions instead of previous C based.
Signed-off-by Guo Ren <[email protected]>Signed-off-by Guo Ren <[email protected]>--- arch/csky/include/asm/barrier.h | 8 +- arch/csky/include/asm/cmpxchg.h | 173 ++++++++++++++++++++++++++++++-- 2 files changed, 172 insertions(+), 9 deletions(-)arch/csky/include/asm/barrier.h +2
-0@@ -37,6 +37,9 @@* bar.brar * bar.bwaw */ +#define ACQUIRE_FENCE ".long 0x8427c000\n" +#define RELEASE_FENCE ".long 0x842ec000\n"
[...]
Quoted 8 lines
arch/csky/include/asm/barrier.h +8
-0+#define __xchg (new, ptr, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(new) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + unsigned long tmp; \ + switch (size) { \ + case 4: \
arch/csky/include/asm/barrier.h
Quoted 10 lines
arch/csky/include/asm/barrier.h +10
-0+ asmvolatile ( \ +"1: ldex.w %0, (%3) \n" \ +ACQUIRE_FENCE \ +" mov %1, %2 \n" \ +RELEASE_FENCE \ +" stex.w %1, (%3) \n" \ +" bez %1, 1b \n" \ + :"=&r" (__ret),"=&r" (tmp) \ + :"r" (__new),"r" (__ptr) \ + :); \
As with the riscv case, I believe this suffers the problem described in:
8e86f0b409a44193 ("arm64: atomics: fix use of acquire + release for full barrier semantics")
... and does not provide FULL ordering semantics.
[...]
Quoted 12 lines
arch/csky/include/asm/barrier.h +12
-0+#define __cmpxchg (ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(new) __new = (new); \ + __typeof__(new) __tmp; \ + __typeof__(old) __old = (old); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + asm volatile ( \ + "1: ldex.w %0, (%3) \n" \ + ACQUIRE_FENCE \
arch/csky/include/asm/barrier.h
Quoted 10 lines
arch/csky/include/asm/barrier.h +10
-0+" cmpne %0, %4 \n" \ +" bt 2f \n" \ +" mov %1, %2 \n" \ +RELEASE_FENCE \ +" stex.w %1, (%3) \n" \ +" bez %1, 1b \n" \ +"2: \n" \ + : "=&r" (__ret), "=&r" (__tmp) \ +: " r" (__new), " r"(__ptr), " r"(__old) \ +:); \
Likewise.
Thanks,
Mark.