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mtd: spinand: add support for ESMT F50x1G41LB

PATCH Superseded Chuanhong Guo 1 participant 2 messages Apr 13, 2022

Subsystems (2)
Memory technology devices (MTD) NAND flash

v1 of 2 Superseded Latest is v2 →

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Chuanhong Guo

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PATCH 1/1 mtd: spinand: add support for ESMT F50x1G41LB

This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name.

Datasheets:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf

Signed-off-by Chuanhong Guo <[email protected]>
---
 drivers/mtd/nand/spi/Makefile |  2 +-
 drivers/mtd/nand/spi/core.c   |  1 +
 drivers/mtd/nand/spi/esmt.c   | 96 +++++++++++++++++++++++++++++++++++
 include/linux/mtd/spinand.h   |  1 +
 4 files changed, 99 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/spi/esmt.c
drivers/mtd/nand/spi/Makefile +1 -1
index 9662b9c1d5a9..7e3ab8a9aec7 100644
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
+spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
drivers/mtd/nand/spi/core.c +1 -0
index ff8336870bc0..6c5d79ec3501 100644
@@ -927,6 +927,7 @@ static const struct nand_ops spinand_ops = {
 };
 
 static const struct spinand_manufacturer *spinand_manufacturers[] = {
+	&esmt_c8_spinand_manufacturer,
 	&gigadevice_spinand_manufacturer,
 	&macronix_spinand_manufacturer,
 	&micron_spinand_manufacturer,
drivers/mtd/nand/spi/esmt.c new file +96 -0

96 lines not on this page · raw message

include/linux/mtd/spinand.h +1 -0
index 3aa28240a77f..e19a1554a1e9 100644
@@ -260,6 +260,7 @@ struct spinand_manufacturer {
 };
 
 /* SPI NAND manufacturers */
+extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
 extern const struct spinand_manufacturer micron_spinand_manufacturer;
Signature · 1 line
2.35.1
author
#1 lore raw
Quoted 13 lines · Chuanhong Guo

This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name.

Datasheets:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf

Signed-off-by Chuanhong Guo <[email protected]>
[...]

drivers/mtd/nand/spi/esmt.c line 67

Quoted 4 lines
drivers/mtd/nand/spi/esmt.c new file +4 -0
+static const struct spinand_info esmt_c8_spinand_table[] = {
+       SPINAND_INFO("F50L1G41LB",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f,
+                               0x7f, 0x7f),

This patch is broken. SPI NAND core doesn't support 5-byte ID atm.

Signature · 2 lines
Regards,
Chuanhong Guo