vmxnet3 version V5 and V6

index d1ef1cad08..a7e1e5fef5 100644
@@ -316,9 +316,12 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 
 	/* Check h/w version compatibility with driver. */
 	ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
-	PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
 
-	if (ver & (1 << VMXNET3_REV_4)) {
+	if (ver & (1 << VMXNET3_REV_5)) {
+		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
+				       1 << VMXNET3_REV_5);
+		hw->version = VMXNET3_REV_5 + 1;
+	} else if (ver & (1 << VMXNET3_REV_4)) {
 		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 				       1 << VMXNET3_REV_4);
 		hw->version = VMXNET3_REV_4 + 1;

index ef858ac951..7ec3b2e1f0 100644
@@ -124,11 +124,13 @@ struct vmxnet3_hw {
 	UPT1_RxStats          snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
 };
 
+#define VMXNET3_REV_5		4		/* Vmxnet3 Rev. 5 */
 #define VMXNET3_REV_4		3		/* Vmxnet3 Rev. 4 */
 #define VMXNET3_REV_3		2		/* Vmxnet3 Rev. 3 */
 #define VMXNET3_REV_2		1		/* Vmxnet3 Rev. 2 */
 #define VMXNET3_REV_1		0		/* Vmxnet3 Rev. 1 */
 
+#define VMXNET3_VERSION_GE_5(hw) ((hw)->version >= VMXNET3_REV_5 + 1)
 #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)

index a7e1e5fef5..d5f9903946 100644
@@ -95,6 +95,14 @@ static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
 				 struct rte_ether_addr *mac_addr);
 static void vmxnet3_process_events(struct rte_eth_dev *dev);
 static void vmxnet3_interrupt_handler(void *param);
+static int
+vmxnet3_rss_reta_update(struct rte_eth_dev *dev,
+			struct rte_eth_rss_reta_entry64 *reta_conf,
+			uint16_t reta_size);
+static int
+vmxnet3_rss_reta_query(struct rte_eth_dev *dev,
+		       struct rte_eth_rss_reta_entry64 *reta_conf,
+		       uint16_t reta_size);
 static int vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 						uint16_t queue_id);
 static int vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,

@@ -137,6 +145,8 @@ static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 	.tx_queue_release     = vmxnet3_dev_tx_queue_release,
 	.rx_queue_intr_enable = vmxnet3_dev_rx_queue_intr_enable,
 	.rx_queue_intr_disable = vmxnet3_dev_rx_queue_intr_disable,
+	.reta_update          = vmxnet3_rss_reta_update,
+	.reta_query           = vmxnet3_rss_reta_query,
 };
 
 struct vmxnet3_xstats_name_off {

@@ -1696,3 +1706,60 @@ RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_init, init, NOTICE);
 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_driver, driver, NOTICE);
+
+static int
+vmxnet3_rss_reta_update(struct rte_eth_dev *dev,
+			struct rte_eth_rss_reta_entry64 *reta_conf,
+			uint16_t reta_size)
+{
+	int i, idx, shift;
+	struct vmxnet3_hw *hw = dev->data->dev_private;
+	struct VMXNET3_RSSConf *dev_rss_conf = hw->rss_conf;
+
+	if (reta_size != dev_rss_conf->indTableSize) {
+		PMD_DRV_LOG(ERR,
+			"The size of hash lookup table configured (%d) doesn't match "
+			"the supported number (%d)",
+			reta_size, dev_rss_conf->indTableSize);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < reta_size; i++) {
+		idx = i / RTE_ETH_RETA_GROUP_SIZE;
+		shift = i % RTE_ETH_RETA_GROUP_SIZE;
+		if (reta_conf[idx].mask & RTE_BIT64(shift))
+			dev_rss_conf->indTable[i] = (uint8_t)reta_conf[idx].reta[shift];
+	}
+
+	VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
+				VMXNET3_CMD_UPDATE_RSSIDT);
+
+	return 0;
+}
+
+static int
+vmxnet3_rss_reta_query(struct rte_eth_dev *dev,
+		       struct rte_eth_rss_reta_entry64 *reta_conf,
+		       uint16_t reta_size)
+{
+	int i, idx, shift;
+	struct vmxnet3_hw *hw = dev->data->dev_private;
+	struct VMXNET3_RSSConf *dev_rss_conf = hw->rss_conf;
+
+	if (reta_size != dev_rss_conf->indTableSize) {
+		PMD_DRV_LOG(ERR,
+			"Size of requested hash lookup table (%d) doesn't "
+			"match the configured size (%d)",
+			reta_size, dev_rss_conf->indTableSize);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < reta_size; i++) {
+		idx = i / RTE_ETH_RETA_GROUP_SIZE;
+		shift = i % RTE_ETH_RETA_GROUP_SIZE;
+		if (reta_conf[idx].mask & RTE_BIT64(shift))
+			reta_conf[idx].reta[shift] = dev_rss_conf->indTable[i];
+	}
+
+	return 0;
+}

index d5f9903946..cd32c1b4ee 100644
@@ -294,6 +294,7 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 	eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
 	eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
 	eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
+	eth_dev->rx_queue_count = vmxnet3_dev_rx_queue_count;
 	pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 
 	/* extra mbuf field is required to guess MSS */

index 7ec3b2e1f0..ceaeb66392 100644
@@ -193,6 +193,9 @@ int  vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
 				uint16_t nb_rx_desc, unsigned int socket_id,
 				const struct rte_eth_rxconf *rx_conf,
 				struct rte_mempool *mb_pool);
+
+uint32_t vmxnet3_dev_rx_queue_count(void *rx_queue);
+
 int  vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 				uint16_t nb_tx_desc, unsigned int socket_id,
 				const struct rte_eth_txconf *tx_conf);

index d745064bc4..e15b377d8c 100644
@@ -1019,6 +1019,36 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 	return nb_rx;
 }
 
+uint32_t
+vmxnet3_dev_rx_queue_count(void *rx_queue)
+{
+	const vmxnet3_rx_queue_t *rxq;
+	const Vmxnet3_RxCompDesc *rcd;
+	uint32_t idx, nb_rxd = 0;
+	uint8_t gen;
+
+	rxq = rx_queue;
+	if (unlikely(rxq->stopped)) {
+		PMD_RX_LOG(DEBUG, "Rx queue is stopped.");
+		return 0;
+	}
+
+	gen = rxq->comp_ring.gen;
+	idx = rxq->comp_ring.next2proc;
+	rcd = &rxq->comp_ring.base[idx].rcd;
+	while (rcd->gen == gen) {
+		if (rcd->eop)
+			++nb_rxd;
+		if (++idx == rxq->comp_ring.size) {
+			idx = 0;
+			gen ^= 1;
+		}
+		rcd = &rxq->comp_ring.base[idx].rcd;
+	}
+
+	return nb_rxd;
+}
+
 int
 vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev,
 			   uint16_t queue_idx,

index cd32c1b4ee..d14ddfcbeb 100644
@@ -103,6 +103,10 @@ static int
 vmxnet3_rss_reta_query(struct rte_eth_dev *dev,
 		       struct rte_eth_rss_reta_entry64 *reta_conf,
 		       uint16_t reta_size);
+static int
+vmxnet3_hw_ver_get(struct rte_eth_dev *dev,
+		   char *fw_version, size_t fw_size);
+
 static int vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 						uint16_t queue_id);
 static int vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,

@@ -124,27 +128,28 @@ static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 	.dev_stop             = vmxnet3_dev_stop,
 	.dev_close            = vmxnet3_dev_close,
 	.dev_reset            = vmxnet3_dev_reset,
+	.link_update          = vmxnet3_dev_link_update,
 	.promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
 	.promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
 	.allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
 	.allmulticast_disable = vmxnet3_dev_allmulticast_disable,
-	.link_update          = vmxnet3_dev_link_update,
+	.mac_addr_set         = vmxnet3_mac_addr_set,
+	.mtu_set              = vmxnet3_dev_mtu_set,
 	.stats_get            = vmxnet3_dev_stats_get,
-	.xstats_get_names     = vmxnet3_dev_xstats_get_names,
-	.xstats_get           = vmxnet3_dev_xstats_get,
 	.stats_reset          = vmxnet3_dev_stats_reset,
-	.mac_addr_set         = vmxnet3_mac_addr_set,
+	.xstats_get           = vmxnet3_dev_xstats_get,
+	.xstats_get_names     = vmxnet3_dev_xstats_get_names,
+	.fw_version_get       = vmxnet3_hw_ver_get,
 	.dev_infos_get        = vmxnet3_dev_info_get,
 	.dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
-	.mtu_set              = vmxnet3_dev_mtu_set,
 	.vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
 	.vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
 	.rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
 	.rx_queue_release     = vmxnet3_dev_rx_queue_release,
-	.tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
-	.tx_queue_release     = vmxnet3_dev_tx_queue_release,
 	.rx_queue_intr_enable = vmxnet3_dev_rx_queue_intr_enable,
 	.rx_queue_intr_disable = vmxnet3_dev_rx_queue_intr_disable,
+	.tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
+	.tx_queue_release     = vmxnet3_dev_tx_queue_release,
 	.reta_update          = vmxnet3_rss_reta_update,
 	.reta_query           = vmxnet3_rss_reta_query,
 };

@@ -1764,3 +1769,19 @@ vmxnet3_rss_reta_query(struct rte_eth_dev *dev,
 
 	return 0;
 }
+
+static int
+vmxnet3_hw_ver_get(struct rte_eth_dev *dev,
+		   char *fw_version, size_t fw_size)
+{
+	int ret;
+	struct vmxnet3_hw *hw = dev->data->dev_private;
+
+	ret = snprintf(fw_version, fw_size, "v%d", hw->version);
+
+	ret += 1; /* add the size of '\0' */
+	if (fw_size < (uint32_t)ret)
+		return ret;
+	else
+		return 0;
+}

index 8d62b3e116..bd6695e69d 100644
@@ -103,7 +103,11 @@ typedef enum {
    VMXNET3_CMD_GET_CONF_INTR,
    VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,
    VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
-   VMXNET3_CMD_RESERVED5,
+	VMXNET3_CMD_RESERVED5,
+	VMXNET3_CMD_RESERVED6,
+	VMXNET3_CMD_RESERVED7,
+	VMXNET3_CMD_RESERVED8,
+	VMXNET3_CMD_GET_MAX_QUEUES_CONF,
 } Vmxnet3_Cmd;
 
 /* Adaptive Ring Info Flags */

@@ -571,6 +575,24 @@ enum vmxnet3_intr_type {
 /* addition 1 for events */
 #define VMXNET3_MAX_INTRS      25
 
+/* Version 6 and later will use below macros */
+#define VMXNET3_EXT_MAX_TX_QUEUES  32
+#define VMXNET3_EXT_MAX_RX_QUEUES  32
+
+/* Version-dependent MAX RX/TX queues macro */
+#define MAX_RX_QUEUES(hw) \
+	(VMXNET3_VERSION_GE_6((hw)) ? \
+	VMXNET3_EXT_MAX_RX_QUEUES : \
+	VMXNET3_MAX_RX_QUEUES)
+#define MAX_TX_QUEUES(hw) \
+	(VMXNET3_VERSION_GE_6((hw)) ? \
+	VMXNET3_EXT_MAX_TX_QUEUES : \
+	VMXNET3_MAX_TX_QUEUES)
+
+/* addition 1 for events */
+#define VMXNET3_EXT_MAX_INTRS      65
+#define VMXNET3_FIRST_SET_INTRS    64
+
 /* value of intrCtrl */
 #define VMXNET3_IC_DISABLE_ALL  0x1   /* bit 0 */
 

@@ -587,6 +609,21 @@ struct Vmxnet3_IntrConf {
 #include "vmware_pack_end.h"
 Vmxnet3_IntrConf;
 
+typedef
+#include "vmware_pack_begin.h"
+struct Vmxnet3_IntrConfExt {
+	uint8    autoMask;
+	uint8    numIntrs;      /* # of interrupts */
+	uint8    eventIntrIdx;
+	uint8    reserved;
+	__le32   intrCtrl;
+	__le32   reserved1;
+	uint8    modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for each intr */
+	uint8    reserved2[3];
+}
+#include "vmware_pack_end.h"
+Vmxnet3_IntrConfExt;
+
 /* one bit per VLAN ID, the size is in the units of uint32 */
 #define VMXNET3_VFT_SIZE  (4096 / (sizeof(uint32) * 8))
 

@@ -692,6 +729,15 @@ struct Vmxnet3_DSDevRead {
 #include "vmware_pack_end.h"
 Vmxnet3_DSDevRead;
 
+typedef
+#include "vmware_pack_begin.h"
+struct Vmxnet3_DSDevReadExt {
+	/* read-only region for device, read by dev in response to a SET cmd */
+	struct Vmxnet3_IntrConfExt    intrConfExt;
+}
+#include "vmware_pack_end.h"
+Vmxnet3_DSDevReadExt;
+
 typedef
 #include "vmware_pack_begin.h"
 struct Vmxnet3_TxQueueDesc {

@@ -778,18 +824,18 @@ Vmxnet3_CmdInfo;
 typedef
 #include "vmware_pack_begin.h"
 struct Vmxnet3_DriverShared {
-   __le32               magic;
-   __le32               pad; /* make devRead start at 64-bit boundaries */
-   Vmxnet3_DSDevRead    devRead;
-   __le32               ecr;
-   __le32               reserved;
-
-   union {
-      __le32            reserved1[4];
-      Vmxnet3_CmdInfo   cmdInfo; /* only valid in the context of executing the
-				  * relevant command
-				  */
-   } cu;
+	__le32               magic;
+	__le32               size;    /* size of DriverShared */
+	Vmxnet3_DSDevRead    devRead;
+	__le32               ecr;
+	__le32               reserved;
+
+	union {
+		__le32			reserved1[4];
+		/* only valid in the context of executing the relevant command */
+		Vmxnet3_CmdInfo	cmdInfo;
+	} cu;
+	struct Vmxnet3_DSDevReadExt   devReadExt;
 }
 #include "vmware_pack_end.h"
 Vmxnet3_DriverShared;

@@ -821,6 +867,7 @@ do {\
    ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
 
 #define VMXNET3_MAX_MTU     9000
+#define VMXNET3_V6_MAX_MTU  9190
 #define VMXNET3_MIN_MTU     60
 
 #define VMXNET3_LINK_UP         (10000 << 16 | 1)    // 10 Gbps, up

339 lines not on this page · raw message

index ceaeb66392..5a303717b1 100644
@@ -70,7 +70,7 @@ struct vmxnet3_intr {
 	enum vmxnet3_intr_type      type; /* MSI-X, MSI, or INTx? */
 	uint8_t num_intrs;                /* # of intr vectors */
 	uint8_t event_intr_idx;           /* idx of the intr vector for event */
-	uint8_t mod_levels[VMXNET3_MAX_MSIX_VECT]; /* moderation level */
+	uint8_t mod_levels[VMXNET3_EXT_MAX_INTRS]; /* moderation level */
 	bool lsc_only;                    /* no Rx queue interrupt */
 };
 

@@ -108,6 +108,7 @@ struct vmxnet3_hw {
 	uint64_t              queueDescPA;
 	uint16_t              queue_desc_len;
 	uint16_t              mtu;
+	bool                  queuesExtEnabled;
 
 	VMXNET3_RSSConf       *rss_conf;
 	uint64_t              rss_confPA;

@@ -117,19 +118,20 @@ struct vmxnet3_hw {
 	Vmxnet3_MemRegs	      *memRegs;
 	uint64_t	      memRegsPA;
 #define VMXNET3_VFT_TABLE_SIZE     (VMXNET3_VFT_SIZE * sizeof(uint32_t))
-	UPT1_TxStats	      saved_tx_stats[VMXNET3_MAX_TX_QUEUES];
-	UPT1_RxStats	      saved_rx_stats[VMXNET3_MAX_RX_QUEUES];
-
+	UPT1_TxStats	      saved_tx_stats[VMXNET3_EXT_MAX_TX_QUEUES];
+	UPT1_RxStats	      saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES];
 	UPT1_TxStats          snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];
 	UPT1_RxStats          snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
 };
 
+#define VMXNET3_REV_6		5		/* Vmxnet3 Rev. 6 */
 #define VMXNET3_REV_5		4		/* Vmxnet3 Rev. 5 */
 #define VMXNET3_REV_4		3		/* Vmxnet3 Rev. 4 */
 #define VMXNET3_REV_3		2		/* Vmxnet3 Rev. 3 */
 #define VMXNET3_REV_2		1		/* Vmxnet3 Rev. 2 */
 #define VMXNET3_REV_1		0		/* Vmxnet3 Rev. 1 */
 
+#define VMXNET3_VERSION_GE_6(hw) ((hw)->version >= VMXNET3_REV_6 + 1)
 #define VMXNET3_VERSION_GE_5(hw) ((hw)->version >= VMXNET3_REV_5 + 1)
 #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)

index e15b377d8c..c94e3762e6 100644
@@ -1400,7 +1400,7 @@ vmxnet3_rss_configure(struct rte_eth_dev *dev)
 	/* loading hashKeySize */
 	dev_rss_conf->hashKeySize = VMXNET3_RSS_MAX_KEY_SIZE;
 	/* loading indTableSize: Must not exceed VMXNET3_RSS_MAX_IND_TABLE_SIZE (128)*/
-	dev_rss_conf->indTableSize = (uint16_t)(hw->num_rx_queues * 4);
+	dev_rss_conf->indTableSize = (uint16_t)((MAX_RX_QUEUES(hw)) * 4);
 
 	if (port_rss_conf->rss_key == NULL) {
 		/* Default hash key */

index af4a1a1b40..e2a695fa88 100644
@@ -1480,7 +1480,12 @@ vmxnet3_dev_info_get(struct rte_eth_dev *dev,
 	dev_info->rx_queue_offload_capa = 0;
 	dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
 	dev_info->tx_queue_offload_capa = 0;
-
+	if (hw->rss_conf == NULL) {
+		/* RSS not configured */
+		dev_info->reta_size = 0;
+	} else {
+		dev_info->reta_size = hw->rss_conf->indTableSize;
+	}
 	return 0;
 }
 

index c94e3762e6..a875ffec07 100644
@@ -759,6 +759,23 @@ vmxnet3_rx_offload(struct vmxnet3_hw *hw, const Vmxnet3_RxCompDesc *rcd,
 		/* Check packet type, checksum errors, etc. */
 		if (rcd->cnc) {
 			ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
+
+			if (rcd->v4) {
+				packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+				if (rcd->tcp)
+					packet_type |= RTE_PTYPE_L4_TCP;
+				else if (rcd->udp)
+					packet_type |= RTE_PTYPE_L4_UDP;
+			} else if (rcd->v6) {
+				packet_type |= RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+				if (rcd->tcp)
+					packet_type |= RTE_PTYPE_L4_TCP;
+				else if (rcd->udp)
+					packet_type |= RTE_PTYPE_L4_UDP;
+			} else {
+				packet_type |= RTE_PTYPE_UNKNOWN;
+			}
+
 		} else {
 			if (rcd->v4) {
 				packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;

index e2a695fa88..fe999c772e 100644
@@ -876,6 +876,11 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
 		rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
 		rqd->conf.compRingSize    = rxq->comp_ring.size;
 
+		if (VMXNET3_VERSION_GE_3(hw)) {
+			rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
+			rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
+		}
+
 		if (hw->intr.lsc_only)
 			rqd->conf.intrIdx = 1;
 		else