dt-bindings: Arm CoreSight binding schema conversions

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.

Signed-off-by Rob Herring <[email protected]>

--
v2:
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references
- Fix double blank line

---
  .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
  .../bindings/arm/arm,coresight-cti.yaml       |   3 +-
  .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
  .../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
  .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
  .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
  .../arm/arm,coresight-static-funnel.yaml      |  89 ++++
  .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
  .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
  .../bindings/arm/arm,coresight-tmc.yaml       | 131 ++++++
  .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
  .../arm/arm,embedded-trace-extension.yaml     |   1 -
  .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
  Documentation/trace/coresight/coresight.rst   |   2 +-
  MAINTAINERS                                   |   3 +-
  15 files changed, 1106 insertions(+), 408 deletions(-)

create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +54 -0

new file mode 100644
index 000000000000..e0377ce48537
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Embedded Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The Embedded Trace Macrocell (ETM) is a real-time trace module providing
+  instruction and data tracing of a processor.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - arm,coresight-etm3x
+          - arm,coresight-etm4x
+          - arm,coresight-etm4x-sysreg
+  required:
+    - compatible
+
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: arm,coresight-etm4x-sysreg
+    then:
+      $ref: /schemas/arm/primecell.yaml#
+      required:
+        - reg
+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          Embedded Trace Macrocell with memory mapped access.
+        items:

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +91 -0

+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  arm,coresight-loses-context-with-cpu:
+    type: boolean
+    description:
+      Indicates that the hardware will lose register context on CPU power down
+      (e.g. CPUIdle). An example of where this may be needed are systems which
+      contain a coresight component and CPU in the same power domain. When the
+      CPU powers down the coresight component also powers down and loses its
+      context.
+
+  arm,cp14:
+    type: boolean
+    description:
+      Must be present if the system accesses ETM/PTM management registers via
+      co-processor 14.
+
+  qcom,skip-power-up:
+    type: boolean
+    description:
+      Indicates that an implementation can skip powering up the trace unit.
+      TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
+      since ETMs are in the same power domain as their CPU cores. This property
+      is required to identify such systems with hardware errata where the CPU
+      watchdog counter is stopped when TRCPDCR.PU is set.
+
+  cpu:
+    description:
+      phandle to the cpu this ETM is bound to.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: Output connection from the ETM to CoreSight Trace bus.
+        $ref: /schemas/graph.yaml#/properties/port > +
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - cpu
+  - out-ports
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ptm@2201c000 {
+        compatible = "arm,coresight-etm3x", "arm,primecell";
+        reg = <0x2201c000 0x1000>;
+
+        cpu = <&cpu0>;
+        clocks = <&oscclk6a>;
+        clock-names = "apb_pclk";
+        out-ports {
+            port {
+                ptm0_out_port: endpoint {
+                    remote-endpoint = <&funnel_in_port0>;
+                };
+            };
+        };
+    };
+
+    ptm@2201d000 {
+        compatible = "arm,coresight-etm3x", "arm,primecell";
+        reg = <0x2201d000 0x1000>;
+
+        cpu = <&cpu1>;
+        clocks = <&oscclk6a>;
+        clock-names = "apb_pclk";
+        out-ports {
+            port {
+                ptm1_out_port: endpoint {
+                    remote-endpoint = <&funnel_in_port1>;
+                };
+            };
+        };
+    };
+...

Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file +5 -0

new file mode 100644
index 000000000000..b9da30ab9ccd
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

+ compatible = "arm,coresight-static-funnel";

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +7 -0

new file mode 100644
index 000000000000..66ee97370fb2
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Static Trace Bus Replicator

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +31 -0

+        compatible = "arm,coresight-static-replicator";
+
+        out-ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* replicator output ports */
+            port@0 {
+                reg = <0>;
+                replicator_out_port0: endpoint {
+                    remote-endpoint = <&etb_in_port>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                replicator_out_port1: endpoint {
+                    remote-endpoint = <&tpiu_in_port>;
+                };
+            };
+        };
+
+        in-ports {
+            port {
+                replicator_in_port0: endpoint {
+                    remote-endpoint = <&funnel_out_port0>;
+                };
+            };
+        };
+    };
+...

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +37 -0

new file mode 100644
index 000000000000..905008faa012
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight System Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The STM is a trace source that is integrated into a CoreSight system, designed
+  primarily for high-bandwidth trace of instrumentation embedded into software.
+  This instrumentation is made up of memory-mapped writes to the STM Advanced
+  eXtensible Interface (AXI) slave, which carry information about the behavior
+  of the software.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-stm
+  required:
+    - compatible
+
+allOf:

Hi Rob

A big Thank You for the effort ! A minor comment below.

Quoted 41 lines · Rob Herring

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.

Signed-off-by Rob Herring <[email protected]>

--
v2:
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references
- Fix double blank line

---
  .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
  .../bindings/arm/arm,coresight-cti.yaml       |   3 +-
  .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
  .../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
  .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
  .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
  .../arm/arm,coresight-static-funnel.yaml      |  89 ++++
  .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
  .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
  .../bindings/arm/arm,coresight-tmc.yaml       | 131 ++++++
  .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
  .../arm/arm,embedded-trace-extension.yaml     |   1 -
  .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
  Documentation/trace/coresight/coresight.rst   |   2 +-
  MAINTAINERS                                   |   3 +-
  15 files changed, 1106 insertions(+), 408 deletions(-)

create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

...

Quoted 45 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +39 -0

new file mode 100644
index 000000000000..e0377ce48537
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Embedded Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The Embedded Trace Macrocell (ETM) is a real-time trace module providing
+  instruction and data tracing of a processor.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - arm,coresight-etm3x
+          - arm,coresight-etm4x
+          - arm,coresight-etm4x-sysreg
+  required:
+    - compatible
+
+allOf:
+  - if:
+      not:

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml line 47

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +8 -0

+        properties:
+          compatible:
+            contains:
+              const: arm,coresight-etm4x-sysreg
+    then:
+      $ref: /schemas/arm/primecell.yaml#
+      required:
+        - reg

Quoted 13 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +13 -0

+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          Embedded Trace Macrocell with memory mapped access.
+        items:
+          - enum:
+              - arm,coresight-etm3x
+              - arm,coresight-etm4x
+          - const: arm,primecell
+      - description:
+          Embedded Trace Macrocell (version 4.x), with system register access only

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml line 64

Quoted 4 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +4 -0

+        const: arm,coresight-etm4x-sysreg
+
+  reg:
+    maxItems: 1

The register field is mandatory for everything, except arm,coresight-etm4x-sysreg. Is there a way to enforce that selectively for the others ?

Quoted 101 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +90 -0

+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: apb_pclk
+      - const: atclk
+
+  arm,coresight-loses-context-with-cpu:
+    type: boolean
+    description:
+      Indicates that the hardware will lose register context on CPU power down
+      (e.g. CPUIdle). An example of where this may be needed are systems which
+      contain a coresight component and CPU in the same power domain. When the
+      CPU powers down the coresight component also powers down and loses its
+      context.
+
+  arm,cp14:
+    type: boolean
+    description:
+      Must be present if the system accesses ETM/PTM management registers via
+      co-processor 14.
+
+  qcom,skip-power-up:
+    type: boolean
+    description:
+      Indicates that an implementation can skip powering up the trace unit.
+      TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
+      since ETMs are in the same power domain as their CPU cores. This property
+      is required to identify such systems with hardware errata where the CPU
+      watchdog counter is stopped when TRCPDCR.PU is set.
+
+  cpu:
+    description:
+      phandle to the cpu this ETM is bound to.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  out-ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    additionalProperties: false
+
+    properties:
+      port:
+        description: Output connection from the ETM to CoreSight Trace bus.
+        $ref: /schemas/graph.yaml#/properties/port > +
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - cpu
+  - out-ports
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ptm@2201c000 {
+        compatible = "arm,coresight-etm3x", "arm,primecell";
+        reg = <0x2201c000 0x1000>;
+
+        cpu = <&cpu0>;
+        clocks = <&oscclk6a>;
+        clock-names = "apb_pclk";
+        out-ports {
+            port {
+                ptm0_out_port: endpoint {
+                    remote-endpoint = <&funnel_in_port0>;
+                };
+            };
+        };
+    };
+
+    ptm@2201d000 {
+        compatible = "arm,coresight-etm3x", "arm,primecell";
+        reg = <0x2201d000 0x1000>;
+
+        cpu = <&cpu1>;
+        clocks = <&oscclk6a>;
+        clock-names = "apb_pclk";
+        out-ports {
+            port {
+                ptm1_out_port: endpoint {
+                    remote-endpoint = <&funnel_in_port1>;
+                };
+            };
+        };
+    };
+...

Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file +5 -0

new file mode 100644
index 000000000000..b9da30ab9ccd
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

...

Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml line 59

Quoted 12 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml new file +12 -0

+  - compatible
+  - in-ports
+  - out-ports
+
+additionalProperties: false
+
+examples:
+  - |
+    funnel {
+        /* non-configurable replicators don't show up on the
+        * AMBA bus.  As such no need to add "arm,primecell".
+        */

minor nit. Comment styling.

Quoted 1 line

+ compatible = "arm,coresight-static-funnel";

...

Quoted 13 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +7 -0

new file mode 100644
index 000000000000..66ee97370fb2
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Static Trace Bus Replicator

...

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml line 59

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +8 -0

+additionalProperties: false
+
+examples:
+  - |
+    replicator {
+        /* non-configurable replicators don't show up on the
+        * AMBA bus.  As such no need to add "arm,primecell".
+        */

same as above.

Quoted 74 lines

Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml new file +31 -0

+        compatible = "arm,coresight-static-replicator";
+
+        out-ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* replicator output ports */
+            port@0 {
+                reg = <0>;
+                replicator_out_port0: endpoint {
+                    remote-endpoint = <&etb_in_port>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                replicator_out_port1: endpoint {
+                    remote-endpoint = <&tpiu_in_port>;
+                };
+            };
+        };
+
+        in-ports {
+            port {
+                replicator_in_port0: endpoint {
+                    remote-endpoint = <&funnel_out_port0>;
+                };
+            };
+        };
+    };
+...

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +37 -0

new file mode 100644
index 000000000000..905008faa012
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight System Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The STM is a trace source that is integrated into a CoreSight system, designed
+  primarily for high-bandwidth trace of instrumentation embedded into software.
+  This instrumentation is made up of memory-mapped writes to the STM Advanced
+  eXtensible Interface (AXI) slave, which carry information about the behavior
+  of the software.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-stm
+  required:
+    - compatible
+
+allOf:

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml line 47

Quoted 10 lines

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +10 -0

+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-stm
+      - const: arm,primecell
+
+  reg:
+    maxItems: 2

stm-stimulus-base is mandatory for stm. So I believe, we should add

minItems: 2
above ?

Quoted 94 lines · Suzuki K Poulose

Hi Rob

A big Thank You for the effort ! A minor comment below.

Quoted 41 lines · Rob Herring

Each CoreSight component has slightly different requirements and nothing applies to every component, so each CoreSight component has its own schema document.

Signed-off-by Rob Herring <[email protected]>

--
v2:
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references
- Fix double blank line

---
   .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
   .../bindings/arm/arm,coresight-cti.yaml       |   3 +-
   .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
   .../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
   .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
   .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
   .../arm/arm,coresight-static-funnel.yaml      |  89 ++++
   .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
   .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
   .../bindings/arm/arm,coresight-tmc.yaml       | 131 ++++++
   .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
   .../arm/arm,embedded-trace-extension.yaml     |   1 -
   .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
   Documentation/trace/coresight/coresight.rst   |   2 +-
   MAINTAINERS                                   |   3 +-
   15 files changed, 1106 insertions(+), 408 deletions(-)

create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

...

Quoted 45 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +39 -0

new file mode 100644
index 000000000000..e0377ce48537
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight Embedded Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The Embedded Trace Macrocell (ETM) is a real-time trace module providing
+  instruction and data tracing of a processor.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - arm,coresight-etm3x
+          - arm,coresight-etm4x
+          - arm,coresight-etm4x-sysreg
+  required:
+    - compatible
+
+allOf:
+  - if:
+      not:

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml line 47

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +8 -0

+        properties:
+          compatible:
+            contains:
+              const: arm,coresight-etm4x-sysreg
+    then:
+      $ref: /schemas/arm/primecell.yaml#
+      required:
+        - reg

^^^^

Quoted 13 lines

Quoted 13 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +13 -0

+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          Embedded Trace Macrocell with memory mapped access.
+        items:
+          - enum:
+              - arm,coresight-etm3x
+              - arm,coresight-etm4x
+          - const: arm,primecell
+      - description:
+          Embedded Trace Macrocell (version 4.x), with system register access only

Quoted 8 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml line 64

Quoted 4 lines

Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml new file +4 -0

+        const: arm,coresight-etm4x-sysreg
+
+  reg:
+    maxItems: 1

The register field is mandatory for everything, except arm,coresight-etm4x-sysreg. Is there a way to enforce that selectively for the others ?

Yes, that's what it is doing up above that I flagged.

Quoted 56 lines

Quoted 43 lines

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +37 -0

new file mode 100644
index 000000000000..905008faa012
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm CoreSight System Trace MacroCell
+
+maintainers:
+  - Mathieu Poirier <[email protected]>
+  - Mike Leach <[email protected]>
+  - Leo Yan <[email protected]>
+  - Suzuki K Poulose <[email protected]>
+
+description: |
+  CoreSight components are compliant with the ARM CoreSight architecture
+  specification and can be connected in various topologies to suit a particular
+  SoCs tracing needs. These trace components can generally be classified as
+  sinks, links and sources. Trace data produced by one or more sources flows
+  through the intermediate links connecting the source to the currently selected
+  sink.
+
+  The STM is a trace source that is integrated into a CoreSight system, designed
+  primarily for high-bandwidth trace of instrumentation embedded into software.
+  This instrumentation is made up of memory-mapped writes to the STM Advanced
+  eXtensible Interface (AXI) slave, which carry information about the behavior
+  of the software.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: arm,coresight-stm
+  required:
+    - compatible
+
+allOf:

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml line 47

Quoted 10 lines

Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml new file +10 -0

+  - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: arm,coresight-stm
+      - const: arm,primecell
+
+  reg:
+    maxItems: 2

stm-stimulus-base is mandatory for stm. So I believe, we should add

Quoted 2 lines

minItems: 2
above ?

That's the default if not explicit.

Convert the CoreSight CPU debug binding to DT schema format.

Reviewed-by Leo Yan <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Signed-off-by Rob Herring <[email protected]>

This series converts all the CoreSight debug bindings to DT schema format. These bindings are at the top of the list of occurrences of bindings without a schema. For arm64 dts files:

    702 ['arm,coresight-etm4x', 'arm,primecell']
    536 ['arm,coresight-cpu-debug', 'arm,primecell']
    509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
    213 ['arm,coresight-tmc', 'arm,primecell']
    143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
     97 ['arm,coresight-stm', 'arm,primecell']

I'll send a reply to these with the errors in dts files that this causes. I've reviewed them and they all look legit. Xilinx Zynq though has 3 clocks instead of 2.

v2:
- Rename other Coresight bindings to use compatible string for filename
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references

Rob

Rob Herring (3):
dt-bindings: arm: Rename Coresight filenames to match compatible
dt-bindings: arm: Convert CoreSight bindings to DT schema
dt-bindings: arm: Convert CoreSight CPU debug to DT schema

 .../bindings/arm/arm,coresight-catu.yaml      | 101 +++++
 .../bindings/arm/arm,coresight-cpu-debug.yaml |  81 ++++
 ...esight-cti.yaml => arm,coresight-cti.yaml} |   5 +-
 .../arm/arm,coresight-dynamic-funnel.yaml     | 126 ++++++
 .../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
 .../bindings/arm/arm,coresight-etb10.yaml     |  92 ++++
 .../bindings/arm/arm,coresight-etm.yaml       | 156 +++++++
 .../arm/arm,coresight-static-funnel.yaml      |  89 ++++
 .../arm/arm,coresight-static-replicator.yaml  |  90 ++++
 .../bindings/arm/arm,coresight-stm.yaml       | 101 +++++
 .../bindings/arm/arm,coresight-tmc.yaml       | 131 ++++++
 .../bindings/arm/arm,coresight-tpiu.yaml      |  91 ++++
 ...yaml => arm,embedded-trace-extension.yaml} |   3 +-
 ...e.yaml => arm,trace-buffer-extension.yaml} |   2 +-
 .../bindings/arm/coresight-cpu-debug.txt      |  49 ---
 .../devicetree/bindings/arm/coresight.txt     | 402 ------------------
 Documentation/trace/coresight/coresight.rst   |   2 +-
 MAINTAINERS                                   |   8 +-
 18 files changed, 1192 insertions(+), 463 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
 rename Documentation/devicetree/bindings/arm/{coresight-cti.yaml => arm,coresight-cti.yaml} (98%)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
 rename Documentation/devicetree/bindings/arm/{ete.yaml => arm,embedded-trace-extension.yaml} (95%)
 rename Documentation/devicetree/bindings/arm/{trbe.yaml => arm,trace-buffer-extension.yaml} (94%)
 delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
 delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt

--
2.34.1

Hi Rob,

Quoted 15 lines · Rob Herring

This series converts all the CoreSight debug bindings to DT schema format. These bindings are at the top of the list of occurrences of bindings without a schema. For arm64 dts files:

    702 ['arm,coresight-etm4x', 'arm,primecell']
    536 ['arm,coresight-cpu-debug', 'arm,primecell']
    509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
    213 ['arm,coresight-tmc', 'arm,primecell']
    143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
     97 ['arm,coresight-stm', 'arm,primecell']

I'll send a reply to these with the errors in dts files that this causes. I've reviewed them and they all look legit. Xilinx Zynq though has 3 clocks instead of 2.

Quoted 6 lines

v2:
- Rename other Coresight bindings to use compatible string for filename
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references

What a massive undertaking... I have looked scrupulously and everything adds up. Let me know if you were looking for me to pick this up. Otherwise:

Reviewed-by Mathieu Poirier <[email protected]>

Quoted 25 lines · Mathieu Poirier

Hi Rob,

Quoted 21 lines · Rob Herring

This series converts all the CoreSight debug bindings to DT schema format. These bindings are at the top of the list of occurrences of bindings without a schema. For arm64 dts files:

    702 ['arm,coresight-etm4x', 'arm,primecell']
    536 ['arm,coresight-cpu-debug', 'arm,primecell']
    509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
    213 ['arm,coresight-tmc', 'arm,primecell']
    143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
     97 ['arm,coresight-stm', 'arm,primecell']

I'll send a reply to these with the errors in dts files that this causes. I've reviewed them and they all look legit. Xilinx Zynq though has 3 clocks instead of 2.

v2:
- Rename other Coresight bindings to use compatible string for filename
- Add missing arm,coresight-dynamic-replicator.yaml and arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references

Quoted 4 lines

What a massive undertaking... I have looked scrupulously and everything adds up. Let me know if you were looking for me to pick this up. Otherwise:

Reviewed-by Mathieu Poirier <[email protected]>

Can you apply. I think there was another series from QCom touching the MAINTAINERS entry that will conflict.

There's a couple of indentation fixups. Can you fix when applying or do you want me to resend?

Rob