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crypto: sa2ul - Set the supported_algos bits individually

PATCH Superseded Andrew Davis 2 participants 9 messages Jul 5, 2022 – Jul 6, 2022

Subsystems (3)
Device tree bindings Crypto API Arm/Texas Instruments K3 architecture

v1 of 2 Superseded Latest is v2 →

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Andrew Davis

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#0 lore raw

PATCH 1/6 crypto: sa2ul - Set the supported_algos bits individually

Setting these individually gives a better picture of supported functions at a glance. Plus if the list changes an unwanted one will not accidentally get set with GENMASK.

Signed-off-by Andrew Davis <[email protected]>
---
 drivers/crypto/sa2ul.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)
drivers/crypto/sa2ul.c +9 -1
index 6957a125b4470..1d732113b81ec 100644
@@ -2361,7 +2361,15 @@ static int sa_link_child(struct device *dev, void *data)
 static struct sa_match_data am654_match_data = {
 	.priv = 1,
 	.priv_id = 1,
-	.supported_algos = GENMASK(SA_ALG_AUTHENC_SHA256_AES, 0),
+	.supported_algos = BIT(SA_ALG_CBC_AES) |
+			   BIT(SA_ALG_EBC_AES) |
+			   BIT(SA_ALG_CBC_DES3) |
+			   BIT(SA_ALG_ECB_DES3) |
+			   BIT(SA_ALG_SHA1) |
+			   BIT(SA_ALG_SHA256) |
+			   BIT(SA_ALG_SHA512) |
+			   BIT(SA_ALG_AUTHENC_SHA1_AES) |
+			   BIT(SA_ALG_AUTHENC_SHA256_AES),
 };
 
 static struct sa_match_data am64_match_data = {
Signature · 1 line
2.36.1
author
#1 lore raw

PATCH 2/6 crypto: sa2ul - Check engine status before enabling

There is a engine status register that can be used to check if the different HW crypto engines are enabled. Check that first and then only try to enable the engines if they are not already on.

This has a couple benefits. First we don't need to use match_data for this. Second, this driver can now work on HS devices where the engine control registers are read-only and writing causes a firewall exception.

Signed-off-by Andrew Davis <[email protected]>
---
 drivers/crypto/sa2ul.c | 15 +++++++--------
 drivers/crypto/sa2ul.h |  1 +
 2 files changed, 8 insertions(+), 8 deletions(-)
drivers/crypto/sa2ul.c +7 -8
index 1d732113b81ec..f4bc06c24ad8f 100644
@@ -86,7 +86,6 @@ struct sa_match_data {
 	u8 priv;
 	u8 priv_id;
 	u32 supported_algos;
-	bool skip_engine_control;
 };
 
 static struct device *sa_k3_dev;

@@ -2380,7 +2379,6 @@ static struct sa_match_data am64_match_data = {
 			   BIT(SA_ALG_SHA256) |
 			   BIT(SA_ALG_SHA512) |
 			   BIT(SA_ALG_AUTHENC_SHA256_AES),
-	.skip_engine_control = true,
 };
 
 static const struct of_device_id of_match[] = {

@@ -2398,6 +2396,7 @@ static int sa_ul_probe(struct platform_device *pdev)
 	struct device_node *node = dev->of_node;
 	static void __iomem *saul_base;
 	struct sa_crypto_data *dev_data;
+	u32 status, val;
 	int ret;
 
 	dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);

@@ -2434,13 +2433,13 @@ static int sa_ul_probe(struct platform_device *pdev)
 
 	spin_lock_init(&dev_data->scid_lock);
 
-	if (!dev_data->match_data->skip_engine_control) {
-		u32 val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN |
-			  SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN |
-			  SA_EEC_TRNG_EN;
-
+	val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN |
+	      SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN |
+	      SA_EEC_TRNG_EN;
+	status = readl_relaxed(saul_base + SA_ENGINE_STATUS);
+	/* Only enable engines if all are not already enabled */
+	if (val & ~status)
 		writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL);
-	}
 
 	sa_register_algos(dev_data);
drivers/crypto/sa2ul.h +1 -0
index ed66d1f111db5..92bf97232a292 100644
@@ -16,6 +16,7 @@
 #include <crypto/sha1.h>
 #include <crypto/sha2.h>
 
+#define SA_ENGINE_STATUS		0x0008
 #define SA_ENGINE_ENABLE_CONTROL	0x1000
 
 struct sa_tfm_ctx;
Signature · 1 line
2.36.1
author
#2 lore raw

PATCH 3/6 arm64: dts: ti: k3-am65-main: Disable RNG node

In reply to Andrew Davis

The hardware random number generator is used by OP-TEE and is access is denied to other users with SoC level bus firewalls. Any access to this device from Linux will result in firewall errors. Disable this node.

Signed-off-by Andrew Davis <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +1 -0
index e749343accedd..113e959ba06d0 100644
@@ -127,6 +127,7 @@ rng: rng@4e10000 {
 			reg = <0x0 0x4e10000 0x0 0x7d>;
 			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&k3_clks 136 1>;
+			status = "disabled";
 		};
 	};
Signature · 1 line
2.36.1
author
#3 lore raw

PATCH 4/6 arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID

In reply to Andrew Davis

The first TX and first two RX PSI-L threads for SA2UL are used by SYSFW on High Security(HS) devices. Use the next available threads to prevent resource allocation conflicts.

Signed-off-by Andrew Davis <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +2 -2
index 113e959ba06d0..2b0bac89b23f2 100644
@@ -117,8 +117,8 @@ crypto: crypto@4e00000 {
 		#size-cells = <2>;
 		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
 
-		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
-				<&main_udmap 0x4001>;
+		dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
+				<&main_udmap 0x4003>;
 		dma-names = "tx", "rx1", "rx2";
 		dma-coherent;
Signature · 1 line
2.36.1
author
#4 lore raw

PATCH 5/6 arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL

In reply to Andrew Davis

The SA2UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail.

Signed-off-by Andrew Davis <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +1 -1
index 2b0bac89b23f2..8f9c6282e8925 100644
@@ -112,7 +112,7 @@ main_uart2: serial@2820000 {
 	crypto: crypto@4e00000 {
 		compatible = "ti,am654-sa2ul";
 		reg = <0x0 0x4e00000 0x0 0x1200>;
-		power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+		power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
Signature · 1 line
2.36.1
author
#5 lore raw

PATCH 6/6 arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node

In reply to Andrew Davis

J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.

Signed-off-by Andrew Davis <[email protected]>
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +20 -0
index 1044ec6c4b0d4..ebad3642c8e30 100644
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
 			ti,loczrama = <1>;
 		};
 	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
 };
Signature · 1 line
2.36.1
maintainer
#6 lore raw

Re: [PATCH 6/6] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node

Quoted 7 lines · Andrew Davis

J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.

Signed-off-by Andrew Davis <[email protected]>
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

Please split this series into what crypto maintainers need to pick up vs what I need to pick up for dts. patches for my tree need to have lakml in cc as a rule (see MAINTAINERS file).

Quoted 16 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +7 -0
index 1044ec6c4b0d4..ebad3642c8e30 100644
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
 			ti,loczrama = <1>;
 		};
 	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi mcu_r5fss0_core1: r5f@41400000 { · line 394

Quoted 10 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +10 -0
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;

Please document why disabled.

Quoted 7 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +3 -0
+			status = "disabled";
+		};
+	};
 };
Signature · 1 line
2.36.1
Signature · 3 lines
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
author
#7 lore raw

Re: [PATCH 6/6] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node

Quoted 4 lines · Nishanth Menon
Quoted 3 lines · Andrew Davis

J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.

Quoted 9 lines
Quoted 4 lines
Signed-off-by Andrew Davis <[email protected]>
---
  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
  1 file changed, 20 insertions(+)

Please split this series into what crypto maintainers need to pick up vs what I need to pick up for dts. patches for my tree need to have lakml in cc as a rule (see MAINTAINERS file).

Okay, I'll break the first two into their own series. Adding LAKML folks for v2.

Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +11 -0
index 1044ec6c4b0d4..ebad3642c8e30 100644
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
  			ti,loczrama = <1>;
  		};
  	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
Quoted 9 lines

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi mcu_r5fss0_core1: r5f@41400000 { · line 394

Quoted 6 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +6 -0
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;

Please document why disabled.

Sure thing, will add background info to the commit message.

Thanks,
Andrew

Quoted 8 lines
Quoted 7 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +3 -0
+			status = "disabled";
+		};
+	};
  };
Signature · 1 line
2.36.1
maintainer
#8 lore raw

Re: [PATCH 6/6] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node

Quoted 20 lines · Andrew Davis
Quoted 10 lines
Quoted 10 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +10 -0
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
Quoted 9 lines

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi mcu_r5fss0_core1: r5f@41400000 { · line 394

Quoted 6 lines
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +6 -0
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;

Please document why disabled.

Quoted 1 line

Sure thing, will add background info to the commit message.

I'd suggest to document in dts as well. See thread [1]

[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/

Signature · 3 lines
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D